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1. 发明申请

US20100095300A1 Online Computation of Cache Occupancy and Performance 有权
标题翻译：缓存占用率和性能的在线计算
公开(公告)号：US20100095300A1
公开(公告)日：2010-04-15
申请号：US12251108
申请日：2008-10-14
申请人： Richard West , Puneet Zaroo , Carl A. Waldspurger , Xiao Zhang , Haoqiang Zheng
发明人： Richard West , Puneet Zaroo , Carl A. Waldspurger , Xiao Zhang , Haoqiang Zheng
IPC分类号： G06F9/50 , G06F9/46
CPC分类号： G06F9/50 , G06F9/5005 , G06F9/5011 , G06F9/5016 , G06F9/5022 , G06F9/5027 , G06F9/5033 , G06F9/5044 , G06F9/505 , G06F9/5055 , G06F11/3409 , G06F11/3442 , G06F11/3452 , G06F11/3466 , G06F12/08 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0815 , G06F12/084 , G06F2201/88
摘要： Methods, computer programs, and systems for managing thread performance in a computing environment based on cache occupancy are provided. In one embodiment, a computer implemented method assigns a thread performance counter to threads being created to measure the number of cache misses for the threads. The thread performance counter is deduced in one embodiment based on performance counters associated with each core in a processor. The method further calculates a self-thread value as the change in the thread performance counter of a given thread during a predetermined period, and an other-thread value as the sum of all the changes in the thread performance counters for all threads except for the given thread. Further, the method estimates a cache occupancy for the given thread based on a previous occupancy for the given thread, and the calculated shelf-thread and other-thread values. The estimated cache occupancy is used to assign computing environment resources to the given thread. In another embodiment, cache miss-rate curves are constructed for a thread to help analyze performance tradeoffs when changing cache allocations of the threads in the system.
摘要翻译：提供了基于缓存占用的用于在计算环境中管理线程性能的方法，计算机程序和系统。在一个实施例中，计算机实现的方法为正在创建的线程分配线程性能计数器以测量线程的高速缓存未命中的数量。基于与处理器中的每个核心相关联的性能计数器，在一个实施例中推导出线程性能计数器。该方法进一步计算自线程值作为在预定时段期间给定线程的线程性能计数器的变化，而另一线程值作为所有线程的线程性能计数器的所有变化之和除外给线程此外，该方法基于给定线程的先前占用以及所计算的架线和其他线程值来估计给定线程的高速缓存占用。估计的高速缓存占用率用于将计算环境资源分配给给定的线程。在另一个实施例中，为线程构建高速缓存未命中率曲线，以帮助在改变系统中的线程的高速缓存分配时分析性能权衡。

2. 发明授权

US09396024B2 Online computation of cache occupancy and performance 有权
标题翻译：在线计算缓存占用率和性能
公开(公告)号：US09396024B2
公开(公告)日：2016-07-19
申请号：US12251108
申请日：2008-10-14
申请人： Richard West , Puneet Zaroo , Carl A. Waldspurger , Xiao Zhang , Haoqiang Zheng
发明人： Richard West , Puneet Zaroo , Carl A. Waldspurger , Xiao Zhang , Haoqiang Zheng
IPC分类号： G06F9/46 , G06F13/00 , G06F13/28 , G06F9/50 , G06F12/08 , G06F11/34
CPC分类号： G06F9/50 , G06F9/5005 , G06F9/5011 , G06F9/5016 , G06F9/5022 , G06F9/5027 , G06F9/5033 , G06F9/5044 , G06F9/505 , G06F9/5055 , G06F11/3409 , G06F11/3442 , G06F11/3452 , G06F11/3466 , G06F12/08 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0815 , G06F12/084 , G06F2201/88
摘要： Methods, computer programs, and systems for managing thread performance in a computing environment based on cache occupancy are provided. In one embodiment, a computer implemented method assigns a thread performance counter to threads being created to measure the number of cache misses for the threads. The thread performance counter is deduced in one embodiment based on performance counters associated with each core in a processor. The method further calculates a self-thread value as the change in the thread performance counter of a given thread during a predetermined period, and an other-thread value as the sum of all the changes in the thread performance counters for all threads except for the given thread. Further, the method estimates a cache occupancy for the given thread based on a previous occupancy for the given thread, and the calculated shelf-thread and other-thread values. The estimated cache occupancy is used to assign computing environment resources to the given thread. In another embodiment, cache miss-rate curves are constructed for a thread to help analyze performance tradeoffs when changing cache allocations of the threads in the system.
摘要翻译：提供了基于缓存占用的用于在计算环境中管理线程性能的方法，计算机程序和系统。在一个实施例中，计算机实现的方法为正在创建的线程分配线程性能计数器以测量线程的高速缓存未命中的数量。基于与处理器中的每个核心相关联的性能计数器，在一个实施例中推导出线程性能计数器。该方法进一步计算自线程值作为在预定时段期间给定线程的线程性能计数器的变化，而另一线程值作为所有线程的线程性能计数器的所有变化之和除外给线程此外，该方法基于给定线程的先前占用以及所计算的架线和其他线程值来估计给定线程的高速缓存占用。估计的高速缓存占用率用于将计算环境资源分配给给定的线程。在另一个实施例中，为线程构建高速缓存未命中率曲线，以帮助在改变系统中的线程的高速缓存分配时分析性能权衡。

3. 发明授权

US09244732B2 Compensating threads for microarchitectural resource contentions by prioritizing scheduling and execution 有权
标题翻译：通过优先安排和执行来补偿微体系结构资源争用的线程
公开(公告)号：US09244732B2
公开(公告)日：2016-01-26
申请号：US12550193
申请日：2009-08-28
申请人： Richard West , Puneet Zaroo , Carl A. Waldspurger , Xiao Zhang
发明人： Richard West , Puneet Zaroo , Carl A. Waldspurger , Xiao Zhang
IPC分类号： G06F9/48 , G06F11/34 , G06F12/08
CPC分类号： G06F9/4881 , G06F9/48 , G06F11/3409 , G06F12/0842 , G06F2209/485 , G06F2209/486
摘要： A thread (or other resource consumer) is compensated for contention for system resources in a computer system having at least one processor core, a last level cache (LLC), and a main memory. In one embodiment, at each descheduling event of the thread following an execution interval, an effective CPU time is determined. The execution interval is a period of time during which the thread is being executed on the central processing unit (CPU) between scheduling events. The effective CPU time is a portion of the execution interval that excludes delays caused by contention for microarchitectural resources, such as time spent repopulating lines from the LLC that were evicted by other threads. The thread may be compensated for microarchitectural contention by increasing its scheduling priority based on the effective CPU time.
摘要翻译：对具有至少一个处理器核心，最后一级缓存（LLC）和主存储器的计算机系统中的系统资源的竞争进行补偿的线程（或其他资源消费者）。在一个实施例中，在执行间隔之后的线程的每个调度事件处，确定有效的CPU时间。执行间隔是在调度事件之间的中央处理单元（CPU）上执行线程的时间段。有效CPU时间是执行间隔的一部分，排除了由微型架构资源的争用引起的延迟，例如，重新生成由其他线程驱逐的LLC的线路所花费的时间。可以通过根据有效CPU时间增加其调度优先级来对线程进行微架构争用补偿。

4. 发明授权

US08429665B2 Cache performance prediction, partitioning and scheduling based on cache pressure of threads 有权
标题翻译：基于线程缓存压力的缓存性能预测，分区和调度
公开(公告)号：US08429665B2
公开(公告)日：2013-04-23
申请号：US12727705
申请日：2010-03-19
申请人： Puneet Zaroo , Richard West , Carl A. Waldspurger , Xiao Zhang
发明人： Puneet Zaroo , Richard West , Carl A. Waldspurger , Xiao Zhang
IPC分类号： G06F9/50
CPC分类号： G06F9/48 , G06F9/4881 , G06F9/50 , G06F9/5005 , G06F9/5011 , G06F9/5016 , G06F9/5022 , G06F9/5027 , G06F9/5033 , G06F9/5044 , G06F9/505 , G06F9/5055 , G06F11/3409 , G06F11/3442 , G06F11/3452 , G06F11/3466 , G06F12/08 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0815 , G06F12/084 , G06F2201/88 , G06F2209/483 , G06F2209/501
摘要： A method is described for scheduling in an intelligent manner a plurality of threads on a processor having a plurality of cores and a shared last level cache (LLC). In the method, a first and second scenario having a corresponding first and second combination of threads are identified. The cache occupancies of each of the threads for each of the scenarios are predicted. The predicted cache occupancies being a representation of an amount of the LLC that each of the threads would occupy when running with the other threads on the processor according to the particular scenario. One of the scenarios is identified that results in the least objectionable impacts on all threads, the least objectionable impacts taking into account the impact resulting from the predicted cache occupancies. Finally, a scheduling decision is made according to the one of the scenarios that results in the least objectionable impacts.
摘要翻译：描述了一种以智能方式调度具有多个核的处理器上的多个线程和共享的最后一级高速缓存（LLC）的方法。在该方法中，识别具有对应的第一和第二线程组合的第一和第二情景。预测每个场景的每个线程的高速缓存占用。预测的高速缓存占用是根据特定场景与处理器上的其他线程一起运行时每个线程将占用的LLC的量的表示。确定了一种情景，对所有线程造成的影响最小，最不令人反感的影响考虑到预测的缓存占用引起的影响。最后，根据导致最不利影响的情景之一进行调度决策。

5. 发明申请

US20110231857A1 CACHE PERFORMANCE PREDICTION AND SCHEDULING ON COMMODITY PROCESSORS WITH SHARED CACHES 有权
标题翻译：具有共享速度的商品处理器的缓存性能预测和调度
公开(公告)号：US20110231857A1
公开(公告)日：2011-09-22
申请号：US12727705
申请日：2010-03-19
申请人： Puneet Zaroo , Richard West , Carl A. Waldspurger , Xiao Zhang
发明人： Puneet Zaroo , Richard West , Carl A. Waldspurger , Xiao Zhang
IPC分类号： G06F9/50 , G06F9/46
CPC分类号： G06F9/48 , G06F9/4881 , G06F9/50 , G06F9/5005 , G06F9/5011 , G06F9/5016 , G06F9/5022 , G06F9/5027 , G06F9/5033 , G06F9/5044 , G06F9/505 , G06F9/5055 , G06F11/3409 , G06F11/3442 , G06F11/3452 , G06F11/3466 , G06F12/08 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0815 , G06F12/084 , G06F2201/88 , G06F2209/483 , G06F2209/501
摘要： A method is described for scheduling in an intelligent manner a plurality of threads on a processor having a plurality of cores and a shared last level cache (LLC). In the method, a first and second scenario having a corresponding first and second combination of threads are identified. The cache occupancies of each of the threads for each of the scenarios are predicted. The predicted cache occupancies being a representation of an amount of the LLC that each of the threads would occupy when running with the other threads on the processor according to the particular scenario. One of the scenarios is identified that results in the least objectionable impacts on all threads, the least objectionable impacts taking into account the impact resulting from the predicted cache occupancies. Finally, a scheduling decision is made according to the one of the scenarios that results in the least objectionable impacts.
摘要翻译：描述了一种以智能方式调度具有多个核的处理器上的多个线程和共享的最后一级高速缓存（LLC）的方法。在该方法中，识别具有对应的第一和第二线程组合的第一和第二情景。预测每个场景的每个线程的高速缓存占用。预测的高速缓存占用是根据特定场景与处理器上的其他线程一起运行时每个线程将占用的LLC的量的表示。确定了一种情景，对所有线程造成的影响最小，最不令人反感的影响考虑到预测的缓存占用引起的影响。最后，根据导致最不利影响的情景之一进行调度决策。

6. 发明申请

US20110055479A1 Thread Compensation For Microarchitectural Contention 有权
标题翻译：微架构竞争线程补偿
公开(公告)号：US20110055479A1
公开(公告)日：2011-03-03
申请号：US12550193
申请日：2009-08-28
申请人： Richard West , Puneet Zaroo , Carl A. Waldspurger , Xiao Zhang
发明人： Richard West , Puneet Zaroo , Carl A. Waldspurger , Xiao Zhang
IPC分类号： G06F9/46 , G06F12/08
CPC分类号： G06F9/4881 , G06F9/48 , G06F11/3409 , G06F12/0842 , G06F2209/485 , G06F2209/486
摘要： A thread (or other resource consumer) is compensated for contention for system resources in a computer system having at least one processor core, a last level cache (LLC), and a main memory. In one embodiment, at each descheduling event of the thread following an execution interval, an effective CPU time is determined. The execution interval is a period of time during which the thread is being executed on the central processing unit (CPU) between scheduling events. The effective CPU time is a portion of the execution interval that excludes delays caused by contention for microarchitectural resources, such as time spent repopulating lines from the LLC that were evicted by other threads. The thread may be compensated for microarchitectural contention by increasing its scheduling priority based on the effective CPU time.
摘要翻译：对具有至少一个处理器核心，最后一级缓存（LLC）和主存储器的计算机系统中的系统资源的竞争进行补偿的线程（或其他资源消费者）。在一个实施例中，在执行间隔之后的线程的每个调度事件处，确定有效的CPU时间。执行间隔是在调度事件之间的中央处理单元（CPU）上执行线程的时间段。有效CPU时间是执行间隔的一部分，排除了由微型架构资源的争用引起的延迟，例如，重新生成由其他线程驱逐的LLC的线路所花费的时间。可以通过根据有效CPU时间增加其调度优先级来对线程进行微架构争用补偿。

7. 发明申请

US20070239589A1 Interest rate derivative financial product 审中-公开
标题翻译：利率衍生金融产品
公开(公告)号：US20070239589A1
公开(公告)日：2007-10-11
申请号：US11394465
申请日：2006-03-31
申请人： Donald Wilson , Dominic Cairo , David Hrencecin , Richard West
发明人： Donald Wilson , Dominic Cairo , David Hrencecin , Richard West
IPC分类号： G06Q40/00
CPC分类号： G06Q40/04
摘要： In accordance with the principles of the present invention, a standardized contract is traded. The contract obligates a buyer and a seller to settle the contract based on a price determined for an effective date. The contract is traded over-the-counter or through an exchange and cleared by a clearinghouse that guarantees payment to the buyer of any amount owed to the buyer from the seller as a result of the contract and that guarantees payment to the seller of any amount owed to the seller from the buyer as a result of the contract. An over-the-counter or exchange traded instrument is utilized to determine the rate that is used to determine the price of the contract.
摘要翻译：根据本发明的原则，交易标准合同。合同规定买方和卖方按照生效日期确定的价格结算合同。合同交易在柜台上或通过交易所进行交易，并通过结算所清算，确保由于合同而向卖方向买方支付欠卖方的任何金额，并保证向卖方支付任何金额由于合同而由买方欠卖方。采用非处方或交易所交易工具确定用于确定合同价格的利率。

8. 发明授权

US06344020B1 Bearing and umbilicus gimbal with bearing retainer in blood processing system 失效
标题翻译：轴承和脐带万向架与血液处理系统中的轴承保持架
公开(公告)号：US06344020B1
公开(公告)日：2002-02-05
申请号：US09455203
申请日：1999-12-06
申请人： Douglas Reitz , Ying-Cheng Lo , John Joseph Belle , Richard West , Timothy Patno
发明人： Douglas Reitz , Ying-Cheng Lo , John Joseph Belle , Richard West , Timothy Patno
IPC分类号： B04B700
CPC分类号： F16C33/44 , B04B5/0442 , B04B2005/045 , B04B2005/0492 , F16C23/084 , F16C33/41
摘要： A bearing supports a rotating element. The bearing comprises an inner annular body and an outer annular body about the inner annular body. A bearing surface, which is located between the inner annular body and the outer annular body, supports the outer annular body for rotation about the inner annular body. A cage supports the bearing surface during rotation of the outer annular body about the inner annular body. The cage includes a material that imparts increased flexural modulus that resists deformation during rotation.
摘要翻译：轴承支撑旋转元件。轴承包括内环形体和围绕内环形体的外环形体。位于内部环形体和外部环形体之间的支承表面支撑外部环形体以围绕内部环形体旋转。在外环形体围绕内环形体旋转期间，保持架支撑轴承表面。笼子包括赋予旋转时抵抗变形的增加的弯曲模量的材料。

9. 发明授权

US4023006A Plasma arc welding method 失效
标题翻译：等离子弧焊法
公开(公告)号：US4023006A
公开(公告)日：1977-05-10
申请号：US533174
申请日：1974-12-16
申请人： Richard West , Donald Leslie Amos Weston
发明人： Richard West , Donald Leslie Amos Weston
IPC分类号： B23K10/00 , B23K9/16 , B23K9/10 , H01J7/24
CPC分类号： B23K10/006
摘要： A method of operating a plasma welding apparatus producing a plasma arc and having valve means arranged to control gas flow for the plasma arc and power supply means arranged to control welding current for the plasma arc, wherein the plasma arc current, gas flow to the plasma arc and the feed of a filler material to the arc are coordinated for producing a weld. The gas flow and welding current are maintained at a steady rate during the weld run. The gas flow is reduced at a constant rate to a minimum valve of about 30 % of the steady flow rate at the conclusion of the welding run and the welding current is subsequently reduced at a constant rate from the steady value of the welding current. At the start of the weld run, the gas flow is initiated at a rate of about 50 % of the steady flow rate, the plasma arc current is initiated and is increased at a constant rate to the steady value from an initial value sufficient to strike the arc and the gas flow is increased at a constant flow rate to the steady flow rate as soon as the plasma arc has established a keyhole. The feed of filler material is at a constant rate and is initiated immediately before the plasma arc has established the keyhole and continued until the welding current decreases by substantially 20 % from its steady value.
摘要翻译：一种操作产生等离子体电弧的等离子体焊接装置的方法，具有设置成控制用于等离子体电弧和供电装置的气流的阀装置，该等离子焊接装置被布置成控制等离子体电弧的焊接电流，其中等离子弧电流，等离子体中的气体流将电弧和填充材料进给到电弧进行协调以产生焊接。在焊接运行期间，气流和焊接电流保持稳定。在焊接运行结束时，气体流量以恒定速率减小到约30％的稳定流量的最小阀，并且焊接电流随后以恒定的速率从焊接电流的稳定值减小。在焊接运行开始时，气体流量以稳定流速的约50％的速率启动，等离子体电弧电流被启动，并以恒定的速率增加到从足以触发的初始值的稳定值一旦等离子体电弧建立了键孔，电弧和气体流量就以恒定的流量增加到稳定的流量。填充材料的进料为恒定速率，并且在等离子体电弧已经建立了钥匙孔之前立即开始，并持续到焊接电流从其稳定值下降大约20％。

10. 发明申请

US20190224554A1 QUARTERBACK TRAINING DEVICE 审中-公开
公开(公告)号：US20190224554A1
公开(公告)日：2019-07-25
申请号：US16253139
申请日：2019-01-21
申请人： Richard West , Guy Grover
发明人： Richard West , Guy Grover
IPC分类号： A63B69/40 , A63B69/00
摘要： A quarterback training device is an electric football launcher that is able to mimic the snap of a center as performed during a football game and to place a spin on the launched ball. The speed of the launch is adjustable via a remote control and the device provides for a handoff shelf to be attached.

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