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1. 发明申请

US20100095300A1 Online Computation of Cache Occupancy and Performance 有权
标题翻译：缓存占用率和性能的在线计算
公开(公告)号：US20100095300A1
公开(公告)日：2010-04-15
申请号：US12251108
申请日：2008-10-14
申请人： Richard West , Puneet Zaroo , Carl A. Waldspurger , Xiao Zhang , Haoqiang Zheng
发明人： Richard West , Puneet Zaroo , Carl A. Waldspurger , Xiao Zhang , Haoqiang Zheng
IPC分类号： G06F9/50 , G06F9/46
CPC分类号： G06F9/50 , G06F9/5005 , G06F9/5011 , G06F9/5016 , G06F9/5022 , G06F9/5027 , G06F9/5033 , G06F9/5044 , G06F9/505 , G06F9/5055 , G06F11/3409 , G06F11/3442 , G06F11/3452 , G06F11/3466 , G06F12/08 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0815 , G06F12/084 , G06F2201/88
摘要： Methods, computer programs, and systems for managing thread performance in a computing environment based on cache occupancy are provided. In one embodiment, a computer implemented method assigns a thread performance counter to threads being created to measure the number of cache misses for the threads. The thread performance counter is deduced in one embodiment based on performance counters associated with each core in a processor. The method further calculates a self-thread value as the change in the thread performance counter of a given thread during a predetermined period, and an other-thread value as the sum of all the changes in the thread performance counters for all threads except for the given thread. Further, the method estimates a cache occupancy for the given thread based on a previous occupancy for the given thread, and the calculated shelf-thread and other-thread values. The estimated cache occupancy is used to assign computing environment resources to the given thread. In another embodiment, cache miss-rate curves are constructed for a thread to help analyze performance tradeoffs when changing cache allocations of the threads in the system.
摘要翻译：提供了基于缓存占用的用于在计算环境中管理线程性能的方法，计算机程序和系统。在一个实施例中，计算机实现的方法为正在创建的线程分配线程性能计数器以测量线程的高速缓存未命中的数量。基于与处理器中的每个核心相关联的性能计数器，在一个实施例中推导出线程性能计数器。该方法进一步计算自线程值作为在预定时段期间给定线程的线程性能计数器的变化，而另一线程值作为所有线程的线程性能计数器的所有变化之和除外给线程此外，该方法基于给定线程的先前占用以及所计算的架线和其他线程值来估计给定线程的高速缓存占用。估计的高速缓存占用率用于将计算环境资源分配给给定的线程。在另一个实施例中，为线程构建高速缓存未命中率曲线，以帮助在改变系统中的线程的高速缓存分配时分析性能权衡。

2. 发明授权

US09396024B2 Online computation of cache occupancy and performance 有权
标题翻译：在线计算缓存占用率和性能
公开(公告)号：US09396024B2
公开(公告)日：2016-07-19
申请号：US12251108
申请日：2008-10-14
申请人： Richard West , Puneet Zaroo , Carl A. Waldspurger , Xiao Zhang , Haoqiang Zheng
发明人： Richard West , Puneet Zaroo , Carl A. Waldspurger , Xiao Zhang , Haoqiang Zheng
IPC分类号： G06F9/46 , G06F13/00 , G06F13/28 , G06F9/50 , G06F12/08 , G06F11/34
CPC分类号： G06F9/50 , G06F9/5005 , G06F9/5011 , G06F9/5016 , G06F9/5022 , G06F9/5027 , G06F9/5033 , G06F9/5044 , G06F9/505 , G06F9/5055 , G06F11/3409 , G06F11/3442 , G06F11/3452 , G06F11/3466 , G06F12/08 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0815 , G06F12/084 , G06F2201/88
摘要： Methods, computer programs, and systems for managing thread performance in a computing environment based on cache occupancy are provided. In one embodiment, a computer implemented method assigns a thread performance counter to threads being created to measure the number of cache misses for the threads. The thread performance counter is deduced in one embodiment based on performance counters associated with each core in a processor. The method further calculates a self-thread value as the change in the thread performance counter of a given thread during a predetermined period, and an other-thread value as the sum of all the changes in the thread performance counters for all threads except for the given thread. Further, the method estimates a cache occupancy for the given thread based on a previous occupancy for the given thread, and the calculated shelf-thread and other-thread values. The estimated cache occupancy is used to assign computing environment resources to the given thread. In another embodiment, cache miss-rate curves are constructed for a thread to help analyze performance tradeoffs when changing cache allocations of the threads in the system.
摘要翻译：提供了基于缓存占用的用于在计算环境中管理线程性能的方法，计算机程序和系统。在一个实施例中，计算机实现的方法为正在创建的线程分配线程性能计数器以测量线程的高速缓存未命中的数量。基于与处理器中的每个核心相关联的性能计数器，在一个实施例中推导出线程性能计数器。该方法进一步计算自线程值作为在预定时段期间给定线程的线程性能计数器的变化，而另一线程值作为所有线程的线程性能计数器的所有变化之和除外给线程此外，该方法基于给定线程的先前占用以及所计算的架线和其他线程值来估计给定线程的高速缓存占用。估计的高速缓存占用率用于将计算环境资源分配给给定的线程。在另一个实施例中，为线程构建高速缓存未命中率曲线，以帮助在改变系统中的线程的高速缓存分配时分析性能权衡。

3. 发明授权

US09244732B2 Compensating threads for microarchitectural resource contentions by prioritizing scheduling and execution 有权
标题翻译：通过优先安排和执行来补偿微体系结构资源争用的线程
公开(公告)号：US09244732B2
公开(公告)日：2016-01-26
申请号：US12550193
申请日：2009-08-28
申请人： Richard West , Puneet Zaroo , Carl A. Waldspurger , Xiao Zhang
发明人： Richard West , Puneet Zaroo , Carl A. Waldspurger , Xiao Zhang
IPC分类号： G06F9/48 , G06F11/34 , G06F12/08
CPC分类号： G06F9/4881 , G06F9/48 , G06F11/3409 , G06F12/0842 , G06F2209/485 , G06F2209/486
摘要： A thread (or other resource consumer) is compensated for contention for system resources in a computer system having at least one processor core, a last level cache (LLC), and a main memory. In one embodiment, at each descheduling event of the thread following an execution interval, an effective CPU time is determined. The execution interval is a period of time during which the thread is being executed on the central processing unit (CPU) between scheduling events. The effective CPU time is a portion of the execution interval that excludes delays caused by contention for microarchitectural resources, such as time spent repopulating lines from the LLC that were evicted by other threads. The thread may be compensated for microarchitectural contention by increasing its scheduling priority based on the effective CPU time.
摘要翻译：对具有至少一个处理器核心，最后一级缓存（LLC）和主存储器的计算机系统中的系统资源的竞争进行补偿的线程（或其他资源消费者）。在一个实施例中，在执行间隔之后的线程的每个调度事件处，确定有效的CPU时间。执行间隔是在调度事件之间的中央处理单元（CPU）上执行线程的时间段。有效CPU时间是执行间隔的一部分，排除了由微型架构资源的争用引起的延迟，例如，重新生成由其他线程驱逐的LLC的线路所花费的时间。可以通过根据有效CPU时间增加其调度优先级来对线程进行微架构争用补偿。

4. 发明授权

US08694728B2 Efficient online construction of miss rate curves 有权
标题翻译：有效率在线构建失误率曲线
公开(公告)号：US08694728B2
公开(公告)日：2014-04-08
申请号：US12942765
申请日：2010-11-09
申请人： Carl A. Waldspurger , Rajesh Venkatasubramanian , Alexander Thomas Garthwaite , Yury Baskakov , Puneet Zaroo
发明人： Carl A. Waldspurger , Rajesh Venkatasubramanian , Alexander Thomas Garthwaite , Yury Baskakov , Puneet Zaroo
IPC分类号： G06F12/00
CPC分类号： G06F12/122 , G06F9/45558 , G06F11/3471 , G06F12/123 , G06F2009/45583 , G06F2201/815 , G06F2201/88
摘要： Miss rate curves are constructed in a resource-efficient manner so that they can be constructed and memory management decisions can be made while the workloads are running. The resource-efficient technique includes the steps of selecting a subset of memory pages for the workload, maintaining a least recently used (LRU) data structure for the selected memory pages, detecting accesses to the selected memory pages and updating the LRU data structure in response to the detected accesses, and generating data for constructing a miss-rate curve for the workload using the LRU data structure. After a memory page is accessed, the memory page may be left untraced for a period of time, after which the memory page is retraced.
摘要翻译：错误率曲线以资源有效的方式构建，以便可以构建它们，并且可以在工作负载运行时进行内存管理决策。资源有效的技术包括以下步骤：为工作负载选择存储器页面的子集，维护所选择的存储器页面的最近最少使用的（LRU）数据结构，检测对所选择的存储器页面的访问以及响应地更新LRU数据结构并且使用LRU数据结构生成用于构建工作负载的错过率曲线的数据。在访问存储器页面之后，存储器页面可以保持未被跟踪一段时间，之后再回读存储器页面。

5. 发明授权

US08429665B2 Cache performance prediction, partitioning and scheduling based on cache pressure of threads 有权
标题翻译：基于线程缓存压力的缓存性能预测，分区和调度
公开(公告)号：US08429665B2
公开(公告)日：2013-04-23
申请号：US12727705
申请日：2010-03-19
申请人： Puneet Zaroo , Richard West , Carl A. Waldspurger , Xiao Zhang
发明人： Puneet Zaroo , Richard West , Carl A. Waldspurger , Xiao Zhang
IPC分类号： G06F9/50
CPC分类号： G06F9/48 , G06F9/4881 , G06F9/50 , G06F9/5005 , G06F9/5011 , G06F9/5016 , G06F9/5022 , G06F9/5027 , G06F9/5033 , G06F9/5044 , G06F9/505 , G06F9/5055 , G06F11/3409 , G06F11/3442 , G06F11/3452 , G06F11/3466 , G06F12/08 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0815 , G06F12/084 , G06F2201/88 , G06F2209/483 , G06F2209/501
摘要： A method is described for scheduling in an intelligent manner a plurality of threads on a processor having a plurality of cores and a shared last level cache (LLC). In the method, a first and second scenario having a corresponding first and second combination of threads are identified. The cache occupancies of each of the threads for each of the scenarios are predicted. The predicted cache occupancies being a representation of an amount of the LLC that each of the threads would occupy when running with the other threads on the processor according to the particular scenario. One of the scenarios is identified that results in the least objectionable impacts on all threads, the least objectionable impacts taking into account the impact resulting from the predicted cache occupancies. Finally, a scheduling decision is made according to the one of the scenarios that results in the least objectionable impacts.
摘要翻译：描述了一种以智能方式调度具有多个核的处理器上的多个线程和共享的最后一级高速缓存（LLC）的方法。在该方法中，识别具有对应的第一和第二线程组合的第一和第二情景。预测每个场景的每个线程的高速缓存占用。预测的高速缓存占用是根据特定场景与处理器上的其他线程一起运行时每个线程将占用的LLC的量的表示。确定了一种情景，对所有线程造成的影响最小，最不令人反感的影响考虑到预测的缓存占用引起的影响。最后，根据导致最不利影响的情景之一进行调度决策。

6. 发明申请

US20120117299A1 EFFICIENT ONLINE CONSTRUCTION OF MISS RATE CURVES 有权
标题翻译：有效的在线建设的速率曲线
公开(公告)号：US20120117299A1
公开(公告)日：2012-05-10
申请号：US12942765
申请日：2010-11-09
申请人： Carl A. WALDSPURGER , Rajesh VENKATASUBRAMANIAN , Alexander Thomas GARTHWAITE , Yury BASKAKOV , Puneet ZAROO
发明人： Carl A. WALDSPURGER , Rajesh VENKATASUBRAMANIAN , Alexander Thomas GARTHWAITE , Yury BASKAKOV , Puneet ZAROO
IPC分类号： G06F12/12 , G06F12/10
CPC分类号： G06F12/122 , G06F9/45558 , G06F11/3471 , G06F12/123 , G06F2009/45583 , G06F2201/815 , G06F2201/88
摘要： Miss rate curves are constructed in a resource-efficient manner so that they can be constructed and memory management decisions can be made while the workloads are running. The resource-efficient technique includes the steps of selecting a subset of memory pages for the workload, maintaining a least recently used (LRU) data structure for the selected memory pages, detecting accesses to the selected memory pages and updating the LRU data structure in response to the detected accesses, and generating data for constructing a miss-rate curve for the workload using the LRU data structure. After a memory page is accessed, the memory page may be left untraced for a period of time, after which the memory page is retraced.
摘要翻译：错误率曲线以资源有效的方式构建，以便可以构建它们，并且可以在工作负载运行时进行内存管理决策。资源有效的技术包括以下步骤：为工作负载选择存储器页面的子集，维护所选择的存储器页面的最近最少使用的（LRU）数据结构，检测对所选择的存储器页面的访问以及响应地更新LRU数据结构并且使用LRU数据结构生成用于构建工作负载的错过率曲线的数据。在访问存储器页面之后，存储器页面可以保持未被跟踪一段时间，之后再回读存储器页面。

7. 发明申请

US20110231857A1 CACHE PERFORMANCE PREDICTION AND SCHEDULING ON COMMODITY PROCESSORS WITH SHARED CACHES 有权
标题翻译：具有共享速度的商品处理器的缓存性能预测和调度
公开(公告)号：US20110231857A1
公开(公告)日：2011-09-22
申请号：US12727705
申请日：2010-03-19
申请人： Puneet Zaroo , Richard West , Carl A. Waldspurger , Xiao Zhang
发明人： Puneet Zaroo , Richard West , Carl A. Waldspurger , Xiao Zhang
IPC分类号： G06F9/50 , G06F9/46
CPC分类号： G06F9/48 , G06F9/4881 , G06F9/50 , G06F9/5005 , G06F9/5011 , G06F9/5016 , G06F9/5022 , G06F9/5027 , G06F9/5033 , G06F9/5044 , G06F9/505 , G06F9/5055 , G06F11/3409 , G06F11/3442 , G06F11/3452 , G06F11/3466 , G06F12/08 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0815 , G06F12/084 , G06F2201/88 , G06F2209/483 , G06F2209/501
摘要： A method is described for scheduling in an intelligent manner a plurality of threads on a processor having a plurality of cores and a shared last level cache (LLC). In the method, a first and second scenario having a corresponding first and second combination of threads are identified. The cache occupancies of each of the threads for each of the scenarios are predicted. The predicted cache occupancies being a representation of an amount of the LLC that each of the threads would occupy when running with the other threads on the processor according to the particular scenario. One of the scenarios is identified that results in the least objectionable impacts on all threads, the least objectionable impacts taking into account the impact resulting from the predicted cache occupancies. Finally, a scheduling decision is made according to the one of the scenarios that results in the least objectionable impacts.
摘要翻译：描述了一种以智能方式调度具有多个核的处理器上的多个线程和共享的最后一级高速缓存（LLC）的方法。在该方法中，识别具有对应的第一和第二线程组合的第一和第二情景。预测每个场景的每个线程的高速缓存占用。预测的高速缓存占用是根据特定场景与处理器上的其他线程一起运行时每个线程将占用的LLC的量的表示。确定了一种情景，对所有线程造成的影响最小，最不令人反感的影响考虑到预测的缓存占用引起的影响。最后，根据导致最不利影响的情景之一进行调度决策。

8. 发明申请

US20110055479A1 Thread Compensation For Microarchitectural Contention 有权
标题翻译：微架构竞争线程补偿
公开(公告)号：US20110055479A1
公开(公告)日：2011-03-03
申请号：US12550193
申请日：2009-08-28
申请人： Richard West , Puneet Zaroo , Carl A. Waldspurger , Xiao Zhang
发明人： Richard West , Puneet Zaroo , Carl A. Waldspurger , Xiao Zhang
IPC分类号： G06F9/46 , G06F12/08
CPC分类号： G06F9/4881 , G06F9/48 , G06F11/3409 , G06F12/0842 , G06F2209/485 , G06F2209/486
摘要： A thread (or other resource consumer) is compensated for contention for system resources in a computer system having at least one processor core, a last level cache (LLC), and a main memory. In one embodiment, at each descheduling event of the thread following an execution interval, an effective CPU time is determined. The execution interval is a period of time during which the thread is being executed on the central processing unit (CPU) between scheduling events. The effective CPU time is a portion of the execution interval that excludes delays caused by contention for microarchitectural resources, such as time spent repopulating lines from the LLC that were evicted by other threads. The thread may be compensated for microarchitectural contention by increasing its scheduling priority based on the effective CPU time.
摘要翻译：对具有至少一个处理器核心，最后一级缓存（LLC）和主存储器的计算机系统中的系统资源的竞争进行补偿的线程（或其他资源消费者）。在一个实施例中，在执行间隔之后的线程的每个调度事件处，确定有效的CPU时间。执行间隔是在调度事件之间的中央处理单元（CPU）上执行线程的时间段。有效CPU时间是执行间隔的一部分，排除了由微型架构资源的争用引起的延迟，例如，重新生成由其他线程驱逐的LLC的线路所花费的时间。可以通过根据有效CPU时间增加其调度优先级来对线程进行微架构争用补偿。

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