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    • 1. 发明申请
    • INTEGRATED CIRCUIT WITH DEGRADATION MONITORING
    • 集成电路与降解监测
    • US20140132315A1
    • 2014-05-15
    • US13677800
    • 2012-11-15
    • Puneet SharmaMatthew A. ThompsonWillard E. Conley
    • Puneet SharmaMatthew A. ThompsonWillard E. Conley
    • H03L7/00
    • G01R31/3016G01R31/2884
    • An integrated circuit including a degradation monitoring circuit. The degradation monitoring circuit includes a comparison circuit having a delay element including an input coupled to a data node of a timing path and having an output to provide a delayed signal of a data signal of the data node. The comparison circuit includes a logic comparator that provides a logic comparison between a data signal of the data node and the output of the delay element. The monitoring circuit includes a sampling circuit that provides a sampled signal of the output of the logic comparator that is a sampled with respect to a clock signal of the clock signal line. The monitoring circuit includes a hold circuit that provides a signal indicative of a data signal of the data node transitioning within a predetermined time of an edge transition of a clock signal of the clock signal line.
    • 一种包括劣化监测电路的集成电路。 劣化监视电路包括具有延迟元件的比较电路,该延迟元件包括耦合到定时路径的数据节点的输入,并具有输出以提供数据节点的数据信号的延迟信号。 比较电路包括逻辑比较器,其提供数据节点的数据信号和延迟元件的输出之间的逻辑比较。 监视电路包括采样电路,该采样电路提供对于时钟信号线的时钟信号采样的逻辑比较器的输出的采样信号。 监视电路包括保持电路,该保持电路提供指示在时钟信号线的时钟信号的边沿转换的预定时间内数据节点的数据信号的信号。
    • 2. 发明授权
    • Method for analyzing placement context sensitivity of standard cells
    • 分析标准细胞放置上下文敏感度的方法
    • US08661393B2
    • 2014-02-25
    • US13536694
    • 2012-06-28
    • Robert E. BoonePuneet SharmaMatthew A. Thompson
    • Robert E. BoonePuneet SharmaMatthew A. Thompson
    • G06F17/50
    • G06F17/5072
    • A disclosed method for evaluating placement context sensitivity in the design of an integrated circuit includes accessing a standard cell library comprising a database of standard cells and determining generating boundary data for each of the standard cells. The boundary data for a standard cell indicates the layout of features located within boundary regions of the standard cell. The method includes merging or consolidating boundary data for any two standard cells if their boundary data is the same to determine a canonical or minimal set of boundary regions. The disclosed method further includes enumerating and evaluating all combinations of pairs of the canonical boundary regions and, responsive to identifying of a proximity-based sensitivity or exception, modifying, notating, or otherwise remediating the applicable one or more standard cells that correspond to the boundary region combination that raised the exception.
    • 用于评估集成电路设计中的放置上下文敏感度的公开的方法包括访问包括标准单元的数据库的标准单元库,并且为每个标准单元确定生成边界数据。 标准单元的边界数据表示位于标准单元的边界区域内的特征的布局。 该方法包括如果边界数据相同以合并或合并任何两个标准单元的边界数据,以确定边界区域的典型或最小集合。 所公开的方法还包括列举和评估规范边界区域对的所有组合,并且响应于识别基于接近度的灵敏度或异常,修改,表示或以其他方式补救对应于边界的可应用的一个或多个标准单元 引起异常的区域组合。
    • 3. 发明申请
    • METHOD FOR ANALYZING PLACEMENT CONTEXT SENSITIVITY OF STANDARD CELLS
    • 分析标准细胞的位置敏感性的方法
    • US20140007029A1
    • 2014-01-02
    • US13536694
    • 2012-06-28
    • Robert E. BoonePuneet SharmaMatthew A. Thompson
    • Robert E. BoonePuneet SharmaMatthew A. Thompson
    • G06F17/50
    • G06F17/5072
    • A disclosed method for evaluating placement context sensitivity in the design of an integrated circuit includes accessing a standard cell library comprising a database of standard cells and determining generating boundary data for each of the standard cells. The boundary data for a standard cell indicates the layout of features located within boundary regions of the standard cell. The method includes merging or consolidating boundary data for any two standard cells if their boundary data is the same to determine a canonical or minimal set of boundary regions. The disclosed method further includes enumerating and evaluating all combinations of pairs of the canonical boundary regions and, responsive to identifying of a proximity-based sensitivity or exception, modifying, notating, or otherwise remediating the applicable one or more standard cells that correspond to the boundary region combination that raised the exception.
    • 用于评估集成电路设计中的放置上下文敏感度的公开的方法包括访问包括标准单元的数据库的标准单元库,并且为每个标准单元确定生成边界数据。 标准单元的边界数据表示位于标准单元的边界区域内的特征的布局。 该方法包括如果边界数据相同以合并或合并任何两个标准单元的边界数据,以确定边界区域的典型或最小集合。 所公开的方法还包括枚举和评估规范边界区域对的所有组合,并且响应于识别基于接近度的灵敏度或异常,修改,表示或以其他方式修复与边界对应的适用的一个或多个标准单元 引起异常的区域组合。