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1. 发明授权

US07134028B2 Processor with low overhead predictive supply voltage gating for leakage power reduction 有权
标题翻译：具有低开销预测电源电压门控的处理器，用于泄漏功率降低
公开(公告)号：US07134028B2
公开(公告)日：2006-11-07
申请号：US10428170
申请日：2003-05-01
申请人： Pradip Bose , David M. Brooks , Peter W. Cook , Philip G. Emma , Michael K. Gschwind , Stanley E. Schuster , Vijayalakshmi Srinivasan
发明人： Pradip Bose , David M. Brooks , Peter W. Cook , Philip G. Emma , Michael K. Gschwind , Stanley E. Schuster , Vijayalakshmi Srinivasan
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F9/3869 , G06F1/3203 , G06F1/3243 , G06F1/3246 , G06F1/3287 , Y02D10/152 , Y02D10/171
摘要： An integrated circuit (IC) including unit power control, leakage reduction circuit for controllably reducing leakage power with reduced LdI/dt noise in the IC and, an activity prediction unit invoking active/dormant states in IC units. The prediction unit determines turn on and turn off times for each IC unit. The prediction unit controls a supply voltage select circuit selectively passing a supply voltage to a separate supply line at the predicted turn on time and selectively blocking the supply voltage at the predicted turn off time.
摘要翻译：包括单元功率控制的集成电路（IC），用于可控地减少IC中的LdI / dt噪声的泄漏功率的泄漏降低电路，以及在IC单元中调用主动/休眠状态的活动预测单元。预测单元确定每个IC单元的导通和关闭时间。预测单元控制电源电压选择电路，其在预测的导通时间选择性地将电源电压传递到单独的电源线，并且在预测的关断时间选择性地阻断电源电压。

2. 发明授权

US08521999B2 Executing touchBHT instruction to pre-fetch information to prediction mechanism for branch with taken history 有权
标题翻译：执行touchBHT指令，预先获取信息到具有历史记录的分支预测机制
公开(公告)号：US08521999B2
公开(公告)日：2013-08-27
申请号：US12721933
申请日：2010-03-11
申请人： Philip G. Emma , Allan M. Hartstein , Brian R. Prasky , Thomas R. Puzak , Vijayalakshmi Srinivasan
发明人： Philip G. Emma , Allan M. Hartstein , Brian R. Prasky , Thomas R. Puzak , Vijayalakshmi Srinivasan
IPC分类号： G06F9/38
CPC分类号： G06F9/3844 , G06F9/30058 , G06F9/30145 , G06F9/3846 , G06F9/3848
摘要： A method comprising receiving a branch instruction, decoding a branch address and the branch instruction, executing a branch action associated with the branch address, determining whether a branch associated with the branch action was taken, and saving an identifier of the branch instruction and in indicator that the branch action was taken in a prefetch history table responsive to determining that the branch associated with the branch action was taken.
摘要翻译：一种方法，包括接收分支指令，解码分支地址和分支指令，执行与分支地址相关联的分支动作，确定是否采用与分支动作相关联的分支，以及保存分支指令的标识符和指示符响应于确定与分支动作相关联的分支被采取，分支动作被采取在预取历史表中。

3. 发明授权

US08108609B2 Structure for implementing dynamic refresh protocols for DRAM based cache 有权
标题翻译：用于实现基于DRAM的缓存的动态刷新协议的结构
公开(公告)号：US08108609B2
公开(公告)日：2012-01-31
申请号：US12126499
申请日：2008-05-23
申请人： John E. Barth , Philip G. Emma , Erik L. Hedberg , Hillery C. Hunter , Peter A. Sandon , Vijayalakshmi Srinivasan , Arnold S. Tran
发明人： John E. Barth , Philip G. Emma , Erik L. Hedberg , Hillery C. Hunter , Peter A. Sandon , Vijayalakshmi Srinivasan , Arnold S. Tran
IPC分类号： G06F12/00
CPC分类号： G06F12/0893 , G06F2212/304 , Y02D10/13
摘要： A hardware description language (HDL) design structure embodied on a machine-readable data storage medium includes elements that when processed in a computer aided design system generates a machine executable representation of a device for implementing dynamic refresh protocols for DRAM based cache. The HDL design structure further includes a DRAM cache partitioned into a refreshable portion and a non-refreshable portion; and a cache controller configured to assign incoming individual cache lines to one of the refreshable portion and the non-refreshable portion of the cache based on a usage history of the cache lines; wherein cache lines corresponding to data having a usage history below a defined frequency are assigned by the controller to the refreshable portion of the cache, and cache lines corresponding to data having a usage history at or above the defined frequency are assigned to the non-refreshable portion of the cache.
摘要翻译：体现在机器可读数据存储介质上的硬件描述语言（HDL）设计结构包括当在计算机辅助设计系统中处理时生成用于实现基于DRAM的高速缓存的动态刷新协议的设备的机器可执行表示的元件。 HDL设计结构还包括划分为可刷新部分和不可刷新部分的DRAM高速缓存; 以及高速缓存控制器，被配置为基于所述高速缓存行的使用历史将输入的各个高速缓存行分配给所述高速缓存的可刷新部分和不可刷新部分之一; 其中对应于具有低于定义频率的使用历史的数据的高速缓存行被控制器分配给高速缓存的可刷新部分，并且与具有等于或高于定义频率的使用历史的数据相对应的高速缓存行被分配给不可刷新部分缓存。

4. 发明申请

US20110078412A1 Processor Core Stacking for Efficient Collaboration 有权
标题翻译：处理器核心堆叠高效协作
公开(公告)号：US20110078412A1
公开(公告)日：2011-03-31
申请号：US12570351
申请日：2009-09-30
申请人： Philip G. Emma , Eren Kursun , Moinuddin K. Qureshi , Vijayalakshmi Srinivasan
发明人： Philip G. Emma , Eren Kursun , Moinuddin K. Qureshi , Vijayalakshmi Srinivasan
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3851 , G06F9/3857 , G06F9/3885 , G06F9/3889
摘要： A mechanism is provided for improving the performance and efficiency of multi-core processors. A system controller in a data processing system determines an operational function for each primary processor core in a set of primary processor cores in a primary processor core logic layer and for each secondary processor core in a set of secondary processor cores in a secondary processor core logic layer, thereby forming a set of determined operational functions. The system controller then generates an initial configuration, based on the set of determined operational functions, for initializing the set of primary processor cores and the set of secondary processor cores in the three-dimensional processor core architecture. The initial configuration indicates how at least one primary processor core of the set of primary processor cores collaborate with at least one secondary processor core of the set of secondary processor cores.
摘要翻译：提供了一种提高多核处理器性能和效率的机制。数据处理系统中的系统控制器确定主处理器核心逻辑层中的一组主处理器核心中的每个主处理器核心的操作功能，以及辅助处理器核心逻辑中的一组次要处理器核心中的每个辅助处理器核心从而形成一组确定的操作功能。系统控制器然后基于所确定的操作功能的集合生成用于初始化三维处理器核心体系结构中的主处理器核心集合和次要处理器核心组的初始配置。初始配置指示主处理器核心组中的至少一个主处理器核与第二处理器核集合中的至少一个辅助处理器核协作。

5. 发明申请

US20090193186A1 EMBEDDED DRAM HAVING MULTI-USE REFRESH CYCLES 审中-公开
标题翻译：嵌入式DRAM具有多次使用的刷新周期
公开(公告)号：US20090193186A1
公开(公告)日：2009-07-30
申请号：US12019818
申请日：2008-01-25
申请人： John E. Barth, JR. , Philip G. Emma , Hillery C. Hunter , Vijayalakshmi Srinivasan , Arnold S. Tran
发明人： John E. Barth, JR. , Philip G. Emma , Hillery C. Hunter , Vijayalakshmi Srinivasan , Arnold S. Tran
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0862 , Y02D10/13
摘要： An embedded DRAM (eDRAM) having multi-use refresh cycles is described. In one embodiment, there is a multi-level cache memory system that comprises a pending write queue configured to receive pending prefetch operations from at least one of the levels of cache. A prefetch queue is configured to receive prefetch operations for at least one of the levels of cache. A refresh controller is configured to determine addresses within each level of cache that are due for a refresh. The refresh controller is configured to assert a refresh write-in signal to write data supplied from the pending write queue specified for an address due for a refresh rather than refresh existing data. The refresh controller asserts the refresh write-in signal in response to a determination that there is pending data to supply to the address specified to have the refresh. The refresh controller is further configured to assert a refresh read-out signal to send refreshed data to the prefetch queue of a higher level of cache as a prefetch operation in response to a determination that the refreshed data is useful.
摘要翻译：描述了具有多次使用刷新周期的嵌入式DRAM（eDRAM）。在一个实施例中，存在多级高速缓冲存储器系统，其包括被配置为从高速缓存的至少一个级别接收未决的预取操作的等待写入队列。预取队列被配置为接收至少一个缓存级别的预取操作。刷新控制器被配置为确定要刷新到期的每个高速缓存级别内的地址。刷新控制器被配置为断言刷新写入信号以写入从针对刷新而不是刷新现有数据的地址指定的等待写入队列提供的数据。刷新控制器响应于确定有未决数据提供给被指定为刷新的地址，来确定刷新写入信号。刷新控制器还被配置为响应于确定刷新的数据是有用的，将更新读出信号断言以将更新的数据发送到较高级别的高速缓存的预取队列作为预取操作。

6. 发明授权

US07472226B1 Methods involving memory caches 失效
标题翻译：涉及内存缓存的方法
公开(公告)号：US07472226B1
公开(公告)日：2008-12-30
申请号：US12052163
申请日：2008-03-20
申请人： Philip G. Emma , Robert K. Montoye , Vijayalakshmi Srinivasan
发明人： Philip G. Emma , Robert K. Montoye , Vijayalakshmi Srinivasan
IPC分类号： G06F12/00
CPC分类号： G06F12/0864
摘要： A method for accessing data in memory comprising, receiving address bits associated with a data item including a first tag, an index, and a sector ID from a requestor, associating the index with a congruence class in a primary directory, determining whether the first tag matches a second tag in a plurality of tags in the congruence class, wherein the each tag of the plurality of tags uniquely identifies a cache line associated with a primary ID in the congruence class, defining the primary ID of the second tag of the primary directory that matches the first tag, determining whether the primary ID and the sector ID are present in a secondary directory entry having a one to one correspondence with a sector in a data array, and sending the data item from the sector to the requestor.
摘要翻译：一种用于访问存储器中的数据的方法，包括：从请求者接收与包括第一标签，索引和扇区ID的数据项相关联的地址位，将索引与主目录中的一致类相关联，确定第一标签匹配所述同余类中的多个标签中的第二标签，其中所述多个标签中的每个标签唯一地标识与所述同余类中的主要ID相关联的高速缓存行，定义所述主目录的第二标签的主ID 与第一标签匹配，确定主ID和扇区ID是否存在于与数据阵列中的扇区具有一对一对应关系的次目录条目中，以及将数据项从扇区发送到请求者。

7. 发明授权

US08024513B2 Method and system for implementing dynamic refresh protocols for DRAM based cache 有权
标题翻译：用于实现基于DRAM的缓存动态刷新协议的方法和系统
公开(公告)号：US08024513B2
公开(公告)日：2011-09-20
申请号：US11949904
申请日：2007-12-04
申请人： John E. Barth, Jr. , Philip G. Emma , Erik L. Hedberg , Hillery C. Hunter , Peter A. Sandon , Vijayalakshmi Srinivasan , Arnold S. Tran
发明人： John E. Barth, Jr. , Philip G. Emma , Erik L. Hedberg , Hillery C. Hunter , Peter A. Sandon , Vijayalakshmi Srinivasan , Arnold S. Tran
IPC分类号： G06F12/00
CPC分类号： G06F12/0893 , Y02D10/13
摘要： A method for implementing dynamic refresh protocols for DRAM based cache includes partitioning a DRAM cache into a refreshable portion and a non-refreshable portion, and assigning incoming individual cache lines to one of the refreshable portion and the non-refreshable portion of the cache based on a usage history of the cache lines. Cache lines corresponding to data having a usage history below a defined frequency are assigned to the refreshable portion of the cache, and cache lines corresponding to data having a usage history at or above the defined frequency are assigned to the non-refreshable portion of the cache.
摘要翻译：一种用于实现基于DRAM的高速缓存的动态刷新协议的方法包括将DRAM高速缓存划分为可刷新部分和不可刷新部分，以及基于以下方式将输入的各个高速缓存行分配到高速缓存的可刷新部分和不可刷新部分之一：高速缓存行的使用历史。对应于具有低于定义频率的使用历史的数据的缓存线被分配给高速缓存的可刷新部分，并且与具有等于或高于定义频率的使用历史的数据相对应的高速缓存行被分配给高速缓存的不可刷新部分。

8. 发明申请

US20090144506A1 METHOD AND SYSTEM FOR IMPLEMENTING DYNAMIC REFRESH PROTOCOLS FOR DRAM BASED CACHE 有权
标题翻译：用于实现基于DRAM的缓存的动态刷新协议的方法和系统
公开(公告)号：US20090144506A1
公开(公告)日：2009-06-04
申请号：US11949904
申请日：2007-12-04
申请人： John E. Barth, JR. , Philip G. Emma , Erik L. Hedberg , Hillery C. Hunter , Peter A. Sandon , Vijayalakshmi Srinivasan , Arnold S. Tran
发明人： John E. Barth, JR. , Philip G. Emma , Erik L. Hedberg , Hillery C. Hunter , Peter A. Sandon , Vijayalakshmi Srinivasan , Arnold S. Tran
IPC分类号： G06F12/08
CPC分类号： G06F12/0893 , Y02D10/13
摘要： A method for implementing dynamic refresh protocols for DRAM based cache includes partitioning a DRAM cache into a refreshable portion and a non-refreshable portion, and assigning incoming individual cache lines to one of the refreshable portion and the non-refreshable portion of the cache based on a usage history of the cache lines. Cache lines corresponding to data having a usage history below a defined frequency are assigned to the refreshable portion of the cache, and cache lines corresponding to data having a usage history at or above the defined frequency are assigned to the non-refreshable portion of the cache.
摘要翻译：一种用于实现基于DRAM的高速缓存的动态刷新协议的方法包括将DRAM高速缓存划分为可刷新部分和不可刷新部分，以及基于以下方式将输入的各个高速缓存行分配到高速缓存的可刷新部分和不可刷新部分之一：高速缓存行的使用历史。对应于具有低于定义频率的使用历史的数据的高速缓存行被分配给高速缓存的可刷新部分，并且与具有等于或高于定义频率的使用历史的数据相对应的高速缓存行被分配给高速缓存的不可刷新部分。

9. 发明授权

US07493480B2 Method and apparatus for prefetching branch history information 失效
标题翻译：用于预取分支历史信息的方法和装置
公开(公告)号：US07493480B2
公开(公告)日：2009-02-17
申请号：US10197714
申请日：2002-07-18
申请人： Philip G. Emma , Klaus J. Getzlaff , Allan M. Hartstein , Thomas Pflueger , Thomas R. Puzak , Eric Mark Schwarz , Vijayalakshmi Srinivasan
发明人： Philip G. Emma , Klaus J. Getzlaff , Allan M. Hartstein , Thomas Pflueger , Thomas R. Puzak , Eric Mark Schwarz , Vijayalakshmi Srinivasan
IPC分类号： G06F9/00
CPC分类号： G06F9/3806
摘要： A two level branch history table (TLBHT) is substantially improved by providing a mechanism to prefetch entries from the very large second level branch history table (L2 BHT) into the active (very fast) first level branch history table (L1 BHT) before the processor uses them in the branch prediction process and at the same time prefetch cache misses into the instruction cache. The mechanism prefetches entries from the very large L2 BHT into the very fast L1 BHT before the processor uses them in the branch prediction process. A TLBHT is successful because it can prefetch branch entries into the L1 BHT sufficiently ahead of the time the entry is needed. This feature of the TLBHT is also used to prefetch instructions into the cache ahead of their use. In fact, the timeliness of the prefetches produced by the TLBHT can be used to remove most of the cycle time penalty incurred by cache misses.
摘要翻译：通过提供一种将超大型第二级分支历史表（L2 BHT）中的条目预取到活动（非常快）的第一级分支历史表（L1 BHT）中的条目之前，两级分支历史表（TLBHT）被大大改善处理器在分支预测过程中使用它们，并且同时将高速缓存未命中预取到指令高速缓存中。在处理器在分支预测过程中使用它们之前，该机制将从非常大的L2 BHT中将条目预取到非常快的L1 BHT中。 TLBHT是成功的，因为它可以在需要输入的时间之前将分支条目预取到L1 BHT中。 TLBHT的这个功能也用于在使用之前将指令预取到高速缓存中。实际上，由TLBHT产生的预取的及时性可以用来消除高速缓存未命中引起的大部分周期时间损失。

10. 发明授权

US08417917B2 Processor core stacking for efficient collaboration 有权
标题翻译：处理器核心堆叠进行高效协作
公开(公告)号：US08417917B2
公开(公告)日：2013-04-09
申请号：US12570351
申请日：2009-09-30
申请人： Philip G. Emma , Eren Kursun , Moinuddin K. Qureshi , Vijayalakshmi Srinivasan
发明人： Philip G. Emma , Eren Kursun , Moinuddin K. Qureshi , Vijayalakshmi Srinivasan
IPC分类号： G06F9/00
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3851 , G06F9/3857 , G06F9/3885 , G06F9/3889
摘要： A mechanism is provided for improving the performance and efficiency of multi-core processors. A system controller in a data processing system determines an operational function for each primary processor core in a set of primary processor cores in a primary processor core logic layer and for each secondary processor core in a set of secondary processor cores in a secondary processor core logic layer, thereby forming a set of determined operational functions. The system controller then generates an initial configuration, based on the set of determined operational functions, for initializing the set of primary processor cores and the set of secondary processor cores in the three-dimensional processor core architecture. The initial configuration indicates how at least one primary processor core of the set of primary processor cores collaborate with at least one secondary processor core of the set of secondary processor cores.
摘要翻译：提供了一种提高多核处理器性能和效率的机制。数据处理系统中的系统控制器确定主处理器核心逻辑层中的一组主处理器核心中的每个主处理器核心的操作功能，以及辅助处理器核心逻辑中的一组次要处理器核心中的每个辅助处理器核心从而形成一组确定的操作功能。系统控制器然后基于所确定的操作功能的集合生成用于初始化三维处理器核心体系结构中的主处理器核心集合和次要处理器核心组的初始配置。初始配置指示主处理器核心组中的至少一个主处理器核与第二处理器核集合中的至少一个辅助处理器核协作。

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