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1. 发明授权

US5724565A Method and system for processing first and second sets of instructions by first and second types of processing systems 失效
标题翻译：用于通过第一和第二类处理系统处理第一和第二组指令的方法和系统
公开(公告)号：US5724565A
公开(公告)日：1998-03-03
申请号：US383282
申请日：1995-02-03
申请人： Pradeep Kumar Dubey , Charles Roberts Moore , Terence Matthew Potter
发明人： Pradeep Kumar Dubey , Charles Roberts Moore , Terence Matthew Potter
IPC分类号： G06F9/46 , G06F9/30 , G06F9/38
CPC分类号： G06F9/3804 , G06F9/3836 , G06F9/3842 , G06F9/3851
摘要： A method and system are provided for processing instruction threads. Execution is initiated by a processing system of a first set of instructions including a particular instruction. The particular instruction includes an indication of a second set of instructions. In response to execution of the particular instruction and to the processing system being of a first type, the processing system continues executing the first set while initiating execution of the second set. In response to execution of the particular instruction and to the processing system being of a second type, the processing system continues executing the first set without initiating execution of the second set.
摘要翻译：提供了一种用于处理指令线程的方法和系统。执行由包括特定指令的第一组指令的处理系统发起。特定指令包括第二组指令的指示。响应于特定指令的执行和处理系统是第一类型，处理系统在启动第二组的执行的同时继续执行第一组。响应于特定指令的执行和处理系统是第二类型，处理系统继续执行第一组而不启动第二组的执行。

2. 发明授权

US5872949A Apparatus and method for managing data flow dependencies arising from out-of-order execution, by an execution unit, of an instruction series input from an instruction source 失效
标题翻译：用于管理由执行单元从指令源输入的指令序列的无序执行产生的数据流依存性的装置和方法
公开(公告)号：US5872949A
公开(公告)日：1999-02-16
申请号：US748459
申请日：1996-11-13
申请人： Betty Yooko Kikuta , Terence Matthew Potter
发明人： Betty Yooko Kikuta , Terence Matthew Potter
IPC分类号： G06F9/38 , G06F9/00 , G06F9/22 , G06F9/30
CPC分类号： G06F9/384 , G06F9/3836 , G06F9/3857 , G06F9/3863
摘要： An apparatus and method to manage data flow dependencies so that a processor can complete instructions and write associated data to architected logical registers out of the program order. This increases the commission bandwidth of the processor allowing greater processor throughput, by allowing instructions to pass the completion stage prior to having produced data.
摘要翻译：一种用于管理数据流依赖性的装置和方法，使得处理器可以完成指令并将相关联的数据写入到程序顺序中的结构化逻辑寄存器中。这增加了处理器的调试带宽，从而允许更高的处理器吞吐量，允许指令在生成数据之前通过完成阶段。

3. 发明授权

US5901307A Processor having a selectively configurable branch prediction unit that can access a branch prediction utilizing bits derived from a plurality of sources 失效
标题翻译：处理器具有可选择地配置的分支预测单元，其可利用从多个源导出的比特来访问分支预测
公开(公告)号：US5901307A
公开(公告)日：1999-05-04
申请号：US684720
申请日：1996-07-22
申请人： Terence Matthew Potter , Paul Charles Rossbach , Thomas Luther Thomas, Jr.
发明人： Terence Matthew Potter , Paul Charles Rossbach , Thomas Luther Thomas, Jr.
IPC分类号： G06F9/38 , G06F9/32
CPC分类号： G06F9/3848
摘要： A processor and method for speculatively executing a branch instruction are disclosed. The processor includes a branch prediction unit for predicting a resolution of a speculative branch instruction, which is selectively configurable such that resolution of the speculative branch instruction is predicted in response to only an address of the speculative branch instruction or in response to branch history of at least one previously executed branch instruction. The processor also includes an address calculation unit for determining a target address in response to the predicted resolution of the speculative branch instruction. In one embodiment, the processor further includes configuration logic for dynamically configuring the branch prediction logic.
摘要翻译：公开了一种用于推测性地执行分支指令的处理器和方法。该处理器包括：分支预测单元，用于预测推测分支指令的分辨率，该分支预测单元可选择性地配置，使得仅响应于推测分支指令的地址或响应于分支历史信号预测推测分支指令的分辨率至少一个先前执行的分支指令。处理器还包括用于响应于推测分支指令的预测分辨率来确定目标地址的地址计算单元。在一个实施例中，处理器还包括用于动态配置分支预测逻辑的配置逻辑。

4. 发明授权

US5740419A Processor and method for speculatively executing an instruction loop 失效
标题翻译：用于推测执行指令循环的处理器和方法
公开(公告)号：US5740419A
公开(公告)日：1998-04-14
申请号：US685060
申请日：1996-07-22
申请人： Terence Matthew Potter
发明人： Terence Matthew Potter
IPC分类号： G06F9/32 , G06F9/38 , G06F15/82
CPC分类号： G06F9/3863 , G06F9/325 , G06F9/3842
摘要： A processor and method for speculatively executing an instruction loop are disclosed. In accordance with the method, the processor initiates execution of an instruction loop and counts each executed iteration of the instruction loop. Thereafter, an actual number of iterations that the instruction loop should be executed is determined. In response to the determination, a difference between the actual number of iterations that the instruction loop should be executed and the number of executed iterations is determined. In response to a determination that the difference is greater than zero, the instruction loop is executed an additional number of iterations equal to the difference. According to one embodiment, unexecuted fetched instructions within mispredicted iterations of the instruction loop are cancelled in response to a determination that the difference is less than zero. In addition, data results of mispredicted iterations of the instruction loop that have been executed are discarded. In accordance with another embodiment, the executed iterations of the instruction loop are counted by setting a count register to zero and decrementing the count register once for each iteration of the instruction loop executed. The difference between the actual number of iterations that should be executed and the number of executed iterations is determined by adding the actual number of iterations and the value of the count register.
摘要翻译：公开了一种用于推测执行指令循环的处理器和方法。根据该方法，处理器启动指令循环的执行并对指令循环的每个执行的迭代进行计数。此后，确定执行指令循环的实际迭代次数。响应于该确定，确定应该执行指令循环的实际迭代次数与执行的迭代次数之间的差异。响应于差异大于零的确定，指令循环被执行等于该差的附加数量的迭代。根据一个实施例，响应于差异小于零的确定，消除指令循环的误预测迭代中的未执行的获取指令。此外，已经执行的指令循环的误预测迭代的数据结果被丢弃。根据另一个实施例，通过将计数寄存器设置为零来计数指令循环的执行迭代，并且对于执行的指令循环的每个迭代递减计数寄存器一次。应该执行的实际迭代次数与执行迭代次数之间的差异是通过将实际迭代次数和计数寄存器的值相加来确定的。

5. 发明授权

US5974535A Method and system in data processing system of permitting concurrent processing of instructions of a particular type 失效
标题翻译：数据处理系统中的方法和系统允许同时处理特定类型的指令
公开(公告)号：US5974535A
公开(公告)日：1999-10-26
申请号：US853009
申请日：1997-05-09
申请人： Chih-Jui Ray Peng , Daniel Chen Chow , Terence Matthew Potter , Paul Charles Rossbach
发明人： Chih-Jui Ray Peng , Daniel Chen Chow , Terence Matthew Potter , Paul Charles Rossbach
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G06F9/00
CPC分类号： G06F9/30094 , G06F9/30101 , G06F9/384 , G06F9/3863 , G06F9/3885
摘要： A method and system in a data processing system of permitting concurrent processing of multiple conditional branch instructions are disclosed. A condition register is established within the processing system. First and second conditional branch instructions are dispatched during a single cycle of the processing system. Prior to speculatively executing the first conditional branch instruction, a first copy of the condition register is stored. Prior to speculatively executing the second conditional branch instruction, a second copy of the condition register is stored. Multiple copies of the condition register are concurrently maintained so that the first and second conditional branch instructions may be concurrently processed during a single cycle of the processing system.
摘要翻译：公开了允许并行处理多个条件分支指令的数据处理系统中的方法和系统。在处理系统内建立条件寄存器。在处理系统的单个周期期间调度第一和第二条件分支指令。在推测性地执行第一条件转移指令之前，存储条件寄存器的第一副本。在推测执行第二条件分支指令之前，存储条件寄存器的第二副本。同时维护条件寄存器的多个副本，使得可以在处理系统的单个周期期间同时处理第一和第二条件转移指令。

6. 发明授权

US5880983A Floating point split multiply/add system which has infinite precision 失效
标题翻译：具有无限精度的浮点分割乘法/加法系统
公开(公告)号：US5880983A
公开(公告)日：1999-03-09
申请号：US620733
申请日：1996-03-25
申请人： Timothy Alan Elliott , Robert Thaddeus Golla , Christopher Hans Olson , Terence Matthew Potter
发明人： Timothy Alan Elliott , Robert Thaddeus Golla , Christopher Hans Olson , Terence Matthew Potter
IPC分类号： G06F7/544 , G06F7/38
CPC分类号： G06F7/5443 , G06F7/483 , G06F7/49942
摘要： A method and system for an infinite precision split multiply and add operation which has increased speed. The method and system for providing a split multiply and add of a plurality of operands include a multiplier and an adder means. The multiplier multiplies a first portion of the plurality of operands, thereby providing a product. The adder, which combines the remaining operands and the product, comprise at least one pair of data paths. Each pair of data paths comprises a first data path and a second data path. The first data path comprises a first aligner, a first adder, and a first normalizer capable of shifting a mantissa by a substantially fewer number digits than the aligner. The second data path comprises a second aligner, a second adder, and a second normalizer capable of shifting a mantissa by a substantially larger number of digits than the aligner. Accordingly, the present invention includes split multiply and add data paths which, individually, are faster than a fused multiply and add. In addition, the split multiply and add data paths can preserve the appearance of infinite precision. Consequently, overall system performance is increased.
摘要翻译：一种用于无限精密分割乘法和加法运算的方法和系统，其具有增加的速度。用于提供多个操作数的分割乘法和相加的方法和系统包括乘法器和加法器装置。乘法器乘以多个操作数的第一部分，从而提供乘积。组合剩余操作数和乘积的加法器包括至少一对数据路径。每对数据路径包括第一数据路径和第二数据路径。第一数据路径包括第一对准器，第一加法器和第一归一化器，其能够将尾数与对准器相比更少的数字位移。第二数据路径包括第二对准器，第二加法器和第二归一化器，其能够将尾数移位比对准器大得多的位数。因此，本发明包括分离的乘法和加法数据路径，其分别比融合乘法和加法更快。此外，拆分乘法和添加数据路径可以保持无限精度的外观。因此，整体系统性能提高。

7. 发明授权

US5784606A Method and system in a superscalar data processing system for the efficient handling of exceptions 失效
标题翻译：超标量数据处理系统中的方法和系统，用于有效处理异常
公开(公告)号：US5784606A
公开(公告)日：1998-07-21
申请号：US768060
申请日：1996-12-16
申请人： Thomas Alan Hoy , Terence Matthew Potter , Paul Charles Rossbach
发明人： Thomas Alan Hoy , Terence Matthew Potter , Paul Charles Rossbach
IPC分类号： G06F9/48 , G06F9/46
CPC分类号： G06F9/4812
摘要： A method and system in a data processing system are disclosed for efficiently handling exceptions. The data processing system includes a register for storing indications of multiple instructions while the multiple instructions are being concurrently processed. An exception is generated within the data processing system. A determination is made whether the exception was generated by one of the multiple instructions. In response to a determination that one of the multiple instructions generated the exception, a determination is then made whether an indication of the instruction which generated the exception is stored in a particular position within a register within the data processing system. In response to a determination that the indication of the instruction is stored in the particular position within the register, the exception is associated with a first priority group. In response to a determination that the indication of the instruction is not stored in the particular position within the register, the exception is associated with a second priority group. In response to a determination that the indication of the instruction did not generate the exception, the exception is associated with the second priority group.
摘要翻译：公开了一种数据处理系统中的方法和系统，用于有效地处理异常。数据处理系统包括一个寄存器，用于存储多个指令同时处理多个指令的指示。在数据处理系统中产生异常。确定异常是否由多个指令之一生成。响应于多个指令中的一个指令产生异常的确定，然后确定产生异常的指令的指示是否存储在数据处理系统内的寄存器内的特定位置。响应于指示的指示被存储在寄存器内的特定位置的确定，该异常与第一优先级组相关联。响应于指示的指示未被存储在寄存器内的特定位置的确定，该异常与第二优先级组相关联。响应于指示的指示没有产生异常的确定，该异常与第二优先级组相关联。

8. 发明授权

US5742784A System for reordering of instructions before placement into cache to reduce dispatch latency 失效
标题翻译：在放入缓存之前重新排序指令的系统，以减少调度延迟
公开(公告)号：US5742784A
公开(公告)日：1998-04-21
申请号：US377976
申请日：1995-01-25
申请人： Terence Matthew Potter , John Stephen Muhich , Christopher Hans Olson , Timothy Alan Elliott
发明人： Terence Matthew Potter , John Stephen Muhich , Christopher Hans Olson , Timothy Alan Elliott
IPC分类号： G06F9/38 , G06F12/08 , G06F9/30
CPC分类号： G06F9/3802 , G06F9/3853
摘要： A method and system for reducing the dispatch latency of instructions of a processor provides for reordering the instructions in a predetermined format before the instructions enter the cache. The method and system also stores information in the cache relating to the reordering of the instructions. The reordered instructions are then provided to the appropriate execution units based upon the predetermined format. With this system, a dispatch buffer is not required when sending the instructions to the cache.
摘要翻译：用于减少处理器的指令的调度等待时间的方法和系统提供在指令进入高速缓存之前以预定格式重新排序指令。方法和系统还将信息存储在与指令的重新排序相关的缓存中。然后，基于预定格式将重排序的指令提供给适当的执行单元。使用该系统，在向缓存发送指令时不需要调度缓冲区。

9. 发明授权

US06266761B1 Method and system in an information processing system for efficient maintenance of copies of values stored within registers 失效
标题翻译：信息处理系统中的方法和系统，用于有效维护存储在寄存器内的值的副本
公开(公告)号：US06266761B1
公开(公告)日：2001-07-24
申请号：US09096836
申请日：1998-06-12
申请人： Michael David Carlson , Thomas Alan Hoy , Terence Matthew Potter , David Domenic Putti
发明人： Michael David Carlson , Thomas Alan Hoy , Terence Matthew Potter , David Domenic Putti
IPC分类号： G06F1500
CPC分类号： G06F9/3867 , G06F9/30101 , G06F9/3836 , G06F9/384 , G06F9/3857
摘要： A method and system in an information processing system are disclosed for efficiently maintaining copies of values stored within a plurality of registers. The information processing system includes first circuitry, second circuitry, and a plurality of buffers. The first circuitry processes an execution state of a first type of instruction which always specifies a destination of at least one of a first type of register or a second type of register, and which outputs first information in response thereto. The first circuitry also processes an execution stage of a second type of instruction which always specifies a destination of only a third type of register, and outputs second information in response thereto. The plurality of buffers are coupled to the execution circuitry for storing the output first and second information, wherein at least one of the buffers is for storing the output first information independent of which of the first and second types of registers is specified by the first type of instruction. The second circuitry is coupled to the buffers for processing a completion stage of the first type of instruction, and writing the stored first information into at least one of the first or a second type of register in response thereto. The second circuitry also processes a completion stage of the second type of instruction, and writes the stored second information into only the third type of register in response thereto.
摘要翻译：公开了一种信息处理系统中的方法和系统，用于有效地维护存储在多个寄存器内的值的副本。信息处理系统包括第一电路，第二电路和多个缓冲器。第一电路处理总是指定第一类型寄存器或第二类型寄存器中的至少一个的目的地的第一类型的指令的执行状态，并响应于此输出第一信息。第一电路还处理总是指定仅第三类型的寄存器的目的地的第二类型的指令的执行级，并响应于此输出第二信息。多个缓冲器耦合到执行电路，用于存储输出的第一和第二信息，其中缓冲器中的至少一个用于存储与第一类型和第二类型寄存器中的哪一类不同的第一类型的输出第一信息的教学。第二电路耦合到缓冲器，用于处理第一类型的指令的完成级，并响应于此将所存储的第一信息写入第一或第二类型的寄存器中的至少一个。第二电路还处理第二类型指令的完成阶段，并且响应于此将所存储的第二信息写入第三类型的寄存器。

10. 发明授权

US5907866A Block address translation circuit using two-bit to four-bit encoder 失效
标题翻译：使用2位至4位编码器的块地址转换电路
公开(公告)号：US5907866A
公开(公告)日：1999-05-25
申请号：US770220
申请日：1996-12-19
申请人： David James Martens , Terence Matthew Potter
发明人： David James Martens , Terence Matthew Potter
IPC分类号： G06F12/10
CPC分类号： G06F12/06
摘要： An approach for determining whether a current address is within an address range in which both the starting address of the range and the size of the address range are determined by variable register contents. Whereas the information in the variable register contents is in binary format, the current address is in a 2B format. The present invention provides logic for translating the binary formatted information so that it can be compared to the 2B formatted current address.
摘要翻译：用于确定当前地址是否在范围的起始地址和地址范围的大小都在可变寄存器内容中确定的地址范围内的方法。而变量寄存器内容中的信息为二进制格式，当前地址为2B格式。本发明提供了用于翻译二进制格式化信息以使其能够与2B格式化的当前地址进行比较的逻辑。

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