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1. 发明授权

US06266761B1 Method and system in an information processing system for efficient maintenance of copies of values stored within registers 失效
标题翻译：信息处理系统中的方法和系统，用于有效维护存储在寄存器内的值的副本
公开(公告)号：US06266761B1
公开(公告)日：2001-07-24
申请号：US09096836
申请日：1998-06-12
申请人： Michael David Carlson , Thomas Alan Hoy , Terence Matthew Potter , David Domenic Putti
发明人： Michael David Carlson , Thomas Alan Hoy , Terence Matthew Potter , David Domenic Putti
IPC分类号： G06F1500
CPC分类号： G06F9/3867 , G06F9/30101 , G06F9/3836 , G06F9/384 , G06F9/3857
摘要： A method and system in an information processing system are disclosed for efficiently maintaining copies of values stored within a plurality of registers. The information processing system includes first circuitry, second circuitry, and a plurality of buffers. The first circuitry processes an execution state of a first type of instruction which always specifies a destination of at least one of a first type of register or a second type of register, and which outputs first information in response thereto. The first circuitry also processes an execution stage of a second type of instruction which always specifies a destination of only a third type of register, and outputs second information in response thereto. The plurality of buffers are coupled to the execution circuitry for storing the output first and second information, wherein at least one of the buffers is for storing the output first information independent of which of the first and second types of registers is specified by the first type of instruction. The second circuitry is coupled to the buffers for processing a completion stage of the first type of instruction, and writing the stored first information into at least one of the first or a second type of register in response thereto. The second circuitry also processes a completion stage of the second type of instruction, and writes the stored second information into only the third type of register in response thereto.
摘要翻译：公开了一种信息处理系统中的方法和系统，用于有效地维护存储在多个寄存器内的值的副本。信息处理系统包括第一电路，第二电路和多个缓冲器。第一电路处理总是指定第一类型寄存器或第二类型寄存器中的至少一个的目的地的第一类型的指令的执行状态，并响应于此输出第一信息。第一电路还处理总是指定仅第三类型的寄存器的目的地的第二类型的指令的执行级，并响应于此输出第二信息。多个缓冲器耦合到执行电路，用于存储输出的第一和第二信息，其中缓冲器中的至少一个用于存储与第一类型和第二类型寄存器中的哪一类不同的第一类型的输出第一信息的教学。第二电路耦合到缓冲器，用于处理第一类型的指令的完成级，并响应于此将所存储的第一信息写入第一或第二类型的寄存器中的至少一个。第二电路还处理第二类型指令的完成阶段，并且响应于此将所存储的第二信息写入第三类型的寄存器。

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