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1. 发明授权

US07895556B2 Method for optimizing an unrouted design to reduce the probability of timing problems due to coupling and long wire routes 有权
标题翻译：用于优化未路由设计以减少由于耦合和长线路引起的定时问题的概率的方法
公开(公告)号：US07895556B2
公开(公告)日：2011-02-22
申请号：US11942990
申请日：2007-11-20
申请人： Pooja M. Kotecha , David J. Hathaway , Louise H. Trevillyan
发明人： Pooja M. Kotecha , David J. Hathaway , Louise H. Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method and a system is described to predict effects of coupling on timing by estimating the delta delay and delta slack that can occur due to coupling on any net, for optimization to minimize the sensitivity of slack to potential coupling violations. The invention protects against other unexpected increases in effective load capacitance, such as those due to unexpectedly long wire routes. It also estimates the delay impact of a single ‘fault’ or ‘event’, such as a coupling event or unexpectedly long wires routes, including the impact of slew propagation.
摘要翻译：描述了一种方法和系统，以通过估计由于任何网络上的耦合而可能发生的增量延迟和增量松弛来预测耦合对定时的影响，以便优化以使松弛对潜在耦合违规的灵敏度最小化。本发明可防止有效负载电容的其他意外增加，例如由于意外长的电线路由引起的负载电容。它还估计单个“故障”或“事件”的延迟影响，例如耦合事件或意外长电线路由，包括转换传播的影响。

2. 发明申请

US20090132982A1 METHOD FOR OPTIMIZING AN UNROUTED DESIGN TO REDUCE THE PROBABILITY OF TIMING PROBLEMS DUE TO COUPLING AND LONG WIRE ROUTES 有权
标题翻译：优化设计的方法，以减少因耦合和长途径导致的时序问题的可行性
公开(公告)号：US20090132982A1
公开(公告)日：2009-05-21
申请号：US11942990
申请日：2007-11-20
申请人： Pooja M. Kotecha , David J. Hathaway , Louise H. Trevillyan
发明人： Pooja M. Kotecha , David J. Hathaway , Louise H. Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method and a system is described to predict effects of coupling on timing by estimating the delta delay and delta slack that can occur due to coupling on any net, for optimization to minimize the sensitivity of slack to potential coupling violations. The invention protects against other unexpected increases in effective load capacitance, such as those due to unexpectedly long wire routes. It also estimates the delay impact of a single ‘fault’ or ‘event’, such as a coupling event or unexpectedly long wires routes, including the impact of slew propagation.
摘要翻译：描述了一种方法和系统，以通过估计由于任何网络上的耦合而可能发生的增量延迟和增量松弛来预测耦合对定时的影响，以便优化以使松弛对潜在耦合违规的灵敏度最小化。本发明可防止有效负载电容的其他意外增加，例如由于意外长的电线路由引起的负载电容。它还估计单个“故障”或“事件”的延迟影响，例如耦合事件或意外长电线路由，包括转换传播的影响。

3. 发明申请

US20100042955A1 Method of Minimizing Early-mode Violations Causing Minimum Impact to a Chip Design 有权
标题翻译：最大限度地减少对芯片设计造成最小影响的早期模式违规方法
公开(公告)号：US20100042955A1
公开(公告)日：2010-02-18
申请号：US12191435
申请日：2008-08-14
申请人： POOJA M. KOTECHA , Frank J. Musante , Veena S. Pureswaran , Louise H. Trevillyan , Paul G. Villarrubia
发明人： POOJA M. KOTECHA , Frank J. Musante , Veena S. Pureswaran , Louise H. Trevillyan , Paul G. Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A system and a method for correcting early-mode timing violations that operate across the process space of a circuit design. Optimizations are performed to replace padding that increase path delays on fast paths. At the stage in the design process where early-mode violations are addressed, placement, late-mode timing closure, routing, and detailed electrical and timing analysis are assumed to have been completed. The optimizations are designed to be effective in delaying fast paths while minimizing the impact on already-completed work on the chip, in contrast to relying only on adding pads that can have a negative impact on all of these quantities. The optimizations are classified according to their invasiveness and are followed by their deployment. The deployment is designed to minimize using delay pads, reduce design disruptions, and minimize effects on other aspects of the design.
摘要翻译：一种用于校正在电路设计的处理空间中工作的早期模式定时违反的系统和方法。执行优化来替代在快速路径上增加路径延迟的填充。在处理早期模式违规的设计过程的阶段，假设已经完成了放置，延迟模式定时关闭，路由以及详细的电气和时序分析。优化设计是有效延迟快速路径，同时最大限度地减少对已经完成的芯片上的工作的影响，而不是仅依靠添加可能对所有这些量产生负面影响的焊盘。优化根据其入侵性进行分类，其后进行部署。该部署旨在最大限度地减少使用延迟焊盘，减少设计中断，并尽量减少对设计其他方面的影响。

4. 发明授权

US07996812B2 Method of minimizing early-mode violations causing minimum impact to a chip design 有权
标题翻译：最小化早期模式违规的方法，对芯片设计造成的影响最小
公开(公告)号：US07996812B2
公开(公告)日：2011-08-09
申请号：US12191435
申请日：2008-08-14
申请人： Pooja M. Kotecha , Frank J. Musante , Veena S. Pureswaran , Louise H. Trevillyan , Paul G. Villarrubia
发明人： Pooja M. Kotecha , Frank J. Musante , Veena S. Pureswaran , Louise H. Trevillyan , Paul G. Villarrubia
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A system and a method for correcting early-mode timing violations that operate across the process space of a circuit design. Optimizations are performed to replace padding that increase path delays on fast paths. At the stage in the design process where early-mode violations are addressed, placement, late-mode timing closure, routing, and detailed electrical and timing analysis are assumed to have been completed. The optimizations are designed to be effective in delaying fast paths while minimizing the impact on already-completed work on the chip, in contrast to relying only on adding pads that can have a negative impact on all of these quantities. The optimizations are classified according to their invasiveness and are followed by their deployment. The deployment is designed to minimize using delay pads, reduce design disruptions, and minimize effects on other aspects of the design.
摘要翻译：一种用于校正在电路设计的处理空间中工作的早期模式定时违反的系统和方法。执行优化来替代在快速路径上增加路径延迟的填充。在处理早期模式违规的设计过程的阶段，假设已经完成了放置，延迟模式定时关闭，路由以及详细的电气和时序分析。优化设计是有效延迟快速路径，同时最大限度地减少对已经完成的芯片上的工作的影响，而不是仅依靠添加可能对所有这些量产生负面影响的焊盘。优化根据其入侵性进行分类，其后进行部署。该部署旨在最大限度地减少使用延迟焊盘，减少设计中断，并尽量减少对设计其他方面的影响。

5. 发明授权

US06958545B2 Method for reducing wiring congestion in a VLSI chip design 失效
标题翻译：降低VLSI芯片设计中布线拥塞的方法
公开(公告)号：US06958545B2
公开(公告)日：2005-10-25
申请号：US10755590
申请日：2004-01-12
申请人： Pooja M. Kotecha , Rama Gopal Gandham , Ruchir Puri , Louise H. Trevillyan , Adam P. Matheny
发明人： Pooja M. Kotecha , Rama Gopal Gandham , Ruchir Puri , Louise H. Trevillyan , Adam P. Matheny
IPC分类号： G06F17/50 , H01L23/52 , H01L29/40
CPC分类号： G06F17/5077
摘要： A system and method for correcting wiring congestion in a placed and partially or fully globally-routed VLSI chip design while avoiding adding new timing or electrical violations or other design constraints. Globally-congested areas are identified along with determining terminated and non-terminated wires in the congested areas. The process includes optimizing the identified congestion areas, incrementally rerouting affected nets, testing the resultant design legality and congestion metrics, and committing or reversing the optimizations and reroutings. The optimizations further includes the movement of logic cells and decomposition, recomposition or any other modification of logic cell structures (possibly combined with cell movement) to move terminated wires to less congested grid edges, rearrangement of commutative connections within or between cells, or addition of buffers to cause reroutes of feedthrough wires.
摘要翻译：一种用于校正放置和部分或全部全局路由VLSI芯片设计中的布线拥塞的系统和方法，同时避免添加新的定时或电气违规或其他设计约束。识别全局拥挤区域以及在拥堵区域中确定终止的和未终止的电线。该过程包括优化识别的拥塞区域，逐步重新路由受影响的网络，测试所得到的设计合法性和拥塞度量，以及提交或反转优化和重新排序。优化还包括逻辑单元的移动以及逻辑单元结构（可能与单元移动相结合）的分解，重组或任何其它修改，以将终止的引线移动到较不拥塞的网格边缘，在单元之内或之间重新排列交换连接，或者添加缓冲器引起馈通线的重新路由。

6. 发明申请

US20080209376A1 SYSTEM AND METHOD FOR SIGN-OFF TIMING CLOSURE OF A VLSI CHIP 失效
标题翻译： VLSI芯片的关闭时序关闭的系统和方法
公开(公告)号：US20080209376A1
公开(公告)日：2008-08-28
申请号：US11680110
申请日：2007-02-28
申请人： Michael A. Kazda , Pooja M. Kotecha , Adam P. Matheny , Lakshmi Reddy , Louise H. Trevillyan , Paul G. Villarrubia
发明人： Michael A. Kazda , Pooja M. Kotecha , Adam P. Matheny , Lakshmi Reddy , Louise H. Trevillyan , Paul G. Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/84
摘要： A method for performing timing optimization of a detail routed netlist, incorporating statistical variability information, common path pessimism reduction, and capacitative coupling information, in a tightly coupled, incremental manner with minimal perturbations to the placement, routing, and asserted parasitic information. The method corrects violations in a placed and routed design of a VLSI circuit chip, where the design is represented by a netlist describing logical and physical characteristics of the design and by a corresponding timing graph, the method including the steps of: identifying violations in the design; iteratively eliminating the violations by incrementally transforming the logical and the physical characteristics of the design, incorporating in the design only legal placements and routes; and applying incremental timing to evaluate the transformations, and updating the existing timing graphs to reflect changes consisting of the legal placements and routes.
摘要翻译：一种用于以紧密耦合的递增方式对细节路由网表执行定时优化的方法，其以最小的扰动对放置，路由和断言的寄生信息进行并入，并入统计变异信息，公共路径悲观度降低和电容耦合信息。该方法校正了VLSI电路芯片的放置和路由设计中的违规，其中设计由描述设计的逻辑和物理特性的网表以及对应的时序图表示，该方法包括以下步骤：识别设计; 通过逐步改变设计的逻辑和物理特征，迭代地消除违规行为，仅在设计中纳入合法的布局和路线; 并应用增量时间来评估变革，并更新现有的时间图，以反映由法定刊登位置和路线组成的变更。

7. 发明授权

US07581201B2 System and method for sign-off timing closure of a VLSI chip 失效
标题翻译：用于签发VLSI芯片的定时关闭的系统和方法
公开(公告)号：US07581201B2
公开(公告)日：2009-08-25
申请号：US11680110
申请日：2007-02-28
申请人： Michael A. Kazda , Pooja M. Kotecha , Adam P. Matheny , Lakshmi Reddy , Louise H. Trevillyan , Paul G. Villarrubia
发明人： Michael A. Kazda , Pooja M. Kotecha , Adam P. Matheny , Lakshmi Reddy , Louise H. Trevillyan , Paul G. Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/84
摘要： A method for performing timing optimization of a detail routed netlist, incorporating statistical variability information, common path pessimism reduction, and capacitative coupling information, in a tightly coupled, incremental manner with minimal perturbations to the placement, routing, and asserted parasitic information. The method corrects violations in a placed and routed design of a VLSI circuit chip, where the design is represented by a netlist describing logical and physical characteristics of the design and by a corresponding timing graph, the method including the steps of: identifying violations in the design; iteratively eliminating the violations by incrementally transforming the logical and the physical characteristics of the design, incorporating in the design only legal placements and routes; and applying incremental timing to evaluate the transformations, and updating the existing timing graphs to reflect changes consisting of the legal placements and routes.
摘要翻译：一种用于以紧密耦合的递增方式对细节路由网表执行定时优化的方法，其以最小的扰动对放置，路由和断言的寄生信息进行并入，并入统计变异信息，公共路径悲观度降低和电容耦合信息。该方法校正了VLSI电路芯片的放置和路由设计中的违规，其中设计由描述设计的逻辑和物理特性的网表以及对应的时序图表示，该方法包括以下步骤：识别设计; 通过逐步改变设计的逻辑和物理特征，迭代地消除违规行为，仅在设计中纳入合法的布局和路线; 并应用增量时间来评估变革，并更新现有的时间图，以反映由法定刊登位置和路线组成的变更。

8. 发明授权

US07225421B2 Clock tree distribution generation by determining allowed placement regions for clocked elements 有权
标题翻译：通过确定时钟元素的允许放置区域来生成时钟树分布
公开(公告)号：US07225421B2
公开(公告)日：2007-05-29
申请号：US10905970
申请日：2005-01-28
申请人： William R. Migatz , Paul M. Campbell , David J. Hathaway , David S. Kung , Ruchir Puri , Louise H. Trevillyan
发明人： William R. Migatz , Paul M. Campbell , David J. Hathaway , David S. Kung , Ruchir Puri , Louise H. Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F1/10
摘要： A method, system and program product are described for generating a clock distribution network on an integrated circuit by determining an allowable placement region for each of a set of clock tree leaf elements in the integrated circuit. This allowable placement region is generated by determining and intersecting a set of sub-regions under different constraints, each of which identifies an area in which the clock tree leaf element is placed to satisfy the respective constraint. Constraints for which sub-regions are determined include timing constraints in the form of slacks and congestion constraints. After allowable placement regions have been determined, the clock tree leaf elements are clustered, and each clock tree leaf element is placed at a location within its allowable placement region which minimizes some cost function for that clustering.
摘要翻译：描述了一种方法，系统和程序产品，用于通过为集成电路中的一组时钟树叶元素中的每一个确定允许的布局区域来在集成电路上生成时钟分配网络。通过确定和相交不同约束下的一组子区域来生成该允许的放置区域，每个子区域标识其中放置时钟树叶元素的区域以满足相应的约束。确定子区域的约束包括松弛和拥挤约束形式的时间约束。在确定了允许的放置区域之后，时钟树叶元素被聚集，并且每个时钟树叶元素被放置在其允许的放置区域内的位置，这使得该聚类的一些成本函数最小化。

9. 发明申请

US20090217227A1 METHOD AND APPARATUS FOR PARALLEL PROCESSING OF SEMICONDUCTOR CHIP DESIGNS 有权
标题翻译：半导体芯片设计的并行处理方法与装置
公开(公告)号：US20090217227A1
公开(公告)日：2009-08-27
申请号：US12035950
申请日：2008-02-22
申请人： MICHAEL W. DOTSON , Anthony DeGroff Drumm , Dazhuang J. Ma , Ruchir Puri , Louise H. Trevillyan
发明人： MICHAEL W. DOTSON , Anthony DeGroff Drumm , Dazhuang J. Ma , Ruchir Puri , Louise H. Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： In one embodiment, the invention is a method and apparatus for parallel processing of semiconductor chip designs. One embodiment of a method for processing a semiconductor chip design includes flattening a netlist corresponding to the semiconductor chip design, performing logic clustering on one or more logic elements incorporated in the flattened netlist to generate one or more clusters, partitioning the semiconductor chip design in accordance with the one or more clusters, and designing the individual partitions in parallel.
摘要翻译：在一个实施例中，本发明是用于半导体芯片设计的并行处理的方法和装置。用于处理半导体芯片设计的方法的一个实施例包括平坦化对应于半导体芯片设计的网表，对并入在扁平化网表中的一个或多个逻辑元件执行逻辑聚类以生成一个或多个簇，根据该划分半导体芯片设计使用一个或多个集群，并且并行设计各个分区。

10. 发明申请

US20090019415A1 STAGE MITIGATION OF INTERCONNECT VARIABILITY 有权
标题翻译：互联不稳定性阶段缓解
公开(公告)号：US20090019415A1
公开(公告)日：2009-01-15
申请号：US12237246
申请日：2008-09-24
申请人： Mark A. Lavin , Ruchir Puri , Louise H. Trevillyan , Hua Xiang
发明人： Mark A. Lavin , Ruchir Puri , Louise H. Trevillyan , Hua Xiang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： The present invention provides a method, system and program product for mitigating effects of interconnect variability during a design stage of a chip. Under the technique of the present invention, a global and detailed routing of interconnects of the chip are determined. Thereafter, a dummy fill estimation and a grid based metal density estimation are performed. Then, based on a CMP model, a variable map of metal thicknesses is obtained. Based on the variable map, wiring nets of the chip that are sensitive to metal variability (e.g., that fail to meet timing closure due to metal thickness loss/gain in the CMP process) are identified. These wiring nets are then re-routed for optimization of the chip.
摘要翻译：本发明提供了一种用于在芯片的设计阶段减轻互连变化的影响的方法，系统和程序产品。在本发明的技术下，确定了芯片互连的全局和详细路由。此后，执行虚拟填充估计和网格基金属密度估计。然后，基于CMP模型，获得金属厚度的可变图。基于可变图，识别对金属变化敏感的芯片的接线网（例如，由于CMP过程中的金属厚度损失/增益而不能满足定时闭合）。然后将这些接线网重新布线以优化芯片。

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