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1. 发明授权

US08020134B2 Method and apparatus for parallel processing of semiconductor chip designs 有权
标题翻译：半导体芯片设计的并行处理方法和装置
公开(公告)号：US08020134B2
公开(公告)日：2011-09-13
申请号：US12035950
申请日：2008-02-22
申请人： Michael W. Dotson , Anthony DeGroff Drumm , Dazhuang J. Ma , Ruchir Puri , Louise H. Trevillyan
发明人： Michael W. Dotson , Anthony DeGroff Drumm , Dazhuang J. Ma , Ruchir Puri , Louise H. Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： In one embodiment, the invention is a method and apparatus for parallel processing of semiconductor chip designs. One embodiment of a method for processing a semiconductor chip design includes flattening a netlist corresponding to the semiconductor chip design, performing logic clustering on one or more logic elements incorporated in the flattened netlist to generate one or more clusters, partitioning the semiconductor chip design in accordance with the one or more clusters, and designing the individual partitions in parallel.
摘要翻译：在一个实施例中，本发明是用于半导体芯片设计的并行处理的方法和装置。用于处理半导体芯片设计的方法的一个实施例包括平坦化对应于半导体芯片设计的网表，对并入在扁平化网表中的一个或多个逻辑元件执行逻辑聚类以生成一个或多个簇，根据该划分半导体芯片设计使用一个或多个集群，并且并行设计各个分区。

2. 发明申请

US20090217227A1 METHOD AND APPARATUS FOR PARALLEL PROCESSING OF SEMICONDUCTOR CHIP DESIGNS 有权
标题翻译：半导体芯片设计的并行处理方法与装置
公开(公告)号：US20090217227A1
公开(公告)日：2009-08-27
申请号：US12035950
申请日：2008-02-22
申请人： MICHAEL W. DOTSON , Anthony DeGroff Drumm , Dazhuang J. Ma , Ruchir Puri , Louise H. Trevillyan
发明人： MICHAEL W. DOTSON , Anthony DeGroff Drumm , Dazhuang J. Ma , Ruchir Puri , Louise H. Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： In one embodiment, the invention is a method and apparatus for parallel processing of semiconductor chip designs. One embodiment of a method for processing a semiconductor chip design includes flattening a netlist corresponding to the semiconductor chip design, performing logic clustering on one or more logic elements incorporated in the flattened netlist to generate one or more clusters, partitioning the semiconductor chip design in accordance with the one or more clusters, and designing the individual partitions in parallel.
摘要翻译：在一个实施例中，本发明是用于半导体芯片设计的并行处理的方法和装置。用于处理半导体芯片设计的方法的一个实施例包括平坦化对应于半导体芯片设计的网表，对并入在扁平化网表中的一个或多个逻辑元件执行逻辑聚类以生成一个或多个簇，根据该划分半导体芯片设计使用一个或多个集群，并且并行设计各个分区。

3. 发明授权

US06643683B1 Interactive client-server environment for performing collaborative timing analysis of circuit designs 失效
标题翻译：交互式客户机 - 服务器环境，用于执行电路设计的协同定时分析
公开(公告)号：US06643683B1
公开(公告)日：2003-11-04
申请号：US09566869
申请日：2000-05-08
申请人： Anthony DeGroff Drumm , Mark S Fredrickson , Marcus Matthew Poplawski , Brian Christopher Wilson
发明人： Anthony DeGroff Drumm , Mark S Fredrickson , Marcus Matthew Poplawski , Brian Christopher Wilson
IPC分类号： G06F1516
CPC分类号： G06F17/5031 , H04L29/06 , H04L67/10 , H04L69/329
摘要： An apparatus, program product and method utilize an interactive request server program to interface a plurality of client computers with a timing analysis program. The interactive request server program receives client requests from the plurality of client computers over a network, and, in response to each client request, accesses the timing analysis program to retrieve timing data based upon such client request and thereafter forwards the timing data to the client computer making such request. The interactive request server program may optionally be implemented using a web server program and an application server program, with the web server program interfacing with the client computers via an Internet-type interface, and the application server program interfacing with the timing analysis program using a programmatic interface supported by the timing analysis program. The web server, program and the application server program interface with one another through the use of scripts, which are executed by the web server in response to client requests, and which generate one or more commands that are issued to the application server program to control the timing analysis program via the programmatic interface.
摘要翻译：一种装置，程序产品和方法利用交互式请求服务器程序来将多个客户端计算机与定时分析程序接口。交互式请求服务器程序通过网络从多个客户端计算机接收客户端请求，并且响应于每个客户端请求，访问定时分析程序以基于这样的客户端请求检索定时数据，然后将定时数据转发给客户端电脑提出这样的要求。交互式请求服务器程序可以可选地使用Web服务器程序和应用程序服务器程序来实现，其中web服务器程序经由因特网型接口与客户端计算机接口，并且应用程序服务器程序使用程序界面支持时序分析程序。 Web服务器，程序和应用程序服务器程序通过使用脚本彼此接口，这些脚本由Web服务器响应于客户机请求执行，并且生成一个或多个发出到应用程序服务器程序以控制的命令时序分析程序通过编程接口。

4. 发明授权

US5825661A Method and apparatus for automatic post-layout optimization of an integrated circuit 失效
标题翻译：用于集成电路自动布局后优化的方法和装置
公开(公告)号：US5825661A
公开(公告)日：1998-10-20
申请号：US641390
申请日：1996-05-01
申请人： Anthony DeGroff Drumm
发明人： Anthony DeGroff Drumm
IPC分类号： G06F17/50 , G06F17/00
CPC分类号： G06F17/5045 , G06F17/5068
摘要： Automatic generation of post-layout optimization circuitry allows a computer system running an integrated circuit design tool to automatically compensate for timing errors by synthesizing circuit elements to bring the timing within specified timing constraints. A new circuit element is assigned a location without determining an allowable physical location on the integrated circuit, and all timing calculations are based on the assigned location. Then, once the timing constraints have been met by one or more new circuit elements, an incremental layout is performed to find physical locations for the new circuit elements, using the assigned locations as initial targets. By using assigned locations during timing calculations and later determining valid physical locations, many different circuit configurations may be evaluated in a short period of time, with only the best ones going through the more time-consuming step of layout and routing.
摘要翻译：自动生成布局后优化电路允许运行集成电路设计工具的计算机系统通过合成电路元件来自动补偿定时误差，从而将定时带到规定的时序约束内。一个新的电路元件被分配一个位置，而不会确定集成电路上允许的物理位置，而所有的时序计算均基于分配的位置。然后，一旦一个或多个新电路元件满足了时序约束，则执行增量布局以使用分配的位置作为初始目标来找到新电路元件的物理位置。通过在定时计算期间使用分配的位置以及随后确定有效的物理位置，可以在短时间内评估许多不同的电路配置，只有最好的电路配置将经历更耗时的布局和布线步骤。

5. 发明授权

US5761079A Engineering change management system employing a smart editor 失效
标题翻译：工程变更管理系统采用智能编辑器
公开(公告)号：US5761079A
公开(公告)日：1998-06-02
申请号：US903045
申请日：1997-07-30
申请人： Anthony DeGroff Drumm
发明人： Anthony DeGroff Drumm
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A system for identifying and bounding the regions of a digital electronic logic design model that are affected by design revisions. The system is useful for improving the efficiency of incremental logic synthesis systems and includes procedures for recording the signals directly affected by user revision operations and for marking signals in the logic to identify those indirectly affected. A smart editor capable of parsing the formal register transfer language (RTL) in which the logic design is described is included in the system.
摘要翻译：用于识别和限制受设计修订影响的数字电子逻辑设计模型的区域的系统。该系统对于提高增量逻辑合成系统的效率是有用的，并且包括用于记录直接受用户修订操作影响的信号的程序，以及用于标识逻辑中的信号以识别那些间接影响的信号。能够解析描述逻辑设计的形式寄存器传送语言（RTL）的智能编辑器被包括在系统中。

6. 发明申请

US20090044155A1 METHOD AND SYSTEM FOR DESIGNING AN ELECTRONIC CIRCUIT 有权
标题翻译：用于设计电子电路的方法和系统
公开(公告)号：US20090044155A1
公开(公告)日：2009-02-12
申请号：US12255819
申请日：2008-10-22
申请人： Anthony DeGroff Drumm , Lakshmi Narasimba Reddy , Louise Trevillyan
发明人： Anthony DeGroff Drumm , Lakshmi Narasimba Reddy , Louise Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method and system of designing an electronic circuit includes dividing a chip area of a design into a plurality of bins, identifying a candidate bin in the plurality of bins, and performing an area reduction on the candidate bin.
摘要翻译：一种设计电子电路的方法和系统包括将设计的芯片面积划分成多个箱体，识别多个箱体中的候选箱，并对候选箱进行面积减小。

7. 发明授权

US07451416B2 Method and system for designing an electronic circuit 有权
标题翻译：电子电路设计方法及系统
公开(公告)号：US07451416B2
公开(公告)日：2008-11-11
申请号：US11377432
申请日：2006-03-17
申请人： Anthony DeGroff Drumm , Lakshmi Narasimha Reddy , Louise Trevillyan
发明人： Anthony DeGroff Drumm , Lakshmi Narasimha Reddy , Louise Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method and system of designing an electronic circuit includes dividing a chip area of a design into a plurality of bins, identifying a candidate bin in the plurality of bins, and performing an area reduction on the candidate bin.
摘要翻译：一种设计电子电路的方法和系统包括将设计的芯片面积划分成多个箱体，识别多个箱体中的候选箱，并对候选箱进行面积减小。

8. 发明授权

US07168057B2 Targeted optimization of buffer-tree logic 失效
标题翻译：缓冲树逻辑的目标优化
公开(公告)号：US07168057B2
公开(公告)日：2007-01-23
申请号：US10920087
申请日：2004-08-17
申请人： Anthony DeGroff Drumm , Brian Christopher Wilson
发明人： Anthony DeGroff Drumm , Brian Christopher Wilson
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/505 , G06F2217/84
摘要： Computationally efficient methods and systems for optimizing an integrated circuit (IC) design by targeting only a limited subsection of buffer trees in the buffer system for optimization are provided. By making intelligent decisions about which buffer trees to optimize, greater gains in design efficiency (e.g., as measured by reduced delays and/or wire length) may be realized at greatly reduced computational times when compared to conventional techniques that attempt to optimize each buffer tree.
摘要翻译：提供了用于优化集成电路（IC）设计的计算有效的方法和系统，仅针对缓冲系统中的有限子节的缓冲树进行优化。通过做出关于哪些缓冲树进行优化的智能决策，与尝试优化每个缓冲树的常规技术相比，可以大大减少计算时间，实现设计效率（例如，通过减少的延迟和/或线长度测量）的更大的增益。

9. 发明授权

US07900182B2 Method and system for designing an electronic circuit 有权
标题翻译：电子电路设计方法及系统
公开(公告)号：US07900182B2
公开(公告)日：2011-03-01
申请号：US12255819
申请日：2008-10-22
申请人： Anthony DeGroff Drumm , Lakshmi Narasimha Reddy , Louise Trevillyan
发明人： Anthony DeGroff Drumm , Lakshmi Narasimha Reddy , Louise Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method and system of designing an electronic circuit includes dividing a chip area of a design into a plurality of bins, identifying a candidate bin in the plurality of bins, and performing an area reduction on the candidate bin.
摘要翻译：一种设计电子电路的方法和系统包括将设计的芯片面积划分成多个箱体，识别多个箱体中的候选箱，并对候选箱进行面积减小。

10. 发明授权

US06826740B2 Automated buffer insertion incorporating congestion relief for use in connection with physical design of integrated circuit 有权
标题翻译：自动缓冲器插入结合了与集成电路的物理设计相结合的阻塞缓解
公开(公告)号：US06826740B2
公开(公告)日：2004-11-30
申请号：US10140517
申请日：2002-05-07
申请人： Anthony DeGroff Drumm
发明人： Anthony DeGroff Drumm
IPC分类号： G06F1750
CPC分类号： G06F17/5068
摘要： An apparatus, program product and method use a congestion relief algorithm in connection with automated buffer insertion to relieve potential congestion during post-layout interconnect routing. The congestion relief algorithm is utilized to manipulate a plurality of L-shaped spans defined in a routing tree, and is configured to apply the congestion relief algorithm to at least a first L-shaped span among the plurality of L-shaped spans by rerouting the first L-shaped span at least partially within a rectangular area bounded by the first L-shaped span.
摘要翻译：一种装置，程序产品和方法使用与自动缓冲器插入相结合的拥堵减免算法来减轻后布局互连路由中的潜在拥塞。所述拥堵解除算法用于操纵在路由树中定义的多个L形跨度，并且被配置为通过重新路由所述拥塞减免算法来应用所述多个L形跨度中的至少第一L形跨度第一L形跨度至少部分地在由第一L形跨度限定的矩形区域内。

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