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1. 发明授权

US08933507B2 Metal/polysilicon gate trench power mosfet 有权
标题翻译：金属/多晶硅栅沟槽功率MOSFET
公开(公告)号：US08933507B2
公开(公告)日：2015-01-13
申请号：US13545131
申请日：2012-07-10
申请人： Chun-Wai Ng , Hsueh-Liang Chou , Po-Chih Su , Ruey-Hsin Liu
发明人： Chun-Wai Ng , Hsueh-Liang Chou , Po-Chih Su , Ruey-Hsin Liu
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L21/823418 , H01L21/823456 , H01L27/0922 , H01L29/407 , H01L29/41766 , H01L29/456 , H01L29/4941 , H01L29/66734 , H01L29/78 , H01L29/7809 , H01L29/7816 , H01L29/7835
摘要： The present disclosure relates to a power MOSFET device having a relatively low resistance hybrid gate electrode that enables good switching performance. In some embodiments, the power MOSFET device has a semiconductor body. An epitaxial layer is disposed on the semiconductor body. A hybrid gate electrode, which controls the flow of electrons between a source electrode and a drain electrode, is located within a trench extending into the epitaxial layer. The hybrid gate electrode has an inner region having a low resistance metal, an outer region having a polysilicon material, and a barrier region disposed between the inner region and the outer region. The low resistance of the inner region provides for a low resistance to the hybrid gate electrode that enables good switching performance for the power MOSFET device.
摘要翻译：本公开涉及具有相对低电阻的混合栅电极的功率MOSFET器件，其实现良好的开关性能。在一些实施例中，功率MOSFET器件具有半导体本体。外延层设置在半导体本体上。控制源电极和漏电极之间的电子流的混合栅电极位于延伸到外延层中的沟槽内。混合栅极具有具有低电阻金属的内部区域，具有多晶硅材料的外部区域和设置在内部区域和外部区域之间的阻挡区域。内部区域的低电阻提供了对功率MOSFET器件具有良好开关性能的混合栅电极的低电阻。

2. 发明申请

US20140008724A1 Apparatus and Method for MOS Transistor 有权
标题翻译： MOS晶体管的装置和方法
公开(公告)号：US20140008724A1
公开(公告)日：2014-01-09
申请号：US13541539
申请日：2012-07-03
申请人： Hsueh-Liang Chou , Chun-Wai Ng , Po-Chih Su , Ruey-Hsin Liu
发明人： Hsueh-Liang Chou , Chun-Wai Ng , Po-Chih Su , Ruey-Hsin Liu
IPC分类号： H01L27/088
CPC分类号： H01L29/1083 , H01L21/761 , H01L27/088 , H01L27/092 , H01L29/0623 , H01L29/0638 , H01L29/0653 , H01L29/0696 , H01L29/0852 , H01L29/1095 , H01L29/66659 , H01L29/7816 , H01L29/7833 , H01L29/7835
摘要： A MOS transistor comprises a substrate of a first conductivity, a first region of the first conductivity formed over the substrate, a second region of the first conductivity formed in the first region, a first drain/source region of a second conductivity formed in the second region, a second drain/source region of the second conductivity and a body contact region of the first conductivity, wherein the body contact region and the first drain/source region are formed in an alternating manner from a top view.
摘要翻译： MOS晶体管包括第一导电性的衬底，在衬底上形成的第一导电体的第一区域，形成在第一区域中的第一导电体的第二区域，形成在第二导电层中的第二导电性的第一漏极/源极区域区域，第二导电性的第二漏极/源极区域和第一导电体的本体接触区域，其中从顶视图以交替方式形成体接触区域和第一漏极/源极区域。

3. 发明申请

US20130320431A1 Vertical Power MOSFET and Methods for Forming the Same 有权
标题翻译：垂直功率MOSFET及其形成方法
公开(公告)号：US20130320431A1
公开(公告)日：2013-12-05
申请号：US13486768
申请日：2012-06-01
申请人： Po-Chih Su , Hsueh-Liang Chou , Ruey-Hsin Liu , Chun-Wai Ng
发明人： Po-Chih Su , Hsueh-Liang Chou , Ruey-Hsin Liu , Chun-Wai Ng
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66666 , H01L21/30604 , H01L21/743 , H01L21/76877 , H01L21/823456 , H01L21/823487 , H01L21/823493 , H01L27/088 , H01L27/098 , H01L29/0847 , H01L29/402 , H01L29/7827 , H01L29/7833
摘要： A device includes a semiconductor region in a semiconductor chip, a gate dielectric layer over the semiconductor region, and a gate electrode over the gate dielectric. A drain region is disposed at a top surface of the semiconductor region and adjacent to the gate electrode. A gate spacer is on a sidewall of the gate electrode. A dielectric layer is disposed over the gate electrode and the gate spacer. A conductive field plate is over the dielectric layer, wherein the conductive field plate has a portion on a drain side of the gate electrode. A deep metal via is disposed in the semiconductor region. A source electrode is underlying the semiconductor region, wherein the source electrode is electrically shorted to the conductive field plate through the deep metal via.
摘要翻译：一种器件包括半导体芯片中的半导体区域，半导体区域上的栅极电介质层和栅极电介质上的栅电极。漏极区域设置在半导体区域的顶表面并与栅电极相邻。栅极间隔物位于栅电极的侧壁上。电介质层设置在栅电极和栅间隔物上。导电场板在电介质层的上方，其中导电场板具有在栅电极的漏极侧的一部分。深金属通孔设置在半导体区域中。源电极位于半导体区域的下方，其中源电极通过深金属通孔与导电场板电短路。

4. 发明授权

US09653459B2 MOSFET having source region formed in a double wells region 有权
公开(公告)号：US09653459B2
公开(公告)日：2017-05-16
申请号：US13541539
申请日：2012-07-03
申请人： Hsueh-Liang Chou , Chun-Wai Ng , Po-Chih Su , Ruey-Hsin Liu
发明人： Hsueh-Liang Chou , Chun-Wai Ng , Po-Chih Su , Ruey-Hsin Liu
IPC分类号： H01L27/088 , H01L29/78 , H01L29/66 , H01L29/08 , H01L27/092 , H01L29/06 , H01L21/761
CPC分类号： H01L29/1083 , H01L21/761 , H01L27/088 , H01L27/092 , H01L29/0623 , H01L29/0638 , H01L29/0653 , H01L29/0696 , H01L29/0852 , H01L29/1095 , H01L29/66659 , H01L29/7816 , H01L29/7833 , H01L29/7835
摘要： A MOS transistor comprises a substrate of a first conductivity, a first region of the first conductivity formed over the substrate, a second region of the first conductivity formed in the first region, a first drain/source region of a second conductivity formed in the second region, a second drain/source region of the second conductivity and a body contact region of the first conductivity, wherein the body contact region and the first drain/source region are formed in an alternating manner from a top view.

5. 发明授权

US09293376B2 Apparatus and method for power MOS transistor 有权
标题翻译：功率MOS晶体管的装置和方法
公开(公告)号：US09293376B2
公开(公告)日：2016-03-22
申请号：US13546824
申请日：2012-07-11
申请人： Po-Chih Su , Hsueh-Liang Chou , Chun-Wai Ng , Ruey-Hsin Liu
发明人： Po-Chih Su , Hsueh-Liang Chou , Chun-Wai Ng , Ruey-Hsin Liu
IPC分类号： H01L29/66 , H01L21/8234 , H01L29/40 , H01L29/423 , H01L29/78 , H01L21/265 , H01L21/28 , H01L29/08
CPC分类号： H01L29/66734 , H01L21/26586 , H01L21/266 , H01L21/2815 , H01L21/823456 , H01L21/823462 , H01L21/823487 , H01L21/823493 , H01L29/0886 , H01L29/1095 , H01L29/401 , H01L29/407 , H01L29/4236 , H01L29/42376 , H01L29/781 , H01L29/7813 , H01L29/7816 , H01L29/7835
摘要： A power MOS transistor comprises a drain contact plug formed over a first side of a substrate, a source contact plug formed over a second side of the substrate and a trench formed between the first drain/source region and the second drain/source region. The trench comprises a first gate electrode, a second gate electrode, wherein top surfaces of the first gate electrode and the second gate electrode are aligned with a bottom surface of drain region. The trench further comprises a field plate formed between the first gate electrode and the second gate electrode, wherein the field plate is electrically coupled to the source region.
摘要翻译：功率MOS晶体管包括形成在衬底的第一侧上的漏极接触插塞，形成在衬底的第二侧上的源极接触插塞和形成在第一漏极/源极区域和第二漏极/源极区域之间的沟槽。沟槽包括第一栅电极和第二栅电极，其中第一栅电极和第二栅电极的顶表面与漏区的底表面对准。沟槽还包括形成在第一栅极电极和第二栅极电极之间的场板，其中场板电耦合到源极区域。

6. 发明申请

US20140015047A1 Integrated Circuit Having a Vertical Power MOS Transistor 有权
标题翻译：具有垂直功率MOS晶体管的集成电路
公开(公告)号：US20140015047A1
公开(公告)日：2014-01-16
申请号：US13588070
申请日：2012-08-17
申请人： Chun-Wai Ng , Hsueh-Liang Chou , Po-Chih Su , Ruey-Hsin Liu
发明人： Chun-Wai Ng , Hsueh-Liang Chou , Po-Chih Su , Ruey-Hsin Liu
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/0922 , H01L21/26513 , H01L21/30604 , H01L21/76224 , H01L21/823418 , H01L21/823437 , H01L21/823481 , H01L21/823487 , H01L21/82385 , H01L21/823878 , H01L21/823885 , H01L21/823892 , H01L29/0649 , H01L29/0847 , H01L29/1095 , H01L29/4236 , H01L29/42364 , H01L29/66621 , H01L29/66666 , H01L29/78 , H01L29/7813 , H01L29/7827
摘要： An integrated circuit comprises a plurality of lateral devices and quasi vertical devices formed in a same semiconductor die. The quasi vertical devices include two trenches. A first trench is formed between a first drain/source region and a second drain/source region. The first trench comprises a dielectric layer formed in a bottom portion of the first trench and a gate region formed in an upper portion of the first trench. A second trench is formed on an opposite side of the second drain/source region from the first trench. The second trench is coupled between the second drain/source region and a buried layer, wherein the second trench is of a same depth as the first trench.
摘要翻译：集成电路包括形成在同一半导体管芯中的多个横向器件和准垂直器件。准垂直装置包括两个沟槽。在第一漏极/源极区域和第二漏极/源极区域之间形成第一沟槽。第一沟槽包括形成在第一沟槽的底部中的介质层和形成在第一沟槽的上部中的栅极区域。第二沟槽形成在与第一沟槽的第二漏极/源极区域相对的一侧上。第二沟槽耦合在第二漏极/源极区域和掩埋层之间，其中第二沟槽具有与第一沟槽相同的深度。

7. 发明申请

US20130320435A1 Trench Power MOSFET 有权
公开(公告)号：US20130320435A1
公开(公告)日：2013-12-05
申请号：US13486681
申请日：2012-06-01
申请人： Chun-Wai Ng , Hsueh-Liang Chou , Ruey-Hsin Liu , Po-Chih Su
发明人： Chun-Wai Ng , Hsueh-Liang Chou , Ruey-Hsin Liu , Po-Chih Su
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66734 , H01L21/02233 , H01L21/26586 , H01L21/266 , H01L29/0878 , H01L29/0882 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/4916 , H01L29/495 , H01L29/66727 , H01L29/7813
摘要： A device includes a semiconductor region of a first conductivity type, a trench extending into the semiconductor region, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion at a same level as, and contacting, the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type.

8. 发明授权

US08921934B2 FinFET with trench field plate 有权
标题翻译： FinFET与沟槽场板
公开(公告)号：US08921934B2
公开(公告)日：2014-12-30
申请号：US13546738
申请日：2012-07-11
申请人： Chun-Wai Ng , Hsueh-Liang Chou , Po-Chih Su , Ruey-Hsin Liu
发明人： Chun-Wai Ng , Hsueh-Liang Chou , Po-Chih Su , Ruey-Hsin Liu
IPC分类号： H01L29/66
CPC分类号： H01L29/401 , H01L29/0684 , H01L29/36 , H01L29/404 , H01L29/407 , H01L29/66704 , H01L29/7824 , H01L29/7825 , H01L29/7856
摘要： An integrated circuit device includes a pad layer having a body portion with a first doping type laterally adjacent to a drift region portion with a second doping type, a trench formed in the pad layer, the trench extending through an interface of the body portion and the drift region portion, a gate formed in the trench and over a top surface of the pad layer along the interface of the body portion and the drift region portion, an oxide formed in the trench on opposing sides of the gate, and a field plate embedded in the oxide on each of the opposing sides of the gate.
摘要翻译：一种集成电路器件包括：衬垫层，其具有主体部分，该主体部分具有横向邻近具有第二掺杂类型的漂移区域部分的第一掺杂型，形成在焊盘层中的沟槽，沟槽延伸穿过主体部分的界面和漂移区部分，形成在沟槽中的栅极和沿着主体部分和漂移区部分的界面的焊盘层的顶表面上的栅极，形成在栅极的相对侧上的沟槽中的氧化物和嵌入的场板在栅极的每个相对侧上的氧化物中。

9. 发明授权

US08884369B2 Vertical power MOSFET and methods of forming the same 有权
标题翻译：垂直功率MOSFET及其形成方法
公开(公告)号：US08884369B2
公开(公告)日：2014-11-11
申请号：US13486633
申请日：2012-06-01
申请人： Chun-Wai Ng , Hsueh-Liang Chou , Ruey-Hsin Liu , Po-Chih Su
发明人： Chun-Wai Ng , Hsueh-Liang Chou , Ruey-Hsin Liu , Po-Chih Su
IPC分类号： H01L29/66
CPC分类号： H01L29/66666 , H01L21/265 , H01L21/30604 , H01L21/823425 , H01L29/402 , H01L29/4232 , H01L29/66484 , H01L29/7827 , H01L29/7831
摘要： A device includes a semiconductor layer of a first conductivity type, and a first and a second body region over the semiconductor layer, wherein the first and the second body regions are of a second conductivity type opposite the first conductivity type. A doped semiconductor region of the first conductivity type is disposed between and contacting the first and the second body regions. A gate dielectric layer is disposed over the first and the second body regions and the doped semiconductor region. A first and a second gate electrode are disposed over the gate dielectric layer, and overlapping the first and the second body regions, respectively. The first and the second gate electrodes are physically separated from each other by a space, and are electrically interconnected. The space between the first and the second gate electrodes overlaps the doped semiconductor region.
摘要翻译：一种器件包括第一导电类型的半导体层以及半导体层上的第一和第二体区，其中第一和第二体区具有与第一导电类型相反的第二导电类型。第一导电类型的掺杂半导体区域设置在第一和第二主体区域之间并且与第一和第二主体区域接触。栅极电介质层设置在第一和第二主体区域和掺杂半导体区域上。第一和第二栅极设置在栅极介电层上方，分别与第一和第二体区重叠。第一和第二栅电极在物理上彼此分开一个空间，并被电互连。第一和第二栅电极之间的空间与掺杂半导体区域重叠。

10. 发明授权

US08823096B2 Vertical power MOSFET and methods for forming the same 有权
标题翻译：垂直功率MOSFET及其形成方法
公开(公告)号：US08823096B2
公开(公告)日：2014-09-02
申请号：US13486768
申请日：2012-06-01
申请人： Po-Chih Su , Hsueh-Liang Chou , Ruey-Hsin Liu , Chun-Wai Ng
发明人： Po-Chih Su , Hsueh-Liang Chou , Ruey-Hsin Liu , Chun-Wai Ng
IPC分类号： H01L29/66
CPC分类号： H01L29/66666 , H01L21/30604 , H01L21/743 , H01L21/76877 , H01L21/823456 , H01L21/823487 , H01L21/823493 , H01L27/088 , H01L27/098 , H01L29/0847 , H01L29/402 , H01L29/7827 , H01L29/7833
摘要： A device includes a semiconductor region in a semiconductor chip, a gate dielectric layer over the semiconductor region, and a gate electrode over the gate dielectric. A drain region is disposed at a top surface of the semiconductor region and adjacent to the gate electrode. A gate spacer is on a sidewall of the gate electrode. A dielectric layer is disposed over the gate electrode and the gate spacer. A conductive field plate is over the dielectric layer, wherein the conductive field plate has a portion on a drain side of the gate electrode. A deep metal via is disposed in the semiconductor region. A source electrode is underlying the semiconductor region, wherein the source electrode is electrically shorted to the conductive field plate through the deep metal via.
摘要翻译：一种器件包括半导体芯片中的半导体区域，半导体区域上的栅极电介质层和栅极电介质上的栅电极。漏极区域设置在半导体区域的顶表面并与栅电极相邻。栅极间隔物位于栅电极的侧壁上。电介质层设置在栅电极和栅间隔物上。导电场板在电介质层的上方，其中导电场板具有在栅电极的漏极侧的一部分。深金属通孔设置在半导体区域中。源电极位于半导体区域的下方，其中源电极通过深金属通孔与导电场板电短路。

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