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    • 5. 发明授权
    • Vertical power MOSFET and methods of forming the same
    • 垂直功率MOSFET及其形成方法
    • US08884369B2
    • 2014-11-11
    • US13486633
    • 2012-06-01
    • Chun-Wai NgHsueh-Liang ChouRuey-Hsin LiuPo-Chih Su
    • Chun-Wai NgHsueh-Liang ChouRuey-Hsin LiuPo-Chih Su
    • H01L29/66
    • H01L29/66666H01L21/265H01L21/30604H01L21/823425H01L29/402H01L29/4232H01L29/66484H01L29/7827H01L29/7831
    • A device includes a semiconductor layer of a first conductivity type, and a first and a second body region over the semiconductor layer, wherein the first and the second body regions are of a second conductivity type opposite the first conductivity type. A doped semiconductor region of the first conductivity type is disposed between and contacting the first and the second body regions. A gate dielectric layer is disposed over the first and the second body regions and the doped semiconductor region. A first and a second gate electrode are disposed over the gate dielectric layer, and overlapping the first and the second body regions, respectively. The first and the second gate electrodes are physically separated from each other by a space, and are electrically interconnected. The space between the first and the second gate electrodes overlaps the doped semiconductor region.
    • 一种器件包括第一导电类型的半导体层以及半导体层上的第一和第二体区,其中第一和第二体区具有与第一导电类型相反的第二导电类型。 第一导电类型的掺杂半导体区域设置在第一和第二主体区域之间并且与第一和第二主体区域接触。 栅极电介质层设置在第一和第二主体区域和掺杂半导体区域上。 第一和第二栅极设置在栅极介电层上方,分别与第一和第二体区重叠。 第一和第二栅电极在物理上彼此分开一个空间,并被电互连。 第一和第二栅电极之间的空间与掺杂半导体区域重叠。