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1. 发明授权

US06939803B2 Method for forming conductor reservoir volume for integrated circuit interconnects 有权
标题翻译：用于形成集成电路互连的导体储存器容积的方法
公开(公告)号：US06939803B2
公开(公告)日：2005-09-06
申请号：US10225656
申请日：2002-08-21
申请人： Amit P. Marathe , Pin-Chin Connie Wang , Christy Mei-Chu Woo
发明人： Amit P. Marathe , Pin-Chin Connie Wang , Christy Mei-Chu Woo
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/44
CPC分类号： H01L21/76844 , H01L21/76838 , H01L21/76873 , H01L21/76874 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A first dielectric layer on the device dielectric layer has an opening formed therein including a conductor reservoir volume. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. A second dielectric layer is formed on the first dielectric layer and has a second channel and via opening provided therein. A barrier layer lines the second channel and via opening except over the first channel opening. A conductor core fills the second channel and via opening over the barrier layer and the first conductor core to form the second channel and via. The conductor reservoir volume provides a supply of conductor material to prevent the formation of voids in the first channel and in the via.
摘要翻译：提供了具有半导体器件的半导体衬底的集成电路及其制造方法。在半导体衬底上形成器件电介质层。器件介电层上的第一介电层具有形成在其中的开口，其中包括导体储存器体积。屏障层对通道开口进行排列。导体芯填充阻挡层上的开口。第二电介质层形成在第一电介质层上并具有设置在其中的第二通道和通孔。除了第一通道开口之外，阻挡层沿着第二通道和通孔开口。导体芯填充第二通道并通过阻挡层和第一导体芯上的开口形成第二通道和通孔。导体储存器容积提供导体材料供应，以防止在第一通道和通孔中形成空隙。

2. 发明授权

US06472757B2 Conductor reservoir volume for integrated circuit interconnects 有权
公开(公告)号：US06472757B2
公开(公告)日：2002-10-29
申请号：US09758994
申请日：2001-01-11
申请人： Amit P. Marathe , Pin-Chin Connie Wang , Christy Mei-Chu Woo
发明人： Amit P. Marathe , Pin-Chin Connie Wang , Christy Mei-Chu Woo
IPC分类号： H01L23528
CPC分类号： H01L21/76844 , H01L21/76838 , H01L21/76873 , H01L21/76874 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A first dielectric layer on the device dielectric layer has an opening formed therein including a conductor reservoir volume. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. A second dielectric layer is formed on the first dielectric layer and has a second channel and via opening provided therein. A barrier layer lines the second channel and via opening except over the first channel opening. A conductor core fills the second channel and via opening over the barrier layer and the first conductor core to form the second channel and via. The conductor reservoir volume provides a supply of conductor material to prevent the formation of voids in the first channel and in the via.

3. 发明授权

US06455938B1 Integrated circuit interconnect shunt layer 有权
标题翻译：集成电路互连分流层
公开(公告)号：US06455938B1
公开(公告)日：2002-09-24
申请号：US09905479
申请日：2001-07-13
申请人： Pin-Chin Connie Wang , Amit P. Marathe , Christy Mei-Chu Woo
发明人： Pin-Chin Connie Wang , Amit P. Marathe , Christy Mei-Chu Woo
IPC分类号： H01L2945
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided for an integrated circuit on a semiconductor substrate grated circuit having a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. A barrier layer lines the opening, and a first conductor core fills the opening over the barrier layer. A second dielectric layer is formed on the first dielectric layer and has a second channel and via opening provided therein. A shunt layer is in the via opening above the conductor core. A barrier layer lines the second channel and via opening over the shunt layer and the second dielectric layer. A conductor core fills the second channel and via opening over the barrier layer and the first conductor core to form the second channel and via.
摘要翻译：提供了一种用于具有半导体器件的半导体衬底格栅电路上的集成电路的集成电路及其制造方法。电介质层位于半导体衬底上，其中设有开口。阻挡层对开口进行排列，并且第一导体芯填充阻挡层上的开口。第二电介质层形成在第一电介质层上并具有设置在其中的第二通道和通孔。并联层位于导体芯上方的通孔中。阻挡层将第二通道和通过开口穿过并联层和第二介电层。导体芯填充第二通道并通过阻挡层和第一导体芯上的开口形成第二通道和通孔。

4. 发明授权

US06590288B1 Selective deposition in integrated circuit interconnects 有权
标题翻译：集成电路互连中的选择性沉积
公开(公告)号：US06590288B1
公开(公告)日：2003-07-08
申请号：US09874549
申请日：2001-06-04
申请人： Christy Mei-Chu Woo , Pin-Chin Connie Wang , Amit P. Marathe
发明人： Christy Mei-Chu Woo , Pin-Chin Connie Wang , Amit P. Marathe
IPC分类号： H01L2348
CPC分类号： H01L21/76846 , H01L21/28562 , H01L21/32051 , H01L21/76873 , H01L23/5222 , H01L23/53223 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A first conductor core is connected to the semiconductor device. A low dielectric constant dielectric layer is formed over the semiconductor substrate and has an opening formed therein. A first barrier layer is deposited over the first conductor core. A second barrier layer is deposited to line the low dielectric constant dielectric layer and the first barrier layer. A third barrier layer is deposited to line the second barrier layer. A second conductor core is deposited to fill the opening over the third barrier layer.
摘要翻译：提供了具有半导体器件的半导体衬底的集成电路及其制造方法。第一导体芯连接到半导体器件。在半导体衬底上形成低介电常数介质层，并且其中形成有开口。第一阻挡层沉积在第一导体芯上。沉积第二阻挡层以对低介电常数介电层和第一阻挡层进行排列。沉积第三阻挡层以使第二阻挡层成线。沉积第二导体芯以填充第三阻挡层上的开口。

5. 发明授权

US06531780B1 Via formation in integrated circuit interconnects 有权
标题翻译：通过集成电路互连形成
公开(公告)号：US06531780B1
公开(公告)日：2003-03-11
申请号：US09894289
申请日：2001-06-27
申请人： Christy Mei-Chu Woo , Pin-Chin Connie Wang , Amit P. Marathe
发明人： Christy Mei-Chu Woo , Pin-Chin Connie Wang , Amit P. Marathe
IPC分类号： H01L2348
CPC分类号： H01L21/76844 , H01L21/76865 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , Y10S438/927 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A first channel dielectric layer over the semiconductor has a first opening lined by a first barrier layer and filled by a first conductor core. A via dielectric layer having a via opening which is open to the first conductor core is formed over the first channel dielectric layer. A second channel dielectric layer with a second opening which is open to the via is formed over the via dielectric layer. A second conductor core fills the via and second channel openings. A second barrier layer lining the via and second channel openings under the second conductor core forms a barrier between the second conductor core and the via and second channel dielectric layers, but does not form a barrier between the first and the second conductor cores.
摘要翻译：提供了具有半导体器件的半导体衬底的集成电路及其制造方法。半导体上的第一通道电介质层具有由第一阻挡层衬里并由第一导体芯填充的第一开口。在第一沟道电介质层上形成具有通向第一导体芯开口的通路开口的通孔电介质层。在通孔电介质层上形成具有对通孔开口的第二开口的第二通道电介质层。第二导体芯填充通孔和第二通道开口。衬在第二导体芯下方的通孔和第二通道开口的第二阻挡层在第二导体芯与通孔和第二通道介电层之间形成阻挡层，但不形成第一和第二导体芯之间的阻挡层。

6. 发明授权

US06462416B1 Gradated barrier layer in integrated circuit interconnects 有权
标题翻译：集成电路互连中的梯度势垒层
公开(公告)号：US06462416B1
公开(公告)日：2002-10-08
申请号：US09905469
申请日：2001-07-13
申请人： Amit P. Marathe , Pin-Chin Connie Wang , Christy Mei-Chu Woo
发明人： Amit P. Marathe , Pin-Chin Connie Wang , Christy Mei-Chu Woo
IPC分类号： H01L2348
CPC分类号： H01L21/76846 , H01L21/76843 , H01L21/76873 , H01L23/53209 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer with an opening formed therein is formed on the semiconductor substrate. A barrier layer of barrier metal and barrier compound lines the opening, the barrier layer having a dielectric layer proximate and distal regions. The barrier layer has no barrier metal adjacent the dielectric layer proximate region and all barrier metal in the dielectric layer distal region, the barrier layer has all barrier compound adjacent the dielectric layer proximate region and no barrier compound before the dielectric layer distal region. A conductor core is over the barrier layer fills the opening and connects to the semiconductor device.
摘要翻译：提供了具有半导体器件的半导体衬底的集成电路及其制造方法。其中形成有开口的器件介电层形成在半导体衬底上。势垒金属和屏障化合物的阻挡层划分开口，阻挡层具有接近和远端区域的电介质层。阻挡层在电介质层邻近区域附近没有阻挡金属，并且介电层远侧区域中的所有势垒金属，阻挡层具有邻近电介质层邻近区域的所有阻挡化合物，并且在电介质层远端区域之前没有阻挡化合物。阻挡层之上的导体芯填充开口并连接到半导体器件。

7. 发明授权

US06727592B1 Copper interconnect with improved barrier layer 有权
标题翻译：铜互连具有改进的阻挡层
公开(公告)号：US06727592B1
公开(公告)日：2004-04-27
申请号：US10079515
申请日：2002-02-22
申请人： Christy Mei-Chu Woo , John E. Sanchez , Darrell M. Erb , Amit P. Marathe
发明人： Christy Mei-Chu Woo , John E. Sanchez , Darrell M. Erb , Amit P. Marathe
IPC分类号： H01L2348
CPC分类号： H01L21/76843 , H01L21/76846 , H01L21/76868 , H01L21/76871 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A Cu interconnect, e.g.; a dual damascene structure, is formed with improved electromigration resistance and increased via chain yield by depositing a barrier layer in an opening by CVD, depositing a flash layer of &agr;-Ta by PVD, at a thickness less than 30 Å, on the bottom of the barrier layer, depositing a seedlayer and then filling the opening with Cu. Embodiments include depositing a thin &agr;-Ta layer, as at a thickness less than 10 Å, and/or as discontinuous regions of clusters of atoms on sides of the opening.
摘要翻译： Cu互连，例如通过在开口中沉积阻挡层通过CVD沉积形成具有改善的电迁移阻力并通过链产量增加的双镶嵌结构，通过PVD沉积α-Ta的闪光层，厚度小于30埃阻挡层，沉积种子层，然后用Cu填充开口。实施方案包括沉积厚度小于的薄的α-Ta层和/或沉积在开口侧面上的原子簇的不连续区域。

8. 发明授权

US06531777B1 Barrier metal integrity testing using a dual level line to line leakage testing pattern and partial CMP 失效
标题翻译：屏蔽金属完整性测试采用双层线对线路泄漏测试模式和部分CMP
公开(公告)号：US06531777B1
公开(公告)日：2003-03-11
申请号：US09599839
申请日：2000-06-22
申请人： Christy Mei-Chu Woo , Amit P. Marathe
发明人： Christy Mei-Chu Woo , Amit P. Marathe
IPC分类号： H01L2348
CPC分类号： H01L21/76843 , H01L22/14 , H01L22/34
摘要： A structure and method for determining barrier layer integrity for multi-level copper metallization structures in integrated circuit manufacturing. Novel testing structures prevent any conducting residues of the copper CMP from diffusing into the dielectric layer. Barrier layer integrity is tested by performing leakage or other electrical measurements between copper features on two different metal levels.
摘要翻译：一种用于确定集成电路制造中多级铜金属化结构的阻挡层完整性的结构和方法。新的测试结构防止铜CMP的任何导电残余物扩散到电介质层中。通过在两个不同的金属层上的铜特征之间执行泄漏或其他电气测量来测试阻挡层的完整性。

9. 发明授权

US06952052B1 Cu interconnects with composite barrier layers for wafer-to-wafer uniformity 有权
标题翻译： Cu与复合阻挡层互连，用于晶片到晶片的均匀性
公开(公告)号：US06952052B1
公开(公告)日：2005-10-04
申请号：US10811860
申请日：2004-03-30
申请人： Amit P. Marathe , Connie Pin-Chin Wang , Christy Mei-Chu Woo
发明人： Amit P. Marathe , Connie Pin-Chin Wang , Christy Mei-Chu Woo
IPC分类号： H01L21/768 , H01L23/48 , H01L29/40
CPC分类号： H01L21/76846
摘要： A composite α-Ta/ graded tantalum nitride /TaN barrier layer is formed in Cu interconnects with a structure designed for improved wafer-to-wafer uniformity, electromigration resistance and reliability, reduced contact resistance, and increased process margin. Embodiments include a dual damascene structure in a low-k interlayer dielectric comprising Cu and a composite barrier layer comprising an initial layer of TaN on the low-k material, a graded layer of tantalum nitride on the initial TaN layer and a continuous α-Ta layer on the graded tantalum nitride layer. Embodiments include forming the initial TaN layer at a thickness sufficient to ensure deposition of α-Ta, e.g., as at a thickness of bout 50 Å to about 100 Å. Embodiments include composite barrier layers having a thickness ratio of α-Ta and graded tantalum nitride: initial TaN of about 2.5:1 to about 3.5:1 for improved electromigration resistance and wafer-to-wafer uniformity.
摘要翻译：在Cu互连中形成复合α-Ta /分级氮化钽/ TaN阻挡层，其具有为提高晶片到晶片的均匀性，电迁移电阻和可靠性，降低的接触电阻和增加的工艺裕度而设计的结构。实施例包括在包含Cu的低k层间电介质中的双镶嵌结构和在低k材料上包含TaN的初始层的复合势垒层，初始TaN层上的氮化钽梯度层和连续的α-Ta 层叠在梯度氮化钽层上。实施方案包括以足以确保α-Ta沉积的厚度形成初始TaN层，例如在50至大约的厚度。实施例包括厚度比为α-Ta和梯度氮化钽的复合阻挡层：初始TaN为约2.5:1至约3.5:1，以提高电迁移阻力和晶片与晶片的均匀性。

10. 发明授权

US06599835B1 Testing dielectric and barrier layers for integrated circuit interconnects 失效
标题翻译：测试用于集成电路互连的电介质层和阻挡层
公开(公告)号：US06599835B1
公开(公告)日：2003-07-29
申请号：US09905470
申请日：2001-07-13
申请人： Amit P. Marathe , Christy Mei-Chu Woo
发明人： Amit P. Marathe , Christy Mei-Chu Woo
IPC分类号： H01L2144
CPC分类号： G01R31/2853 , G01R31/129 , G01R31/2831
摘要： An integrated circuit test system and method therefor is provided having a semiconductor substrate with an electrical ground and a source of electrical potential. A dielectric layer with first and second openings is formed on the semiconductor substrate. First and second barrier layers are deposited on the dielectric layer to line the openings. A first conductor core is deposited over the first barrier layer to fill the first opening and is connected to a source of electrical potential. A second conductor core is deposited over the second barrier layer to fill the second opening and is connected to the electrical ground. A current measuring device is provided to measure leakage current flow between the first and second conductor cores.
摘要翻译：提供了具有具有电接地和电势源的半导体衬底的集成电路测试系统及其方法。在半导体衬底上形成具有第一和第二开口的电介质层。第一和第二阻挡层沉积在电介质层上以对开口进行排列。第一导体芯沉积在第一阻挡层上以填充第一开口并连接到电势源。第二导体芯沉积在第二阻挡层上以填充第二开口并且连接到电接地。提供电流测量装置以测量第一和第二导体芯之间的漏电流。

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