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1. 发明授权

US06727592B1 Copper interconnect with improved barrier layer 有权
标题翻译：铜互连具有改进的阻挡层
公开(公告)号：US06727592B1
公开(公告)日：2004-04-27
申请号：US10079515
申请日：2002-02-22
申请人： Christy Mei-Chu Woo , John E. Sanchez , Darrell M. Erb , Amit P. Marathe
发明人： Christy Mei-Chu Woo , John E. Sanchez , Darrell M. Erb , Amit P. Marathe
IPC分类号： H01L2348
CPC分类号： H01L21/76843 , H01L21/76846 , H01L21/76868 , H01L21/76871 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A Cu interconnect, e.g.; a dual damascene structure, is formed with improved electromigration resistance and increased via chain yield by depositing a barrier layer in an opening by CVD, depositing a flash layer of &agr;-Ta by PVD, at a thickness less than 30 Å, on the bottom of the barrier layer, depositing a seedlayer and then filling the opening with Cu. Embodiments include depositing a thin &agr;-Ta layer, as at a thickness less than 10 Å, and/or as discontinuous regions of clusters of atoms on sides of the opening.
摘要翻译： Cu互连，例如通过在开口中沉积阻挡层通过CVD沉积形成具有改善的电迁移阻力并通过链产量增加的双镶嵌结构，通过PVD沉积α-Ta的闪光层，厚度小于30埃阻挡层，沉积种子层，然后用Cu填充开口。实施方案包括沉积厚度小于的薄的α-Ta层和/或沉积在开口侧面上的原子簇的不连续区域。

2. 发明授权

US07157795B1 Composite tantalum nitride/tantalum copper capping layer 有权
标题翻译：复合氮化钽/钽铜覆盖层
公开(公告)号：US07157795B1
公开(公告)日：2007-01-02
申请号：US10934511
申请日：2004-09-07
申请人： Darrell M. Erb , Steven C. Avanzino , Christy Mei-Chu Woo
发明人： Darrell M. Erb , Steven C. Avanzino , Christy Mei-Chu Woo
IPC分类号： H01L23/48
CPC分类号： H01L21/2855 , H01L21/76843 , H01L21/76846 , H01L21/76849 , Y10S438/927
摘要： Electromigration and stress migration of Cu interconnects are significantly reduced by forming a composite capping layer comprising a layer of tantalum nitride on the upper surface of the inlaid Cu and a layer of α-Ta on the titanium nitride layer. Embodiments include forming a recess in an upper surface of an upper surface of Cu inlaid in a dielectric layer, depositing a layer of titanium nitride of a thickness of 20 Å to 100 Å and then depositing a layer of α-Ta at a thickness of 200 Å to 500 Å.
摘要翻译：通过在镶嵌Cu的上表面上形成包含氮化钽层的复合顶盖层和氮化钛层上的α-Ta层，显着降低了铜互连的电迁移和应力迁移。实施例包括在介电层中嵌入的Cu的上表面的上表面中形成凹陷，沉积厚度为的厚度为的二氧化钛层，然后沉积厚度为200埃的α-Ta层 Å至500Å。

3. 发明授权

US07071564B1 Composite tantalum capped inlaid copper with reduced electromigration and reduced stress migration 有权
标题翻译：复合钽封装铜，具有减少的电迁移和减少的应力迁移
公开(公告)号：US07071564B1
公开(公告)日：2006-07-04
申请号：US10791904
申请日：2004-03-04
申请人： Darrell M. Erb , Steven Avanzino , Christy Mei-Chu Woo
发明人： Darrell M. Erb , Steven Avanzino , Christy Mei-Chu Woo
IPC分类号： H01L29/40 , H01L23/12
CPC分类号： H01L23/53238 , H01L21/76843 , H01L21/76846 , H01L21/76849 , H01L2924/0002 , H01L2924/00
摘要： The electromigration and stress migration of Cu interconnects is significantly reduced by forming a composite capping layer comprising a layer of β-Ta on the upper surface of the inlaid Cu, a layer of tantalum nitride on the β-Ta layer and a layer of α-Ta on the tantalum nitride layer. Embodiments include forming a recess in an upper surface of Cu inlaid in a dielectric layer, depositing a layer of β-Ta at a thickness of 25 Å to 40 Å, depositing a layer of tantalum nitride at a thickness of 20 Å to 100 Å and then depositing a layer of α-Ta at a thickness of 200 Å to 500 Å. Embodiments further include forming an overlying dielectric layer, forming an opening therein, e.g., a via opening or a dual damascene opening, lining the opening with α-Ta, and filling the opening with Cu in electrical contact with the underlying inlaid Cu.
摘要翻译：通过在嵌入的Cu的上表面上形成包含β-Ta层的复合顶盖层，β-Ta层上的氮化钽层和α-Ta层的一层复合覆盖层，显着降低了铜互连的电迁移和应力迁移， Ta在氮化钽层上。实施例包括在介电层中嵌入的Cu的上表面中形成凹陷，沉积厚度为的Å-Ta层，沉积厚度为Å至100埃的氮化钽层，以及然后沉积厚度为200埃至500埃的α-Ta层。实施例还包括形成覆盖的介电层，在其中形成开口，例如通孔开口或双镶嵌开口，用α-Ta衬套开口，以及用与电镀底层Cu接触的Cu填充开口。

4. 发明授权

US06979625B1 Copper interconnects with metal capping layer and selective copper alloys 有权
标题翻译：铜互连与金属覆盖层和选择性铜合金
公开(公告)号：US06979625B1
公开(公告)日：2005-12-27
申请号：US10704595
申请日：2003-11-12
申请人： Christy Mei-Chu Woo , Connie Pin-Chin Wang , Darrell M. Erb
发明人： Christy Mei-Chu Woo , Connie Pin-Chin Wang , Darrell M. Erb
IPC分类号： H01L21/3213 , H01L21/331 , H01L21/768 , H01L23/532
CPC分类号： H01L21/76877 , H01L21/32134 , H01L21/7684 , H01L21/76849 , H01L21/76886 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： High reliable copper interconnects are formed with copper or a low resistivity copper alloy filling relatively narrow openings and partially filling relatively wider openings and a copper alloy having improved electromigration resistance selectively deposited in the relatively wider openings. The filled openings are recessed and a metal capping layer deposited followed by CMP. The metal capping layer prevents diffusion along the copper-capping layer interface while the copper alloy filling the relatively wider openings impedes electromigration along the grain boundaries.
摘要翻译：通过铜或低电阻铜合金形成高可靠的铜互连，填充较窄的开口并部分地填充相对较宽的开口，并且具有改进的电迁移电阻的铜合金选择性地沉积在较宽的开口中。填充的开口凹陷并且金属覆盖层沉积，然后沉积CMP。金属覆盖层防止沿着铜覆盖层界面的扩散，而填充相对较宽的开口的铜合金阻止沿着晶界的电迁移。

5. 发明授权

US06717266B1 Use of an alloying element to form a stable oxide layer on the surface of metal features 有权
标题翻译：使用合金元素在金属表面上形成稳定的氧化物层
公开(公告)号：US06717266B1
公开(公告)日：2004-04-06
申请号：US10175393
申请日：2002-06-18
申请人： Amit P. Marathe , Darrell M. Erb
发明人： Amit P. Marathe , Darrell M. Erb
IPC分类号： H01L2348
CPC分类号： H01L23/53238 , H01L21/76886 , H01L21/76888 , H01L2924/0002 , H01L2924/00
摘要： The electromigration resistance of planarized metallization patterns, for example copper, inlaid in the surface of a layer of dielectric material, is enhanced by a process comprising blanket-depositing on the planarized, upper surfaces of the metallization features and the dielectric layer at least one alloying layer comprising at least one alloying element for the metal of the features, and diffusing the at least one alloying element within the metallization features to effect alloying therewith. The at least one alloying element diffused within the metallization features, under conditions wherein an oxide layer forms on the surface of the metallization features, forms a stable oxide layer on the surface of the metallization features. The stable oxide layer reduces electromigration from the metallization features along the oxide layer.
摘要翻译：通过包括在金属化特征和电介质层的平坦化的上表面上覆盖沉积至少一种合金化的方法来增强镶嵌在介电材料层的表面中的平坦化金属化图案（例如铜）的电迁移阻力该层包括用于特征金属的至少一个合金元素，并且将金属化特征内的至少一个合金元素扩散以实现与其的合金化。在其中在金属化特征的表面上形成氧化物层的条件下，在金属化特征内扩散的至少一种合金元素在金属化特征的表面上形成稳定的氧化物层。稳定的氧化物层减少沿着氧化物层的金属化特征的电迁移。

6. 发明授权

US06869878B1 Method of forming a selective barrier layer using a sacrificial layer 失效
标题翻译：使用牺牲层形成选择性阻挡层的方法
公开(公告)号：US06869878B1
公开(公告)日：2005-03-22
申请号：US10367406
申请日：2003-02-14
申请人： Ercan Adem , John E. Sanchez , Darrell M. Erb , Suzette K. Pangrle
发明人： Ercan Adem , John E. Sanchez , Darrell M. Erb , Suzette K. Pangrle
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/76849 , H01L21/76807 , H01L21/76885
摘要： The reliability and performance of planarized metallization patterns in an electrical device, for example copper, inlaid in the surface of a layer of dielectric material overlying a semiconductor wafer substrate, are enhanced by a method for reliably depositing a barrier layer selective to the metallization patterns. The method comprises forming a sacrificial dielectric layer above a substrate. Metallization patterns are formed in the sacrificial dielectric layer. The barrier layer is selectively deposited on the metallization patterns. Portions of the barrier material undesirably deposited on the sacrificial dielectric layer are removed by removing the sacrificial dielectric layer, thus preventing bridging of adjacent metallization features by the barrier layer portions. An interlevel dielectric layer is then formed in place of the sacrificial dielectric layer. The selectively deposited barrier layer advantageously reduces parasitic capacitance between metallization features in comparison to a conventional blanket-deposited silicon nitride barrier layer.
摘要翻译：通过用于可靠地沉积对金属化图案有选择性的阻挡层的方法，增强了嵌入在覆盖在半导体晶片衬底上的介电材料层的表面中的电子器件（例如铜）中的平面化金属化图案的可靠性和性能。该方法包括在衬底上形成牺牲介电层。在牺牲电介质层中形成金属化图案。阻挡层选择性地沉积在金属化图案上。通过去除牺牲介电层来去除不期望地沉积在牺牲介电层上的阻挡材料的部分，从而防止相邻金属化特征由阻挡层部分桥接。然后形成层间电介质层代替牺牲电介质层。与常规的覆盖层沉积的氮化硅阻挡层相比，选择性沉积的势垒层有利地减小了金属化特征之间的寄生电容。

7. 发明授权

US06454916B1 Selective electroplating with direct contact chemical polishing 失效
标题翻译：选择性电镀与直接接触化学抛光
公开(公告)号：US06454916B1
公开(公告)日：2002-09-24
申请号：US09477810
申请日：2000-01-05
申请人： Fei Wang , Steven C. Avanzino , Darrell M. Erb
发明人： Fei Wang , Steven C. Avanzino , Darrell M. Erb
IPC分类号： C25D1700
CPC分类号： C25D5/22 , B23H5/08 , C25D7/12 , C25D17/001
摘要： A deposition tool and a method for depositing a material within the recesses in a substrate of semiconductor wafer employs a rotatable diffuser that diffuses the plating material onto the top surface of a substrate. The diffuser is placed into contact with the semiconductor wafer and rotated while the plating material is applied through apertures in the diffuser. The plating material fills recesses patterned into the substrate of the semiconductor wafer but is prevented from forming to a significant degree on the top surface of the semiconductor wafer due to the contact and rotation of the diffuser. Since the plating material is not deposited on the top surface of the semiconductor wafer to any significant degree, chemical mechanical polishing (CMP) planarization is significantly reduced or completely eliminated.
摘要翻译：沉积工具和用于在半导体晶片的衬底内的凹槽内沉积材料的方法采用将电镀材料扩散到衬底顶表面上的可旋转漫射器。扩散器被放置成与半导体晶片接触并且当电镀材料通过扩散器中的孔施加时旋转。电镀材料填充图案化到半导体晶片的衬底中的凹槽，但是由于扩散器的接触和旋转，防止了在半导体晶片的顶表面上形成很大程度。由于电镀材料没有以任何显着的程度沉积在半导体晶片的顶表面上，所以化学机械抛光（CMP）平面化被显着地减少或完全消除。

8. 发明授权

US06169034A Chemically removable Cu CMP slurry abrasive 有权
标题翻译：化学去除Cu CMP浆料研磨剂
公开(公告)号：US06169034A
公开(公告)日：2001-01-02
申请号：US09199352
申请日：1998-11-25
申请人： Steven C. Avanzino , Darrell M. Erb , Diana M. Schonauer , Kai Yang
发明人： Steven C. Avanzino , Darrell M. Erb , Diana M. Schonauer , Kai Yang
IPC分类号： H01L21461
CPC分类号： H01L21/3212 , C09G1/02 , C09K3/1463
摘要： Abrasion of Cu metallization during CMP is reduced and residual slurry particulate removal facilitated by employing a CMP slurry containing a dispersion of soft mineral particles having high solubility in dilute acids. Embodiments include CMP Cu metallization with a slurry containing magnesium oxide particles and removing any residual magnesium oxide particles after CMP with an organic acid, such as citric acid or acetic acid, or a dilute inorganic acid, such as hydrochloric, phosphoric, boric or fluoboric acid.
摘要翻译：在CMP期间对Cu金属化的磨损降低，并且通过使用含有在稀酸中具有高溶解度的软矿物颗粒的分散体的CMP浆料来促进残留的浆料颗粒去除。实施方案包括用含有氧化镁颗粒的浆料进行CMP Cu金属化，并在CMP之后用有机酸如柠檬酸或乙酸或稀无机酸如盐酸，磷酸，硼酸或氟硼酸除去残留的氧化镁颗粒。

9. 发明授权

US4745454A High capacity semiconductor capacitance device structure 失效
标题翻译：大容量半导体电容器件结构
公开(公告)号：US4745454A
公开(公告)日：1988-05-17
申请号：US926600
申请日：1986-11-03
申请人： Darrell M. Erb
发明人： Darrell M. Erb
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/92 , H01L27/02 , H01L29/78
CPC分类号： H01L27/1085 , H01L27/10805
摘要： The present invention provides for a method for manufacturing a charge storage region in a semiconductor substrate for a memory cell in a dynamic RAM, comprising forming an insulating layer on the substrate, forming a masking layer over the insulating layer, forming at least one aperture in the masking layer, the aperture defining the charge storage region in the semiconductor substrate, implanting dopant ions of a first polarity through the aperture for diffusion through the substrate, and implanting dopant ions of a second polarity through the aperture for diffusion through the substrate to a lesser degree than the first polarity dopant diffusion so that the diffusion of the first polarity dopant with respect to the diffusion of the second polarity dopant forms a P-N junction substantially aligned with the edge of the masking layer aperture to define the periphery of the charge storage region. One way of diffusing the second polarity dopant to a lesser degree than the first polarity dopant in the substrate is to select a first polarity dopant which has a diffusivity greater than the second polarity dopant. Another way of achieving the desired diffusion of first polarity dopant with respect to the second polarity dopant is to select the two dopants with diffusivities approximately equal and to diffuse the first polarity dopant before the second polarity dopants is implanted into the semiconductor substrate.
摘要翻译：本发明提供一种在动态RAM中用于存储单元的半导体衬底中的电荷存储区域的制造方法，包括在衬底上形成绝缘层，在绝缘层上形成掩模层，形成至少一个孔掩模层，限定半导体衬底中的电荷存储区域的孔，通过孔径注入第一极性的掺杂离子以通过衬底扩散，以及通过孔径注入第二极性的掺杂剂离子，以通过衬底扩散到比第一极性掺杂剂扩散程度小，使得第一极性掺杂剂相对于第二极性掺杂剂的扩散的扩散形成基本上与掩模层孔的边缘对准的PN结，以限定电荷存储区域的周边。将第二极性掺杂剂扩散到比衬底中的第一极性掺杂剂更小程度的一种方法是选择具有大于第二极性掺杂剂的扩散率的第一极性掺杂剂。实现第一极性掺杂剂相对于第二极性掺杂剂的期望扩散的另一种方法是选择具有大致相等的扩散率的两种掺杂剂，并且在将第二极性掺杂剂注入到半导体衬底之前扩散第一极性掺杂剂。

10. 发明授权

US06465889B1 Silicon carbide barc in dual damascene processing 有权
标题翻译：碳化硅棒在双镶嵌加工
公开(公告)号：US06465889B1
公开(公告)日：2002-10-15
申请号：US09778109
申请日：2001-02-07
申请人： Ramkumar Subramanian , Fei Wang , Lynne A. Okada , Calvin T. Gabriel , Darrell M. Erb
发明人： Ramkumar Subramanian , Fei Wang , Lynne A. Okada , Calvin T. Gabriel , Darrell M. Erb
IPC分类号： H01L2348
CPC分类号： H01L21/76808 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The dimensional accuracy of trenches and, hence, the width of metal lines, in damascene interconnection structures is improved by employing silicon carbide as a capping layer/BARC on an underlying metal feature, e.g., Cu. Embodiments include via first-trench last dual damascene techniques employing a silicon carbide capping layer/BARC having an extinction coefficient (k) of about −0.2 to about −0.5, without the need for a middle etch stop layer, thereby improving efficiency by reducing the number of processing steps.
摘要翻译：通过在下面的金属特征例如Cu上使用碳化硅作为覆盖层/ BARC来改善镶嵌互连结构中的沟槽的尺寸精度以及因此的金属线的宽度。实施例包括采用采用碳消耗系数（k）约-0.2至约-0.5的碳化硅覆盖层/ BARC的第一沟槽最后双镶嵌技术，而不需要中间蚀刻停止层，从而通过减少处理步骤数

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