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1. 发明授权

US4805192A Method and apparatus for pulse code modulation combination chip having an improved autozero circuit 失效
标题翻译：具有改进的自动调零电路的脉冲编码调制组合芯片的方法和装置
公开(公告)号：US4805192A
公开(公告)日：1989-02-14
申请号：US936369
申请日：1986-12-01
申请人： Pierangelo Confalonieri , Daniel Senderowicz , Augusto Tirelli
发明人： Pierangelo Confalonieri , Daniel Senderowicz , Augusto Tirelli
IPC分类号： H03K5/08 , H03M1/00 , H03M1/10 , H04B14/04 , H03M1/12
CPC分类号： H03M1/0607 , H03M1/825
摘要： In a Pulse Code Modulated (PCM) circuit chip, apparatus in the transmit path to compensate for an offset voltage signal from a band-pass filter includes an up-down counter which is actuated to provide a digital value equivalent to the offset signal and a digital to analog converter coupled to the counter to provide an analog signal representing the digital value in the counter. During an initialization phase, the counter is incremented until the digital value of the counter provides, by means of the digital to analog converter, an analog signal that compensates for the off-set signal. After the initialization phase when the band-pass filter's offset voltage is compensated, then other circuitry including an exclusive OR gate and an associated overflow counter are used to eneable or disable the up-down counter to insure that the PCM output signal is an accurate representation of the analog input signal. The up-down counter, during the operation phase following the initialization phase, is only enabled when the analog input signal is not present.
摘要翻译：在脉冲编码调制（PCM）电路芯片中，用于补偿来自带通滤波器的偏移电压信号的传输路径中的装置包括被启动以提供与偏移信号等效的数字值的升降计数器，以及数模转换器耦合到计数器以提供表示计数器中的数字值的模拟信号。在初始化阶段期间，计数器递增，直到计数器的数字值通过数模转换器提供补偿偏移信号的模拟信号。在对带通滤波器的偏移电压进行补偿的初始化阶段之后，使用包括异或门和相关联的溢出计数器的其它电路来使能或禁止升降计数器，以确保PCM输出信号是准确的表示的模拟输入信号。在初始化阶段之后的运行阶段，只有当模拟输入信号不存在时，才能使能上拉计数器。

2. 发明授权

US4799042A Apparatus and method for offset voltage correction in an analog to digital converter 失效
标题翻译：用于模数转换器中偏移电压校正的装置和方法
公开(公告)号：US4799042A
公开(公告)日：1989-01-17
申请号：US936368
申请日：1986-12-01
申请人： Pierangelo Confalonieri , Daniel Senderowicz , Germano Nicollini
发明人： Pierangelo Confalonieri , Daniel Senderowicz , Germano Nicollini
IPC分类号： H03M1/10 , H03M1/00 , H03M1/46 , H03M1/80 , H03M1/06
CPC分类号： H03M1/1047 , H03M1/464 , H03M1/804
摘要： A charge redistribution analog-to-digital converter is described that permits their ncorporation of offset voltage correction to provide an accurate reflection in the digitalized output signal of the analog input signal. In a distributed capacitor successive approximation device, additional capacitors are added both to a most significant bit array group of capacitors and to a least significant array group of capacitors that are used in conjunction with the offset voltage. The value of the offset voltage is stored in a register and the register determines various switch positions that determine the value of the offset voltage incorporated in the final output voltage.
摘要翻译：描述了一种电荷再分配模数转换器，其允许其偏移电压校正的组合在模拟输入信号的数字化输出信号中提供准确的反射。在分布式电容器逐次逼近装置中，附加电容器被添加到最高有效比特阵列组的电容器和与偏移电压结合使用的最不重要的阵列组的电容器。偏移电压的值存储在寄存器中，并且寄存器确定确定最终输出电压中所包含的偏移电压的值的各种开关位置。

3. 发明授权

US5287106A Circuit for PCM conversion of an analog signal, with improvement in gain-tracking 失效
标题翻译：模拟信号的PCM转换电路，具有增益跟踪的改进
公开(公告)号：US5287106A
公开(公告)日：1994-02-15
申请号：US187507
申请日：1988-04-28
申请人： Daniel Senderowicz , Germano Nicollini , Carlo Crippa , Pierangelo Confalonieri
发明人： Daniel Senderowicz , Germano Nicollini , Carlo Crippa , Pierangelo Confalonieri
IPC分类号： H03M1/12 , H03M1/00 , H03M1/08 , H03M3/02 , H03M1/06 , H03M3/04
CPC分类号： H03M1/0604 , H03M1/12
摘要： The circuit includes a filter to which an analog signal is applied, a quantizer driven by the filter, a sampler at a desired frequency driven by the quantizer and a PCM encoder driven by the sampler. The quantizer generates a quantize signal according to the received analog signal and further generates a difference signal according to the difference between a quantized signal and the analog signal. A feedback circuit feeds back the difference signal from the quantizer to a stage of the filter so that the overall transfer function from the input of the feedback circuit to the output of the filter is equivalent to a low pass filtering.
摘要翻译：电路包括施加模拟信号的滤波器，由滤波器驱动的量化器，由量化器驱动的期望频率的采样器和由采样器驱动的PCM编码器。量化器根据接收到的模拟信号生成量化信号，并根据量化信号和模拟信号之间的差产生差分信号。反馈电路将差分信号从量化器反馈到滤波器的级，使得从反馈电路的输入到滤波器的输出的整体传递函数等效于低通滤波。

4. 发明授权

US4609877A Buffer circuit with differential structure for measurement of capacitive charges 失效
标题翻译：具有差分结构的缓冲电路，用于测量电容性电荷
公开(公告)号：US4609877A
公开(公告)日：1986-09-02
申请号：US795834
申请日：1985-11-07
申请人： Germano Nicollini , Daniel Senderowicz , Pierangelo Confalonieri
发明人： Germano Nicollini , Daniel Senderowicz , Pierangelo Confalonieri
IPC分类号： H03F3/72 , G01R29/24 , H03F3/70 , H03F3/45
CPC分类号： G01R29/24
摘要： In a buffer with an operational amplifier having two inputs and two outputs and two feedback capacitances are inserted two other capacitances which in the measurement stage are switched in parallel to the feedback ones with opposite sign in such a manner as to cancel out the effects on the output voltage signal.
摘要翻译：在具有两个输入和两个输出的运算放大器和两个反馈电容的缓冲器中插入两个其他电容，其中测量级与具有相反符号的反馈开关平行地切换，以抵消对输出电压信号。

5. 发明授权

US08692612B2 Electronic device for regulating a variable capacitance of an integrated circuit 有权
标题翻译：用于调节集成电路的可变电容的电子装置
公开(公告)号：US08692612B2
公开(公告)日：2014-04-08
申请号：US12891409
申请日：2010-09-27
申请人： Pierangelo Confalonieri , Federico Guanziroli , Germano Nicollini
发明人： Pierangelo Confalonieri , Federico Guanziroli , Germano Nicollini
IPC分类号： H03B1/00 , H03K5/00 , H04B1/10
CPC分类号： H03H5/12
摘要： The present disclosure relates to an electronic regulation device of a variable capacitance of an integrated circuit having a time parameter depending on the variable capacitance. The regulation device includes a regulation loop, and is configured to generate in output a plurality of binary regulation signals.
摘要翻译：本公开涉及具有取决于可变电容的时间参数的集成电路的可变电容的电子调节装置。调节装置包括调节回路，并且被配置为在输出中产生多个二进制调节信号。

6. 发明授权

US07675449B2 Current steering digital-analog converter particularly insensitive to packaging stresses 有权
标题翻译：电流转向数模转换器特别对包装应力不敏感
公开(公告)号：US07675449B2
公开(公告)日：2010-03-09
申请号：US12172692
申请日：2008-07-14
申请人： Pierangelo Confalonieri , Marco Zamprogno , Riccardo Martignone
发明人： Pierangelo Confalonieri , Marco Zamprogno , Riccardo Martignone
IPC分类号： H03M1/66
CPC分类号： H03M1/0648 , H03M1/687 , H03M1/747
摘要： A current steering digital-analog converter for converting a digital code into an analog signal, the converter including a substrate of semiconductor material, an array of current generators integrated in the substrate, a common summation node and switches controllable on the basis of the digital code for connecting and disconnecting the current generators to and from the common summation node. The current generators are adapted to provide the common summation node with currents having a multiple value according to a power of two compared to a unit current value provided to the summation node by a current generator of the array of generators. The current generator is divided into a base number of modular current generation elements in parallel to one another at least equal to two.
摘要翻译：一种用于将数字代码转换为模拟信号的电流转向数模转换器，所述转换器包括半导体材料的衬底，集成在衬底中的电流发生器的阵列，公共求和节点和基于数字代码可控的开关用于将当前发生器连接到和从公共求和节点断开连接。电流发生器适于根据与发电机阵列的电流发生器提供给求和节点的单位电流值相比的功率，为公共求和节点提供具有多个值的电流。电流发生器被分成基本数量的模块化电流产生元件，彼此平行至少等于2。

7. 发明申请

US20050195010A1 Time-delay circuit 有权
标题翻译：延时电路
公开(公告)号：US20050195010A1
公开(公告)日：2005-09-08
申请号：US11055564
申请日：2005-02-09
申请人： Pierangelo Confalonieri , Marco Zamprogno , Federico Garibaldi
发明人： Pierangelo Confalonieri , Marco Zamprogno , Federico Garibaldi
IPC分类号： H03B1/00 , H03H11/26 , H03K5/00 , H03K5/04 , H03K5/13
CPC分类号： H03H11/26 , H03K5/04 , H03K5/133 , H03K2005/00071 , H03K2005/00123 , H03K2005/00143 , H03K2005/00156 , H03K2005/00195
摘要： A time delay logic comprises a first stage with an inverter, a capacitor connected to the input terminal of the inverter, a constant current generator and an electronic switch controlled by an input pulse. The capacitor begins to charge at a predetermined edge of the input pulse and brings the input terminal of the inverter from a first voltage (ground) to the switching threshold voltage of the inverter, so that on the output terminal of the inverter there is obtained a pulse having an edge that, as referred to the predetermined edge of the input pulse, has a delay time that depends on the inverter threshold. The circuit comprises a second stage, coupled with the first, that is a dual circuit of the circuit of the first stage and has an inverter equal to the one of the first stage.
摘要翻译：时间延迟逻辑包括具有逆变器的第一级，连接到逆变器的输入端的电容器，恒定电流发生器和由输入脉冲控制的电子开关。电容器开始在输入脉冲的预定边沿充电，并将逆变器的输入端从第一电压（接地）转换到逆变器的开关阈值电压，从而在逆变器的输出端上获得具有如参照输入脉冲的预定边缘具有取决于反相器阈值的延迟时间的边缘的脉冲。电路包括与第一级耦合的第二级，即第一级的电路的双电路，并且具有等于第一级中的一级的反相器。

8. 发明授权

US06897801B2 High-speed, high-resolution and low-consumption analog/digital converter with single-ended input 有权
标题翻译：具有单端输入的高速，高分辨率和低功耗模拟/数字转换器
公开(公告)号：US06897801B2
公开(公告)日：2005-05-24
申请号：US10483790
申请日：2002-06-13
申请人： Pierangelo Confalonieri , Marco Zamprogno , Angelo Nagari
发明人： Pierangelo Confalonieri , Marco Zamprogno , Angelo Nagari
IPC分类号： H03M1/06 , H03M1/46 , H03M1/80 , H03M1/12 , G06F7/64 , G06G7/18 , G06G7/19
CPC分类号： H03M1/0682 , H03M1/468 , H03M1/804
摘要： An A/D converter having capacitors of a first array of sampling capacitors weighted in binary code connected between a first common circuit node and an input terminal to be charged to an input voltage with respect to a ground of a signal to be converted, and in accordance with SAR technique are then selectively connected with two differential reference terminals, and at the same time capacitors of a second array equal to the first and all connected to a second node are selectively connected to ground and the lower differential voltage terminal. The two nodes are connected to the respective inputs of a comparator. A logic unit controls the connections of the capacitors of the two arrays in accordance with a predetermined timing program and as a function of the output of the comparator.
摘要翻译：一种A / D转换器，具有电容器，其具有以二进制代码加权的采样电容器的第一阵列阵列，连接在第一公共电路节点和待充电的输入端子之间，所述第一公共电路节点和输入端子相对于要转换的信号的接地为输入电压，然后根据SAR技术选择性地与两个差分参考端子连接，并且同时等效于第一和所有连接到第二节点的第二阵列的电容器选择性地连接到地和下差分电压端子。两个节点连接到比较器的相应输入端。逻辑单元根据预定的定时程序和作为比较器的输出的函数来控制两个阵列的电容器的连接。

9. 发明授权

US5763907A Library of standard cells for the design of integrated circuits 失效
标题翻译：集成电路设计标准单元库
公开(公告)号：US5763907A
公开(公告)日：1998-06-09
申请号：US763937
申请日：1996-12-12
申请人： Carlo Dallavalle , Pierangelo Confalonieri
发明人： Carlo Dallavalle , Pierangelo Confalonieri
IPC分类号： H01L27/02 , H01L27/10
CPC分类号： H01L27/0207
摘要： A cell library for the design of integrated circuits, for example using CMOS technology, includes cells which define circuit modules in rectangular areas having an identical side. Two traces are provided which extend at right-angles to the identical side and which define strips for connection to the supply, at least one of which is in contact with the source regions of MOS transistors of a CMOS pair. In order to permit the design of integrated circuits in which the analog parts are insensitive to the noise induced in the substrate by the digital parts and in which it is possible to reduce the current absorption of the digital parts in stand-by mode, the cell library also provides a group of cells in which there is provided at least one additional trace which defines an additional strip for connection to the outside and which is in contact with the body regions of the MOS transistors of the CMOS pair.
摘要翻译：用于设计集成电路的单元库，例如使用CMOS技术，包括在具有相同侧面的矩形区域中定义电路模块的单元。提供了两条迹线，它们以直角延伸到同一侧，并且限定了用于连接到电源的条，其中至少一条与CMOS对的MOS晶体管的源极区域接触。为了允许模拟部件对由数字部件在基板中感应的噪声不敏感的集成电路的设计，并且其中可以减少待机模式下的数字部件的电流吸收，电池库还提供了一组单元，其中提供至少一个额外的迹线，其限定用于连接到外部并与CMOS对的MOS晶体管的体区接触的附加条。

10. 发明授权

US4883993A Antibounce circuit for digital circuits 失效
标题翻译：数字电路防反弹电路
公开(公告)号：US4883993A
公开(公告)日：1989-11-28
申请号：US279036
申请日：1988-12-02
申请人： Pierangelo Confalonieri , Sergio Pernici , Germano Nicollini
发明人： Pierangelo Confalonieri , Sergio Pernici , Germano Nicollini
IPC分类号： H03K5/1252
CPC分类号： H03K5/1252
摘要： The antibounce circuit comprises:(a) a first flip-flop constituted by a first and a second NAND gate (10, 12) having their respective outputs connected to one of the inputs of the other gate, the free input of the first gate being the input for said digital signal;(b) a second flip-flop constituted by a third and fourth NAND gate (14, 16) having their respective outputs connected to one of the inputs of the other gate, the free input of the third gate being connected to the output of the first gate;(c) a non-inverting delay circuit (20, 22, 24) connecting the output of the third gate to the free input of the second gate;(d) a first inverter connecting the output of the delay circuit to the free input of the fourth gate.

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