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1. 发明授权

US5500946A Integrated dual bus controller 失效
标题翻译：集成双总线控制器
公开(公告)号：US5500946A
公开(公告)日：1996-03-19
申请号：US380453
申请日：1995-01-27
申请人： Philip Roden , Khodor Elnashar , Brian T. Deng , Steve Tsang , William Saperstein
发明人： Philip Roden , Khodor Elnashar , Brian T. Deng , Steve Tsang , William Saperstein
IPC分类号： G06F13/36 , G06F13/14
CPC分类号： G06F13/36
摘要： A dual bus controller includes a system bus control module connected to a local bus control module. An optional filter is also connected to the system bus control module. A plurality of programmable status registers for the local bus is connected to the local bus control module and a time dependent reset circuit is connected to both the system bus control module and the local bus control module. The dual bus controller allows simultaneous, autonomous activity with both the local bus and the system bus via the local bus and system bus control modules. The unique interaction between the local bus and system bus control modules also allow both the local bus and system bus to interact with the dual bus controller operating as a slave without any imposed speed limitations by actively resolving bus collisions and "live-lock" conditions.
摘要翻译：双总线控制器包括连接到本地总线控制模块的系统总线控制模块。可选的过滤器也连接到系统总线控制模块。用于本地总线的多个可编程状态寄存器连接到本地总线控制模块，并且时间相关复位电路连接到系统总线控制模块和本地总线控制模块。双总线控制器允许通过本地总线和系统总线控制模块与本地总线和系统总线同时进行自主活动。本地总线和系统总线控制模块之间的独特交互还允许本地总线和系统总线与作为从站操作的双总线控制器进行交互，而不会通过主动解决总线冲突和“实时锁定”条件而施加速度限制。

2. 发明授权

US5497466A Universal address generator 失效
标题翻译：通用地址生成器
公开(公告)号：US5497466A
公开(公告)日：1996-03-05
申请号：US210093
申请日：1994-03-17
申请人： Philip Roden , Brian T. Deng , William Saperstein
发明人： Philip Roden , Brian T. Deng , William Saperstein
IPC分类号： G06F13/28 , G06F13/42 , G06F13/00 , G06F12/00
CPC分类号： G06F13/28 , G06F13/4226
摘要： A bus interface system includes a processor unit 10 a local bus 11 coupled to the processor unit and interface circuitry 12 coupled to the local bus 11 for providing continuous generation of addresses on the local bus 11 or on a system bus 15. The local bus 11 may be a processor bus on a computer board while the system bus 15 may be an architectural bus standard such as Futurebus+. The interface circuitry 12 includes a universal address generator 14 that provides proper address generation on both system bus 15 and local bus 11. Also a method of generating addresses includes loading an address into an address register, saving the address if it is the first address, outputting the address to a local or system bus, incrementing the address, and repeating sequence at the loading step.
摘要翻译：总线接口系统包括处理器单元10，耦合到处理器单元的本地总线11和耦合到本地总线11的接口电路12，用于在本地总线11上或系统总线15上提供连续的地址生成。本地总线11 可以是计算机板上的处理器总线，而系统总线15可以是诸如Futurebus +的架构总线标准。接口电路12包括通用地址发生器14，其在系统总线15和本地总线11上提供适当的地址生成。另外，产生地址的方法包括将地址加载到地址寄存器中，如果地址是第一地址，则保存地址，将地址输出到本地或系统总线，递增地址，并在加载步骤重复序列。

3. 发明授权

US06584536B1 Bus transaction accelerator for multi-clock systems 有权
标题翻译：用于多时钟系统的总线事务加速器
公开(公告)号：US06584536B1
公开(公告)日：2003-06-24
申请号：US09414693
申请日：1999-10-07
申请人： Brian T. Deng
发明人： Brian T. Deng
IPC分类号： G06F1314
CPC分类号： H04L7/0012 , H04L7/02
摘要： A bus transaction accelerator, incorporating an innovative control register and status register circuit. The innovative accelerator allows systems with different clocks to handshake in the background, thereby reducing bus idle time.
摘要翻译：总线事务加速器，包含创新的控制寄存器和状态寄存器电路。创新的加速器允许具有不同时钟的系统在后台握手，从而减少总线空闲时间。

4. 发明授权

US06499080B1 Post write buffer for a dual clock system 有权
标题翻译：用于双时钟系统的后写入缓冲器
公开(公告)号：US06499080B1
公开(公告)日：2002-12-24
申请号：US09478846
申请日：2000-01-07
申请人： Brian T. Deng
发明人： Brian T. Deng
IPC分类号： G06F1336
CPC分类号： G06F13/4059 , G06F13/4213
摘要： A post write buffer for a dual clock system which improves the utilization of host data bus (10) bandwidth is provided which consists of an address buffer (60), a data buffer (62), a first clock timing signal (22), a second clock timing signal (48), an address decoder (24), a first write enable circuit (72), and a second write enable circuit (74). The address-buffer (60) and data buffer (62). hold the data and the destination address for that data until the clock signals are synchronized and the data is ready for transfer. The address decoder (24) determines which destination register byte will receive the data in the host data bus (10). The write enable circuits (72, 74) synchronize the clock signals (22, 48) and determine when the destination register is ready to receive the data from the data buffer (62).
摘要翻译：提供了一种提高主机数据总线（10）带宽利用率的双时钟系统的后置写缓冲器，其包括地址缓冲器（60），数据缓冲器（62），第一时钟定时信号（22），第二时钟定时信号（48），地址解码器（24），第一写入使能电路（72）和第二写入使能电路（74）。地址缓冲器（60）和数据缓冲器（62）。保持该数据的数据和目标地址，直到时钟信号同步并且数据准备好传输。地址解码器（24）确定哪个目的地寄存器字节将在主机数据总线（10）中接收数据。写入使能电路（72,74）使时钟信号（22,48）同步，并且确定目的地寄存器何时准备好从数据缓冲器（62）接收数据。

5. 发明授权

US6157972A Apparatus and method for processing packetized information over a serial bus 有权
标题翻译：通过串行总线处理分组化信息的装置和方法
公开(公告)号：US6157972A
公开(公告)日：2000-12-05
申请号：US196903
申请日：1998-11-20
申请人： Merril Newman , Brian T. Deng , David E. Kimble
发明人： Merril Newman , Brian T. Deng , David E. Kimble
IPC分类号： H04L12/40 , H04L12/64 , G06F13/00
CPC分类号： H04L12/40071 , H04L12/6418 , Y10S370/912
摘要： An IEEE 1394 serial bus, during bus initialization, transmits a plurality of self-ID packets across the bus. Each node on the bus is operable to receive the self-ID packet from the bus (140) via receiver (146). Asynchronous packets and isochronous packets are stored in a FIFO (166) for later use by a host interface (150). The self-ID packets are verified by a hardware circuit (170) that provides verification of the self-ID packets as they are received without requiring the software to later evaluate the self-ID packets from storage in the FIFO (166). If an error is determined, this is stored in registers (164) for later processing by the host interface (150).
摘要翻译：在总线初始化期间，IEEE 1394串行总线通过总线发送多个自身ID分组。总线上的每个节点可操作以经由接收器（146）从总线（140）接收自身ID分组。异步分组和同步分组被存储在FIFO（166）中以备以后由主机接口（150）使用。所述自身ID分组由硬件电路（170）进行验证，所述硬件电路（170）在接收到所述自身ID分组时进行验证，而不需要所述软件稍后从所述FIFO（166）中的存储中评估所述自身ID分组。如果确定了错误，则将其存储在寄存器（164）中以供主机接口（150）稍后处理。

6. 发明授权

US5619544A Universal asynchronous receive/transmit circuit with flow control 失效
标题翻译：具有流量控制的通用异步接收/发送电路
公开(公告)号：US5619544A
公开(公告)日：1997-04-08
申请号：US607840
申请日：1996-02-27
申请人： Clarence D. Lewis , Mahmoud M. Yazdani , Dinghui Nie , Brian T. Deng , Matthew J. DiMarco
发明人： Clarence D. Lewis , Mahmoud M. Yazdani , Dinghui Nie , Brian T. Deng , Matthew J. DiMarco
IPC分类号： G06F13/38 , H04L12/56 , H04B1/38 , H04L7/00
CPC分类号： H04L47/10 , G06F13/385
摘要： A method and apparatus for a circuit physically realizing a Universal Asynchronous Receive/Transmit (UART) circuit 31, 40 having an automatic flow control feature. A preferred embodiment includes a UART 31 provided with additional control circuitry 39, 34 for automatically pausing transfers from the transmit data circuitry 35, 32 in response to a transition at the CTS (Clear to Send) input, and further provided with control circuitry 39 for automatically asserting and deasserting a RTS (Ready to Send) output when a receiver data threshold is reached.
摘要翻译：一种用于物理实现具有自动流量控制特征的通用异步接收/发送（UART）电路31,40的电路的方法和装置。优选实施例包括具有附加控制电路39,34的UART 31，用于响应于CTS（清除发送）输入的转变而自动暂停来自发送数据电路35,32的传输，并且还提供控制电路39，用于当达到接收机数据阈值时，自动断言和解除RTS（Ready to Send）输出。

7. 发明授权

US06377650B1 Counter register monitor and update circuit for dual-clock system 有权
标题翻译：双时钟系统的计数器寄存器监视和更新电路
公开(公告)号：US06377650B1
公开(公告)日：2002-04-23
申请号：US09638830
申请日：2000-08-14
申请人： Brian T. Deng , Michael D. McKinney
发明人： Brian T. Deng , Michael D. McKinney
IPC分类号： H03K2300
CPC分类号： G06F13/387
摘要： An improved counter register (30) and method of transferring data from a host data bus (29) controlled by a first clock source (BCLK) to the cycle timer (18) controlled by a second clock source (NCLK) which frees the host data bus (29) to perform other functions while a clock synchronization process occurs to allow the data (24) to be written to the counter register (30) or read from the counter register (30). This synchronization scheme is such that at any time the host data bus (29) may read data (25) from the cycle timer (18) and retrieve the current counter register value. In the alternative, at any time, the host data bus (29) may write to the cycle timer (18) and it will receive this data (24) immediately. In either case, the data is transferred immediately without the host data bus (29) having to wait for synchronization across the aforementioned clock boundary.
摘要翻译：一种改进的计数器寄存器（30）以及从第一时钟源（BCLK）控制的主机数据总线（29）将数据传送到由第二时钟源（NCLK）控制的周期定时器（18）的方法，该第二时钟源（NCLK）释放主机数据总线（29）在执行时钟同步处理时执行其他功能，以允许将数据（24）写入计数器寄存器（30）或从计数器寄存器（30）读取。该同步方案使得在任何时候，主机数据总线（29）可以从周期定时器（18）读取数据（25）并且检索当前的计数器寄存器值。或者，在任何时候，主机数据总线（29）可以写入周期定时器（18），并且它将立即接收该数据（24）。在任一种情况下，立即传送数据，而不需要在上述时钟边界上等待同步的主机数据总线（29）。

8. 发明授权

US06347097B1 Method and apparatus for buffering received data from a serial bus 有权
标题翻译：用于从串行总线缓冲接收数据的方法和装置
公开(公告)号：US06347097B1
公开(公告)日：2002-02-12
申请号：US09205892
申请日：1998-12-04
申请人： Brian T. Deng
发明人： Brian T. Deng
IPC分类号： H04J300
CPC分类号： H04L12/40071 , H04L12/40013 , H04L12/40091
摘要： A method for reading data from an IEEE 1394 serial bus system and storing the data in a FIFO includes partitioning the FIFO into a plurality of registers, each having 32 register bits for the data and a single register bit for a control data bit. To manipulate the system such that reads on a data quadlet involve only one system read on a 32-bit system, a packet token is stored in the initial register in a data packet. This packet token includes the quadlet count in the data packet. The host system need only read the first register in the data packet, the packet token, to determine the number of data quadlets within the data packet. Thereafter, the control data bit need not be read such that only a single read operation is performed for each operation of the read pointer. The last register associated with the packet is the acknowledge register which contains information that is sent back to the transmit node in the system. Further, each data packet can be divided into partitions with a plurality of packet tokens. Each packet token has a defined quadlet count associated therewith, the packet tokens disposed at the beginning of each partition. The last partition has a Complete bit set equal to “1” to define that as a the last partition. In this last packet token, the acknowledge signal is stored.
摘要翻译：用于从IEEE 1394串行总线系统读取数据并将数据存储在FIFO中的方法包括将FIFO划分成多个寄存器，每个寄存器具有用于数据的32个寄存器位和用于控制数据位的单个寄存器位。为了操纵系统，使得数据quadlet上的读取仅涉及在32位系统上读取的一个系统，则数据包令牌被存储在数据包中的初始寄存器中。该分组令牌包括数据分组中的四字节计数。主机系统只需要读取数据包中的第一个寄存器，即数据包令牌，以确定数据包内的数据quadlet的数量。此后，不需要读取控制数据位，使得仅对读指针的每个操作执行单个读操作。与分组相关联的最后一个寄存器是确认寄存器，其包含发回到系统中的发送节点的信息。此外，每个数据分组可以被划分成具有多个分组令牌的分区。每个分组令牌具有与之相关联的定义的四元组计数，每个分区的开始处设置分组令牌。最后一个分区具有等于“1”的完整位，将其定义为最后一个分区。在最后一个包令牌中，存储确认信号。

9. 发明授权

US5647057A Multiple block transfer mechanism 失效
标题翻译：多块传输机制
公开(公告)号：US5647057A
公开(公告)日：1997-07-08
申请号：US303549
申请日：1994-09-09
申请人： Philip A. Roden , Brian T. Deng
发明人： Philip A. Roden , Brian T. Deng
IPC分类号： G06F13/28 , G06F13/38
CPC分类号： G06F13/28
摘要： A block data transfer system may comprise a microprocessor integrated within a bus controller, a bus, and a plurality of computer boards coupled together via the bus. A PAL (programmable array logic device), integrated within the bus controller, allows an efficient block transfer of data between components on the computer boards by asserting a binary signal to indicate to the bus controller when to continue the data transfer and when to truncate the data transfer. The PAL utilizes a counter, dependent upon the data transfer size, to control the binary indication signal. The binary signal overrides the architectural data transfer protocol, thereby eliminating "protocol overhead" timing associated in multiple data transfers by allowing the entire data block to transfer within one transfer protocol period.
摘要翻译：块数据传输系统可以包括集成在总线控制器，总线和经由总线耦合在一起的多个计算机板的微处理器。集成在总线控制器中的PAL（可编程阵列逻辑器件）允许在计算机主板上的组件之间有效地传输数据，通过断言二进制信号向总线控制器指示何时继续数据传输，何时截断数据传输。 PAL利用依赖于数据传输大小的计数器来控制二进制指示信号。二进制信号覆盖架构数据传输协议，从而通过允许整个数据块在一个传输协议周期内传输来消除与多个数据传输相关的“协议开销”定时。

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