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1. 发明授权

US5500946A Integrated dual bus controller 失效
标题翻译：集成双总线控制器
公开(公告)号：US5500946A
公开(公告)日：1996-03-19
申请号：US380453
申请日：1995-01-27
申请人： Philip Roden , Khodor Elnashar , Brian T. Deng , Steve Tsang , William Saperstein
发明人： Philip Roden , Khodor Elnashar , Brian T. Deng , Steve Tsang , William Saperstein
IPC分类号： G06F13/36 , G06F13/14
CPC分类号： G06F13/36
摘要： A dual bus controller includes a system bus control module connected to a local bus control module. An optional filter is also connected to the system bus control module. A plurality of programmable status registers for the local bus is connected to the local bus control module and a time dependent reset circuit is connected to both the system bus control module and the local bus control module. The dual bus controller allows simultaneous, autonomous activity with both the local bus and the system bus via the local bus and system bus control modules. The unique interaction between the local bus and system bus control modules also allow both the local bus and system bus to interact with the dual bus controller operating as a slave without any imposed speed limitations by actively resolving bus collisions and "live-lock" conditions.
摘要翻译：双总线控制器包括连接到本地总线控制模块的系统总线控制模块。可选的过滤器也连接到系统总线控制模块。用于本地总线的多个可编程状态寄存器连接到本地总线控制模块，并且时间相关复位电路连接到系统总线控制模块和本地总线控制模块。双总线控制器允许通过本地总线和系统总线控制模块与本地总线和系统总线同时进行自主活动。本地总线和系统总线控制模块之间的独特交互还允许本地总线和系统总线与作为从站操作的双总线控制器进行交互，而不会通过主动解决总线冲突和“实时锁定”条件而施加速度限制。

2. 发明授权

US5497466A Universal address generator 失效
标题翻译：通用地址生成器
公开(公告)号：US5497466A
公开(公告)日：1996-03-05
申请号：US210093
申请日：1994-03-17
申请人： Philip Roden , Brian T. Deng , William Saperstein
发明人： Philip Roden , Brian T. Deng , William Saperstein
IPC分类号： G06F13/28 , G06F13/42 , G06F13/00 , G06F12/00
CPC分类号： G06F13/28 , G06F13/4226
摘要： A bus interface system includes a processor unit 10 a local bus 11 coupled to the processor unit and interface circuitry 12 coupled to the local bus 11 for providing continuous generation of addresses on the local bus 11 or on a system bus 15. The local bus 11 may be a processor bus on a computer board while the system bus 15 may be an architectural bus standard such as Futurebus+. The interface circuitry 12 includes a universal address generator 14 that provides proper address generation on both system bus 15 and local bus 11. Also a method of generating addresses includes loading an address into an address register, saving the address if it is the first address, outputting the address to a local or system bus, incrementing the address, and repeating sequence at the loading step.
摘要翻译：总线接口系统包括处理器单元10，耦合到处理器单元的本地总线11和耦合到本地总线11的接口电路12，用于在本地总线11上或系统总线15上提供连续的地址生成。本地总线11 可以是计算机板上的处理器总线，而系统总线15可以是诸如Futurebus +的架构总线标准。接口电路12包括通用地址发生器14，其在系统总线15和本地总线11上提供适当的地址生成。另外，产生地址的方法包括将地址加载到地址寄存器中，如果地址是第一地址，则保存地址，将地址输出到本地或系统总线，递增地址，并在加载步骤重复序列。

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