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1. 发明授权

US06878999B2 Transistor with improved safe operating area 有权
标题翻译：晶体管具有改进的安全操作区域
公开(公告)号：US06878999B2
公开(公告)日：2005-04-12
申请号：US10619699
申请日：2003-07-15
申请人： Philip L. Hower , John Lin , Sameer Pendharkar , Steven L. Jensen
发明人： Philip L. Hower , John Lin , Sameer Pendharkar , Steven L. Jensen
IPC分类号： H01L23/482 , H01L29/06 , H01L29/417 , H01L29/45 , H01L29/49 , H01L29/73 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7816 , H01L23/4824 , H01L24/05 , H01L24/06 , H01L29/0692 , H01L29/0696 , H01L29/41758 , H01L29/456 , H01L29/4933 , H01L29/73 , H01L29/7824 , H01L2224/04042 , H01L2224/05553 , H01L2224/48463 , H01L2224/4911 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/00
摘要： Segmented transistor devices are provided, wherein contiguous individual transistor segments extend along corresponding segment axes, in which two or more of the segment axes are at a non-zero angle with respect to one another. The segmentation of the transistor provides a high overall device aspect ratio which may be easily fit into pre-existing circuit blocks or cells in a device layout, thereby facilitating device scaling.
摘要翻译：提供了分段晶体管器件，其中相邻的单独晶体管段沿着相应的分段轴线延伸，其中两个或多个分段轴线相对于彼此处于非零角度。晶体管的分割提供了高的整体器件纵横比，其可以容易地装配到器件布局中的预先存在的电路块或单元中，从而有助于器件缩放。

2. 发明授权

US08872273B2 Integrated gate controlled high voltage divider 有权
标题翻译：集成门控高压分压器
公开(公告)号：US08872273B2
公开(公告)日：2014-10-28
申请号：US13567340
申请日：2012-08-06
申请人： Hideaki Kawahara , Marie Denison , Sameer Pendharkar , Philip L. Hower , John Lin , Robert A. Neidorff
发明人： Hideaki Kawahara , Marie Denison , Sameer Pendharkar , Philip L. Hower , John Lin , Robert A. Neidorff
IPC分类号： H01L27/11 , H01L27/06 , H01L49/02
CPC分类号： H01L28/20 , H01L27/0629
摘要： An integrated circuit containing a gate controlled voltage divider having an upper resistor on field oxide in series with a transistor switch in series with a lower resistor. A resistor drift layer is disposed under the upper resistor, and the transistor switch includes a switch drift layer adjacent to the resistor drift layer, separated by a region which prevents breakdown between the drift layers. The switch drift layer provides an extended drain or collector for the transistor switch. A sense terminal of the voltage divider is coupled to a source or emitter node of the transistor and to the lower resistor. An input terminal is coupled to the upper resistor and the resistor drift layer. A process of forming the integrated circuit containing the gate controlled voltage divider.
摘要翻译：一种集成电路，其包含栅极控制分压器，该栅极控制分压器具有与场效应晶体管上的上电阻串联的晶体管开关，与下电阻串联。电阻器漂移层设置在上电阻器下方，并且晶体管开关包括与电阻器漂移层相邻的开关漂移层，由防止漂移层之间的击穿的区域分开。开关漂移层为晶体管开关提供了扩展的漏极或集电极。分压器的感测端子耦合到晶体管的源极或发射极节点和下电阻器。输入端子耦合到上电阻器和电阻漂移层。形成包含栅极控制分压器的集成电路的工艺。

3. 发明申请

US20100264486A1 FIELD PLATE TRENCH MOSFET TRANSISTOR WITH GRADED DIELECTRIC LINER THICKNESS 审中-公开
标题翻译：具有分级电介质衬里厚度的现场板式TRENCH MOSFET晶体管
公开(公告)号：US20100264486A1
公开(公告)日：2010-10-21
申请号：US12426717
申请日：2009-04-20
申请人： Marie Denison , Sameer Pendharkar , Philip L. Hower , John Lin
发明人： Marie Denison , Sameer Pendharkar , Philip L. Hower , John Lin
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/66719 , H01L29/66734
摘要： An electronic device has a plurality of trenches formed in a semiconducting layer. A vertical drift region is located between and adjacent the trenches. An electrode is located within each trench, the electrode having a gate electrode section and a field plate section. A graded field plate dielectric is located between the field plate section and the vertical drift region.
摘要翻译：电子器件具有形成在半导体层中的多个沟槽。垂直漂移区域位于沟槽之间和相邻的沟槽之间。电极位于每个沟槽内，电极具有栅电极部分和场板部分。梯度场板电介质位于场板部分和垂直漂移区之间。

4. 发明授权

US08853029B2 Method of making vertical transistor with graded field plate dielectric 有权
标题翻译：制造具有梯度场板电介质的垂直晶体管的方法
公开(公告)号：US08853029B2
公开(公告)日：2014-10-07
申请号：US13188162
申请日：2011-07-21
申请人： Marie Denison , Sameer Pendharkar , Philip L. Hower , John Lin
发明人： Marie Denison , Sameer Pendharkar , Philip L. Hower , John Lin
IPC分类号： H01L21/336 , H01L29/66 , H01L29/78 , H01L29/423
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/66719 , H01L29/66734
摘要： An electronic device has a plurality of trenches formed in a semiconductor layer. A vertical drift region is located between and adjacent the trenches. An electrode is located within each trench, the electrode having a gate electrode section and a field plate section. A graded field plate dielectric having increased thickness at greater depth is located between the field plate section and the vertical drift region.
摘要翻译：电子器件具有形成在半导体层中的多个沟槽。垂直漂移区域位于沟槽之间和相邻的沟槽之间。电极位于每个沟槽内，电极具有栅电极部分和场板部分。在场板部分和垂直漂移区域之间设置具有较大深度的厚度增加的分级场板电介质。

5. 发明申请

US20130032922A1 INTEGRATED HIGH VOLTAGE DIVIDER 有权
标题翻译：集成高压分压器
公开(公告)号：US20130032922A1
公开(公告)日：2013-02-07
申请号：US13567456
申请日：2012-08-06
申请人： Hideaki Kawahara , Marie Denison , Sameer Pendharkar , Philip L. Hower , John Lin , Robert A. Neidorff
发明人： Hideaki Kawahara , Marie Denison , Sameer Pendharkar , Philip L. Hower , John Lin , Robert A. Neidorff
IPC分类号： H01L29/06 , H01L21/761
CPC分类号： H01L21/761 , H01L21/266
摘要： An integrated circuit containing a voltage divider having an upper resistor of unsilicided gate material over field oxide around a central opening and a drift layer under the upper resistor, an input terminal coupled to an input node of the upper resistor adjacent to the central opening in the field oxide and coupled to the drift layer through the central opening, a sense terminal coupled to a sense node on the upper resistor opposite from the input node, a lower resistor with a sense node coupled to the sense terminal and a reference node, and a reference terminal coupled to the reference node. A process of forming the integrated circuit containing the voltage divider.
摘要翻译：一种集成电路，包括分压器，该分压器具有围绕中心开口的场氧化物上的非硅栅极材料的上电阻器，以及位于上电阻器下的漂移层的输入端子，所述输入端子与所述上电阻器的输入节点相邻，场氧化物并通过中心开口耦合到漂移层，感测端子耦合到与输入节点相反的上电阻上的感测节点，具有耦合到感测端子的检测节点和参考节点的下电阻器，以及参考终端耦合到参考节点。形成包含分压器的集成电路的工艺。

6. 发明申请

US20130032863A1 INTEGRATED GATE CONTROLLED HIGH VOLTAGE DIVIDER 有权
标题翻译：集成门控高压分压器
公开(公告)号：US20130032863A1
公开(公告)日：2013-02-07
申请号：US13567340
申请日：2012-08-06
申请人： Hideaki Kawahara , Marie Denison , Sameer Pendharkar , Philip L. Hower , John Lin , Robert A. Neidorff
发明人： Hideaki Kawahara , Marie Denison , Sameer Pendharkar , Philip L. Hower , John Lin , Robert A. Neidorff
IPC分类号： H01L27/07 , H01L21/20
CPC分类号： H01L28/20 , H01L27/0629
摘要： An integrated circuit containing a gate controlled voltage divider having an upper resistor on field oxide in series with a transistor switch in series with a lower resistor. A resistor drift layer is disposed under the upper resistor, and the transistor switch includes a switch drift layer adjacent to the resistor drift layer, separated by a region which prevents breakdown between the drift layers. The switch drift layer provides an extended drain or collector for the transistor switch. A sense terminal of the voltage divider is coupled to a source or emitter node of the transistor and to the lower resistor. An input terminal is coupled to the upper resistor and the resistor drift layer. A process of forming the integrated circuit containing the gate controlled voltage divider.
摘要翻译：一种集成电路，其包含栅极控制分压器，该栅极控制分压器具有与场效应晶体管上的上电阻串联的晶体管开关，与下电阻串联。电阻器漂移层设置在上电阻器下方，并且晶体管开关包括与电阻器漂移层相邻的开关漂移层，由防止漂移层之间的击穿的区域分开。开关漂移层为晶体管开关提供了扩展的漏极或集电极。分压器的感测端子耦合到晶体管的源极或发射极节点和下电阻器。输入端子耦合到上电阻器和电阻漂移层。形成包含栅极控制分压器的集成电路的工艺。

7. 发明授权

US07195965B2 Premature breakdown in submicron device geometries 有权
标题翻译：亚微米器件几何中的过早击穿
公开(公告)号：US07195965B2
公开(公告)日：2007-03-27
申请号：US10302256
申请日：2002-11-22
申请人： John Lin , Philip L. Hower , Taylor R. Efland , Sameer Pendharkar , Vladimir Bolkhovsky
发明人： John Lin , Philip L. Hower , Taylor R. Efland , Sameer Pendharkar , Vladimir Bolkhovsky
IPC分类号： H01L21/8248
CPC分类号： H01L29/7816 , H01L21/266 , H01L29/0615 , H01L29/0692 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/4238 , H01L29/66674 , H01L29/7322 , H01L29/8611
摘要： The concept of the present invention describes a semiconductor device with a junction 504 between a lightly doped region 501 and a heavily doped region 502, wherein the junction has an elongated portion 504a and curved portions 504b. The doping concentration of the lightly doped region is configured so that it exhibits higher resistivity in the proximity 510 of the curved portion by an amount suitable to lower the electric field strength during device operation and thus to offset the increased field strength caused by the curved portion. As a consequence, the device breakdown voltage in the curved junction portion becomes equal to or greater than the breakdown voltage in the linear portion.
摘要翻译：本发明的概念描述了在轻掺杂区域501和重掺杂区域502之间具有结504的半导体器件，其中该接合部具有细长部分504a和弯曲部分504b。轻掺杂区域的掺杂浓度被配置为使得其在弯曲部分的接近510处表现出较高的电阻率，其量适于在器件操作期间降低电场强度，并因此抵消由弯曲部分引起的增加的场强。结果，弯曲接合部中的器件击穿电压变得等于或大于直线部分中的击穿电压。

8. 发明授权

US08878330B2 Integrated high voltage divider 有权
标题翻译：集成高压分压器
公开(公告)号：US08878330B2
公开(公告)日：2014-11-04
申请号：US13567456
申请日：2012-08-06
申请人： Hideaki Kawahara , Marie Denison , Sameer Pendharkar , Philip L. Hower , John Lin , Robert A. Neidorff
发明人： Hideaki Kawahara , Marie Denison , Sameer Pendharkar , Philip L. Hower , John Lin , Robert A. Neidorff
IPC分类号： H01L29/02 , H01L21/761 , H01L21/266
CPC分类号： H01L21/761 , H01L21/266
摘要： An integrated circuit containing a voltage divider having an upper resistor of unsilicided gate material over field oxide around a central opening and a drift layer under the upper resistor, an input terminal coupled to an input node of the upper resistor adjacent to the central opening in the field oxide and coupled to the drift layer through the central opening, a sense terminal coupled to a sense node on the upper resistor opposite from the input node, a lower resistor with a sense node coupled to the sense terminal and a reference node, and a reference terminal coupled to the reference node. A process of forming the integrated circuit containing the voltage divider.
摘要翻译：一种集成电路，包括分压器，该分压器具有围绕中心开口的场氧化物上的非硅栅极材料的上电阻器，以及位于上电阻器下的漂移层的输入端子，所述输入端子与所述上电阻器的输入节点相邻，场氧化物并通过中心开口耦合到漂移层，感测端子耦合到与输入节点相反的上电阻上的感测节点，具有耦合到感测端子的检测节点和参考节点的下电阻器，以及参考终端耦合到参考节点。形成包含分压器的集成电路的工艺。

9. 发明申请

US20110275210A1 METHOD OF MAKING VERTICAL TRANSISTOR WITH GRADED FIELD PLATE DIELECTRIC 有权
标题翻译：制造具有等级场板电介质的垂直晶体管的方法
公开(公告)号：US20110275210A1
公开(公告)日：2011-11-10
申请号：US13188162
申请日：2011-07-21
申请人： Marie Denison , Sameer Pendharkar , Philip L. Hower , John Lin
发明人： Marie Denison , Sameer Pendharkar , Philip L. Hower , John Lin
IPC分类号： H01L21/28
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/66719 , H01L29/66734
摘要： An electronic device has a plurality of trenches formed in a semiconductor layer. A vertical drift region is located between and adjacent the trenches. An electrode is located within each trench, the electrode having a gate electrode section and a field plate section. A graded field plate dielectric having increased thickness at greater depth is located between the field plate section and the vertical drift region.
摘要翻译：电子器件具有形成在半导体层中的多个沟槽。垂直漂移区域位于沟槽之间和相邻的沟槽之间。电极位于每个沟槽内，电极具有栅电极部分和场板部分。在场板部分和垂直漂移区域之间设置具有较大深度的厚度增加的分级场板电介质。

10. 发明申请

US20090159968A1 BVDII Enhancement with a Cascode DMOS 审中-公开
标题翻译： BVDII增强与Cascode DMOS
公开(公告)号：US20090159968A1
公开(公告)日：2009-06-25
申请号：US11960432
申请日：2007-12-19
申请人： Steve L. Merchant , John Lin , Sameer Pendharkar , Philip L. Hower
发明人： Steve L. Merchant , John Lin , Sameer Pendharkar , Philip L. Hower
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L21/823481 , H01L21/823425 , H01L21/823456 , H01L21/823462 , H01L29/0653 , H01L29/42368 , H01L29/66659 , H01L29/7833 , H01L29/7835
摘要： Double diffused MOS (DMOS) transistors feature extended drain regions to provide depletion regions which drop high drain voltages to lower voltages at the gate edges. DMOS transistors exhibit lower drain breakdown potential in the on-state than in the off-state than in the off-state due to snapback by a parasitic bipolar transistor that exists in parallel with the DMOS transistor. The instant invention is a cascoded DMOS transistor in an integrated circuit incorporating an NMOS transistor on the DMOS source node to reverse bias the parasitic emitter-base junction during on-state operation, eliminating snapback. The NMOS transistor may be integrated with the DMOS transistor by connections in the interconnect system of the integrated circuit, or the NMOS transistor and DMOS transistor may be fabricated in a common p-type well and integrated in the IC substrate. Methods of fabricating an integrated circuit with the incentive cascoded DMOS transistor are also disclosed.
摘要翻译：双扩散MOS（DMOS）晶体管具有扩展的漏极区域，以提供耗尽区域，其将高漏极电压降低到栅极边缘处的较低电压。由于与DMOS晶体管并联存在的寄生双极晶体管的回跳，DMOS晶体管在导通状态下的漏极击穿电位低于截止状态下的漏极击穿电位。本发明是在DMOS源节点上结合有NMOS晶体管的集成电路中的级联DMOS晶体管，以在接通状态操作期间反向偏置寄生发射极 - 基极结，从而消除了快速恢复。 NMOS晶体管可以通过集成电路的互连系统中的连接与DMOS晶体管集成，或者NMOS晶体管和DMOS晶体管可以制造在共同的p型阱中并集成在IC衬底中。还公开了使用激励级联DMOS晶体管制造集成电路的方法。

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