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1. 发明授权

US08878330B2 Integrated high voltage divider 有权
标题翻译：集成高压分压器
公开(公告)号：US08878330B2
公开(公告)日：2014-11-04
申请号：US13567456
申请日：2012-08-06
申请人： Hideaki Kawahara , Marie Denison , Sameer Pendharkar , Philip L. Hower , John Lin , Robert A. Neidorff
发明人： Hideaki Kawahara , Marie Denison , Sameer Pendharkar , Philip L. Hower , John Lin , Robert A. Neidorff
IPC分类号： H01L29/02 , H01L21/761 , H01L21/266
CPC分类号： H01L21/761 , H01L21/266
摘要： An integrated circuit containing a voltage divider having an upper resistor of unsilicided gate material over field oxide around a central opening and a drift layer under the upper resistor, an input terminal coupled to an input node of the upper resistor adjacent to the central opening in the field oxide and coupled to the drift layer through the central opening, a sense terminal coupled to a sense node on the upper resistor opposite from the input node, a lower resistor with a sense node coupled to the sense terminal and a reference node, and a reference terminal coupled to the reference node. A process of forming the integrated circuit containing the voltage divider.
摘要翻译：一种集成电路，包括分压器，该分压器具有围绕中心开口的场氧化物上的非硅栅极材料的上电阻器，以及位于上电阻器下的漂移层的输入端子，所述输入端子与所述上电阻器的输入节点相邻，场氧化物并通过中心开口耦合到漂移层，感测端子耦合到与输入节点相反的上电阻上的感测节点，具有耦合到感测端子的检测节点和参考节点的下电阻器，以及参考终端耦合到参考节点。形成包含分压器的集成电路的工艺。

2. 发明授权

US08872273B2 Integrated gate controlled high voltage divider 有权
标题翻译：集成门控高压分压器
公开(公告)号：US08872273B2
公开(公告)日：2014-10-28
申请号：US13567340
申请日：2012-08-06
申请人： Hideaki Kawahara , Marie Denison , Sameer Pendharkar , Philip L. Hower , John Lin , Robert A. Neidorff
发明人： Hideaki Kawahara , Marie Denison , Sameer Pendharkar , Philip L. Hower , John Lin , Robert A. Neidorff
IPC分类号： H01L27/11 , H01L27/06 , H01L49/02
CPC分类号： H01L28/20 , H01L27/0629
摘要： An integrated circuit containing a gate controlled voltage divider having an upper resistor on field oxide in series with a transistor switch in series with a lower resistor. A resistor drift layer is disposed under the upper resistor, and the transistor switch includes a switch drift layer adjacent to the resistor drift layer, separated by a region which prevents breakdown between the drift layers. The switch drift layer provides an extended drain or collector for the transistor switch. A sense terminal of the voltage divider is coupled to a source or emitter node of the transistor and to the lower resistor. An input terminal is coupled to the upper resistor and the resistor drift layer. A process of forming the integrated circuit containing the gate controlled voltage divider.
摘要翻译：一种集成电路，其包含栅极控制分压器，该栅极控制分压器具有与场效应晶体管上的上电阻串联的晶体管开关，与下电阻串联。电阻器漂移层设置在上电阻器下方，并且晶体管开关包括与电阻器漂移层相邻的开关漂移层，由防止漂移层之间的击穿的区域分开。开关漂移层为晶体管开关提供了扩展的漏极或集电极。分压器的感测端子耦合到晶体管的源极或发射极节点和下电阻器。输入端子耦合到上电阻器和电阻漂移层。形成包含栅极控制分压器的集成电路的工艺。

3. 发明申请

US20130032922A1 INTEGRATED HIGH VOLTAGE DIVIDER 有权
标题翻译：集成高压分压器
公开(公告)号：US20130032922A1
公开(公告)日：2013-02-07
申请号：US13567456
申请日：2012-08-06
申请人： Hideaki Kawahara , Marie Denison , Sameer Pendharkar , Philip L. Hower , John Lin , Robert A. Neidorff
发明人： Hideaki Kawahara , Marie Denison , Sameer Pendharkar , Philip L. Hower , John Lin , Robert A. Neidorff
IPC分类号： H01L29/06 , H01L21/761
CPC分类号： H01L21/761 , H01L21/266
摘要： An integrated circuit containing a voltage divider having an upper resistor of unsilicided gate material over field oxide around a central opening and a drift layer under the upper resistor, an input terminal coupled to an input node of the upper resistor adjacent to the central opening in the field oxide and coupled to the drift layer through the central opening, a sense terminal coupled to a sense node on the upper resistor opposite from the input node, a lower resistor with a sense node coupled to the sense terminal and a reference node, and a reference terminal coupled to the reference node. A process of forming the integrated circuit containing the voltage divider.
摘要翻译：一种集成电路，包括分压器，该分压器具有围绕中心开口的场氧化物上的非硅栅极材料的上电阻器，以及位于上电阻器下的漂移层的输入端子，所述输入端子与所述上电阻器的输入节点相邻，场氧化物并通过中心开口耦合到漂移层，感测端子耦合到与输入节点相反的上电阻上的感测节点，具有耦合到感测端子的检测节点和参考节点的下电阻器，以及参考终端耦合到参考节点。形成包含分压器的集成电路的工艺。

4. 发明申请

US20130032863A1 INTEGRATED GATE CONTROLLED HIGH VOLTAGE DIVIDER 有权
标题翻译：集成门控高压分压器
公开(公告)号：US20130032863A1
公开(公告)日：2013-02-07
申请号：US13567340
申请日：2012-08-06
申请人： Hideaki Kawahara , Marie Denison , Sameer Pendharkar , Philip L. Hower , John Lin , Robert A. Neidorff
发明人： Hideaki Kawahara , Marie Denison , Sameer Pendharkar , Philip L. Hower , John Lin , Robert A. Neidorff
IPC分类号： H01L27/07 , H01L21/20
CPC分类号： H01L28/20 , H01L27/0629
摘要： An integrated circuit containing a gate controlled voltage divider having an upper resistor on field oxide in series with a transistor switch in series with a lower resistor. A resistor drift layer is disposed under the upper resistor, and the transistor switch includes a switch drift layer adjacent to the resistor drift layer, separated by a region which prevents breakdown between the drift layers. The switch drift layer provides an extended drain or collector for the transistor switch. A sense terminal of the voltage divider is coupled to a source or emitter node of the transistor and to the lower resistor. An input terminal is coupled to the upper resistor and the resistor drift layer. A process of forming the integrated circuit containing the gate controlled voltage divider.
摘要翻译：一种集成电路，其包含栅极控制分压器，该栅极控制分压器具有与场效应晶体管上的上电阻串联的晶体管开关，与下电阻串联。电阻器漂移层设置在上电阻器下方，并且晶体管开关包括与电阻器漂移层相邻的开关漂移层，由防止漂移层之间的击穿的区域分开。开关漂移层为晶体管开关提供了扩展的漏极或集电极。分压器的感测端子耦合到晶体管的源极或发射极节点和下电阻器。输入端子耦合到上电阻器和电阻漂移层。形成包含栅极控制分压器的集成电路的工艺。

5. 发明申请

US20100123448A1 CONTROLLED ON-TIME BUCK PFC 有权
标题翻译：控制的时间补偿PFC
公开(公告)号：US20100123448A1
公开(公告)日：2010-05-20
申请号：US12273460
申请日：2008-11-18
申请人： Robert A. Neidorff , Bing Lu
发明人： Robert A. Neidorff , Bing Lu
IPC分类号： G05F5/00
CPC分类号： G05F1/70 , H02M1/42 , H02M3/157 , H02M3/1588 , H02M2001/4291 , Y02B70/12 , Y02B70/126 , Y02B70/1466
摘要： An apparatus for generating an output voltage from an input voltage is provided. The apparatus comprises a switch that receives the input voltage, an inductor that is coupled to the switch, a capacitor coupled to the inductor with the output voltage being output from a node between the inductor and the capacitor, a measuring circuit that receives and measures the input voltage, and a controller that is coupled to the switch and to the measuring circuit. Additionally, the controller receives the measured input voltage and calculates an on-time for the switch based on the measured input voltage and actuates the switch for the on-time.
摘要翻译：提供一种用于从输入电压产生输出电压的装置。该装置包括接收输入电压的开关，耦合到开关的电感器，耦合到电感器的电容器，其中输出电压从电感器和电容器之间的节点输出;测量电路，其接收和测量输入电压，以及耦合到开关和测量电路的控制器。此外，控制器接收测量的输入电压，并根据测量的输入电压计算开关的导通时间，并为导通时间启动开关。

6. 发明授权

US4924288A High current-gain PNP transistor 失效
标题翻译：高电流增益PNP晶体管
公开(公告)号：US4924288A
公开(公告)日：1990-05-08
申请号：US312372
申请日：1989-02-15
申请人： Robert A. Neidorff
发明人： Robert A. Neidorff
IPC分类号： H01L29/417 , H01L29/735
CPC分类号： H01L29/41708 , H01L29/735
摘要： A high current gain high-frequency planar process PNP transistor comprising an emitter region and a surrounding annular collector. The surface of the transistor is covered with an insulative oxide layer, with an aperture to the emitter region. An overlaying metal layer is provided which substantially covers the base region between the emitter and collector. Connection to the emitter region is provided with an extension of the metal surface to the aperture. However except for this connection, the surface area above the emitter region is not covered by the metal layer. The resulting transistor provides a high-frequency PNP transistor with significantly enhanced Beta.
摘要翻译：包括发射极区域和周围环形收集器的高电流增益高频平面处理PNP晶体管。晶体管的表面被绝缘氧化物层覆盖，具有到发射极区的孔径。提供覆盖金属层，其基本上覆盖发射极和集电极之间的基极区域。与发射极区域的连接设置有金属表面与孔径的延伸。然而，除了这种连接之外，发射极区域上方的表面积不被金属层覆盖。所产生的晶体管提供了具有显着增强的Beta的高频PNP晶体管。

7. 发明授权

US4727264A Fast, low-power, low-drop driver circuit 失效
标题翻译：快速，低功耗，低压驱动电路
公开(公告)号：US4727264A
公开(公告)日：1988-02-23
申请号：US749307
申请日：1985-06-27
申请人： Robert A. Neidorff
发明人： Robert A. Neidorff
IPC分类号： H03K17/0422 , H03K17/615 , H03K17/00
CPC分类号： H03K17/0422 , H03K17/615 , Y10T307/826
摘要： A power driver circuit which provides a low voltage drop thereacross when turned on, without being driven into hard saturation. Hard saturation of the circuit according to the present invention is prevented by additional circuit elements which allow the transistor output circuit to be turned on while diverting excess drive current away from the input transistor. As a result, the driver circuit can provide the low saturation voltage and avoid unnecessary saturation of the output transistor while maintaining high-speed switching operation. The circuit may be implemented by discrete components, by a single integrated circuit or part of a larger integrated circuit.
摘要翻译：电源驱动器电路，当打开时提供低压降，而不会被驱动到硬饱和。通过附加的电路元件来防止根据本发明的电路的硬饱和度，这允许晶体管输出电路导通，同时使过多的驱动电流远离输入晶体管。结果，驱动电路可以提供低饱和电压，并且在保持高速开关操作的同时避免输出晶体管的不必要的饱和。电路可以由分立元件，单个集成电路或较大集成电路的一部分来实现。

8. 发明授权

US08922189B2 Controlled on-time buck PFC 有权
标题翻译：受控时间降压PFC
公开(公告)号：US08922189B2
公开(公告)日：2014-12-30
申请号：US12273460
申请日：2008-11-18
申请人： Robert A. Neidorff , Bing Lu
发明人： Robert A. Neidorff , Bing Lu
IPC分类号： G05F5/00 , G05F1/70 , H02M1/42 , H02M3/157 , H02M3/158 , H02M5/257 , G05F1/00
CPC分类号： G05F1/70 , H02M1/42 , H02M3/157 , H02M3/1588 , H02M2001/4291 , Y02B70/12 , Y02B70/126 , Y02B70/1466
摘要： An apparatus for generating an output voltage from an input voltage is provided. The apparatus comprises a switch that receives the input voltage, an inductor that is coupled to the switch, a capacitor coupled to the inductor with the output voltage being output from a node between the inductor and the capacitor, a measuring circuit that receives and measures the input voltage, and a controller that is coupled to the switch and to the measuring circuit. Additionally, the controller receives the measured input voltage and calculates an on-time for the switch based on the measured input voltage and actuates the switch for the on-time.
摘要翻译：提供一种用于从输入电压产生输出电压的装置。该装置包括接收输入电压的开关，耦合到开关的电感器，耦合到电感器的电容器，其中输出电压从电感器和电容器之间的节点输出;测量电路，其接收和测量输入电压，以及耦合到开关和测量电路的控制器。此外，控制器接收测量的输入电压，并根据测量的输入电压计算开关的导通时间，并为导通时间启动开关。

9. 发明授权

US08558583B2 Slew detection for high voltage isolation region 有权
标题翻译：用于高电压隔离区的摆动检测
公开(公告)号：US08558583B2
公开(公告)日：2013-10-15
申请号：US12758357
申请日：2010-04-12
申请人： Victor Samuel Sinow , Bharath Balaji Kannan , Robert A. Neidorff
发明人： Victor Samuel Sinow , Bharath Balaji Kannan , Robert A. Neidorff
IPC分类号： G11C8/08 , H03K3/00
CPC分类号： H03K17/6871 , H03K2217/0063 , H03K2217/0081
摘要： A system includes control circuitry configured to provide one or more control pulses in response to a command signal, the one or more control pulses being communicated from the control circuitry to associated circuitry via a connection. A detector is configured to detect a disturbing signal that mitigates reception of the one or more control pulses via the connection. The command signal is controlled to cause the control circuitry to provide one or more additional control pulses when the disturbing signal is detected by the detector to improve a likelihood of the reception of the one or more control pulses via the connection.
摘要翻译：系统包括控制电路，其被配置为响应于命令信号提供一个或多个控制脉冲，所述一个或多个控制脉冲通过连接从控制电路传送到相关电路。检测器被配置为检测通过连接减轻一个或多个控制脉冲的接收的干扰信号。控制命令信号以使得控制电路在检测器检测到干扰信号时提供一个或多个附加的控制脉冲，以提高通过连接接收一个或多个控制脉冲的可能性。

10. 发明申请

US20130147513A1 RECURSIVE CODE LOGIC 有权
标题翻译：累积代码逻辑
公开(公告)号：US20130147513A1
公开(公告)日：2013-06-13
申请号：US13324381
申请日：2011-12-13
申请人： Paul G. Hlebowitsh , Robert A. Neidorff
发明人： Paul G. Hlebowitsh , Robert A. Neidorff
IPC分类号： H03K19/173
CPC分类号： H03K19/173 , H03K19/0948
摘要： A logic device includes a transmission gate block configured to receive a binary input and a control input, the transmission gate block configured to provide a multi-bit output that is correlated from the binary input and in response to the control input having a first value. A state driver block is activated to drive one of a low state bit pattern or a high state bit pattern to the multi-bit output in response to the control input having a second value, which is different from the first value.
摘要翻译：逻辑设备包括被配置为接收二进制输入和控制输入的传输门区块，所述传输门区块被配置为提供与二进制输入相关联并响应于具有第一值的控制输入的多位输出。响应于具有不同于第一值的第二值的控制输入，激活状态驱动器块以将低状态位模式或高状态位模式中的一个驱动到多位输出。

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