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1. 发明申请

US20110073955A1 ISOLATION TRENCH WITH ROUNDED CORNERS FOR BiCMOS PROCESS 有权
标题翻译：用于BiCMOS工艺的带圆角的隔离开关
公开(公告)号：US20110073955A1
公开(公告)日：2011-03-31
申请号：US12962159
申请日：2010-12-07
申请人： Sameer P. Pendharkar , John Lin , Philip L. Hower , Steven L. Merchant
发明人： Sameer P. Pendharkar , John Lin , Philip L. Hower , Steven L. Merchant
IPC分类号： H01L27/06
CPC分类号： H01L21/8249 , H01L21/76232 , H01L27/0623
摘要： A semiconductor device comprising a first transistor device (130) on or in a semiconductor substrate (115) and a second transistor device (132) on or in the substrate. The device further comprises an insulating trench (200) located between the first transistor device and the second transistor device. At least one upper corner (610) of the insulating trench is a rounded corner in a lateral plane (620) of the substrate.
摘要翻译：一种半导体器件，包括在半导体衬底（115）上或半导体衬底（115）中的第一晶体管器件（130）和衬底上或衬底中的第二晶体管器件（132）。该器件还包括位于第一晶体管器件和第二晶体管器件之间的绝缘沟槽（200）。绝缘沟槽的至少一个上角（610）是衬底的横向平面（620）中的圆角。

2. 发明授权

US08274131B2 Isolation trench with rounded corners for BiCMOS process 有权
标题翻译：用于BiCMOS工艺的带圆角的隔离槽
公开(公告)号：US08274131B2
公开(公告)日：2012-09-25
申请号：US12962159
申请日：2010-12-07
申请人： Sameer P. Pendharkar , John Lin , Philip L. Hower , Steven L. Merchant
发明人： Sameer P. Pendharkar , John Lin , Philip L. Hower , Steven L. Merchant
IPC分类号： H01L21/70
CPC分类号： H01L21/8249 , H01L21/76232 , H01L27/0623
摘要： A semiconductor device comprising a first transistor device (130) on or in a semiconductor substrate (115) and a second transistor device (132) on or in the substrate. The device further comprises an insulating trench (200) located between the first transistor device and the second transistor device. At least one upper corner (610) of the insulating trench is a rounded corner in a lateral plane (620) of the substrate.
摘要翻译：一种半导体器件，包括在半导体衬底（115）上或半导体衬底（115）中的第一晶体管器件（130）和衬底上或衬底中的第二晶体管器件（132）。该器件还包括位于第一晶体管器件和第二晶体管器件之间的绝缘沟槽（200）。绝缘沟槽的至少一个上角（610）是衬底的横向平面（620）中的圆角。

3. 发明授权

US07846789B2 Isolation trench with rounded corners for BiCMOS process 有权
标题翻译：用于BiCMOS工艺的带圆角的隔离槽
公开(公告)号：US07846789B2
公开(公告)日：2010-12-07
申请号：US11873205
申请日：2007-10-16
申请人： Sameer P. Pendharkar , John Lin , Philip L. Hower , Steven L. Merchant
发明人： Sameer P. Pendharkar , John Lin , Philip L. Hower , Steven L. Merchant
IPC分类号： H01L21/8238
CPC分类号： H01L21/8249 , H01L21/76232 , H01L27/0623
摘要： A semiconductor device comprising a first transistor device on or in a semiconductor substrate and a second transistor device on or in the substrate. The device further comprises an insulating trench located between the first transistor device and the second transistor device. At least one upper corner of the insulating trench is a rounded corner in a lateral plane of the substrate.
摘要翻译：一种半导体器件，包括半导体衬底上或半导体衬底中的第一晶体管器件和衬底上或衬底中的第二晶体管器件。该器件还包括位于第一晶体管器件和第二晶体管器件之间的绝缘沟槽。绝缘沟槽的至少一个上角是衬底的横向平面中的圆角。

4. 发明授权

US07187034B2 Distributed power MOSFET 有权
标题翻译：分布式功率MOSFET
公开(公告)号：US07187034B2
公开(公告)日：2007-03-06
申请号：US10888776
申请日：2004-07-09
申请人： Philip L. Hower , John Lin , Sameer P. Pendharkar , Steven L. Merchant
发明人： Philip L. Hower , John Lin , Sameer P. Pendharkar , Steven L. Merchant
IPC分类号： H01L29/78
CPC分类号： H01L29/7816 , H01L23/4824 , H01L29/0696 , H01L29/41758 , H01L29/4238 , H01L2924/0002 , H01L2924/00
摘要： Segmented power transistors and fabrication methods are disclosed in which transistor segments are spaced from one another to facilitate thermal diffusion, and in which other electrical devices can be formed in the spaces between transistor segments.
摘要翻译：公开了分段功率晶体管和制造方法，其中晶体管段彼此间隔开以促进热扩散，并且其中可以在晶体管段之间的空间中形成其它电气器件。

5. 发明授权

US06815276B2 Segmented power MOSFET of safe operation 有权
标题翻译：分段功率MOSFET安全运行
公开(公告)号：US06815276B2
公开(公告)日：2004-11-09
申请号：US10264038
申请日：2002-10-03
申请人： Philip L. Hower , John Lin , Sameer P. Pendharkar , Steven L. Merchant
发明人： Philip L. Hower , John Lin , Sameer P. Pendharkar , Steven L. Merchant
IPC分类号： H01L21336
CPC分类号： H01L29/7816 , H01L23/4824 , H01L29/0696 , H01L29/41758 , H01L29/4238 , H01L2924/0002 , H01L2924/00
摘要： Segmented power transistors and fabrication methods are disclosed in which transistor segments are spaced from one another to facilitate thermal diffusion, and in which other electrical devices can be formed in the spaces between transistor segments.
摘要翻译：公开了分段功率晶体管和制造方法，其中晶体管段彼此间隔开以促进热扩散，并且其中可以在晶体管段之间的空间中形成其它电气器件。

6. 发明申请

US20090096033A1 ISOLATION TRENCH WITH ROUNDED CORNERS FOR BiCMOS PROCESS 有权
标题翻译：用于BiCMOS工艺的带圆角的隔离开关
公开(公告)号：US20090096033A1
公开(公告)日：2009-04-16
申请号：US11873205
申请日：2007-10-16
申请人： Sameer P. Pendharkar , John Lin , Philip Hower , Steven L. Merchant
发明人： Sameer P. Pendharkar , John Lin , Philip Hower , Steven L. Merchant
IPC分类号： H01L29/94 , H01L21/8238
CPC分类号： H01L21/8249 , H01L21/76232 , H01L27/0623
摘要： A semiconductor device comprising a first transistor device on or in a semiconductor substrate and a second transistor device on or in the substrate. The device further comprises an insulating trench located between the first transistor device and the second transistor device. At least one upper corner of the insulating trench is a rounded corner in a lateral plane of the substrate.
摘要翻译：一种半导体器件，包括半导体衬底上或半导体衬底中的第一晶体管器件和衬底上或衬底中的第二晶体管器件。该器件还包括位于第一晶体管器件和第二晶体管器件之间的绝缘沟槽。绝缘沟槽的至少一个上角是衬底的横向平面中的圆角。

7. 发明授权

US06624481B1 ESD robust bipolar transistor with high variable trigger and sustaining voltages 有权
标题翻译：具有高可变触发和维持电压的ESD稳健双极晶体管
公开(公告)号：US06624481B1
公开(公告)日：2003-09-23
申请号：US10407037
申请日：2003-04-04
申请人： Sameer P. Pendharkar , Philip L. Hower , Robert Steinhoff
发明人： Sameer P. Pendharkar , Philip L. Hower , Robert Steinhoff
IPC分类号： H01L2362
CPC分类号： H01L27/0259 , H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： An ESD robust bipolar transistor (200) that includes first and second bipolar elements (210, 220), wherein a first trigger voltage of the first bipolar element (210) is proximate a second sustaining voltage of the second bipolar element (220). The first and second bipolar elements (210, 220) include first and second bases (214, 224), emitters (216, 226) and collectors (212, 222), respectively. The first and second bases (214, 224) are coupled and the first and second collectors (212, 222) are coupled. The ESD robust bipolar transistor (200) also includes an emitter resistor (250) and a base resistor (260), wherein the emitter resistor (250) couples the first and second emitters (216, 226) and the base resistor (260) couples the second emitter (226) and the first and second bases (214, 224).
摘要翻译：包括第一和第二双极元件（210,220）的ESD坚固的双极晶体管（200），其中第一双极元件（210）的第一触发电压接近第二双极元件（220）的第二维持电压。第一和第二双极元件（210,220）分别包括第一和第二基极（214,224），发射极（216,226）和集电极（212,222）。耦合第一和第二基极（214,224），并且耦合第一和第二集电极（212,222）。 ESD稳健双极晶体管（200）还包括发射极电阻（250）和基极电阻（260），其中发射极电阻（250）将第一和第二发射极（216,226）和基极电阻（260）耦合第二发射器（226）和第一和第二基极（214,224）。

8. 发明授权

US06797547B2 Bladed silicon-on-insulator semiconductor devices and method of making 有权
公开(公告)号：US06797547B2
公开(公告)日：2004-09-28
申请号：US10679220
申请日：2003-10-03
申请人： Sheldon D. Haynie , Steven L. Merchant , Sameer P. Pendharkar , Vladimir Bolkhovsky
发明人： Sheldon D. Haynie , Steven L. Merchant , Sameer P. Pendharkar , Vladimir Bolkhovsky
IPC分类号： H01L2100
CPC分类号： H01L29/66681 , H01L29/0657 , H01L29/4175 , H01L29/66674 , H01L29/66772 , H01L29/7824 , H01L29/78624 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes an elongated, blade-shaped semiconductor element isolated from a surrounding region of a semiconductor substrate by buried and side oxide layers. A polysilicon post disposed at one end of the element has a bottom portion extending through the buried oxide to contact the substrate, providing for electrical and thermal coupling between the element and the substrate and for gettering impurities during processing. A device fabrication process employs a selective silicon-on-insulator (SOI) technique including forming trenches in the substrate; passivating the upper portion of the element; and performing a long oxidation to create the buried oxide layer. A second oxidation is used to create an insulating oxide layer on the sidewalls of the semiconductor element, and polysilicon material is used to fill the trenches and to create the post. The process can be used with conventional bulk silicon wafers and processes, and the blade devices can be integrated with conventional planar devices formed on other areas of the wafer.

9. 发明授权

US06800917B2 Bladed silicon-on-insulator semiconductor devices and method of making 有权
标题翻译：刀片绝缘体上半导体器件及其制造方法
公开(公告)号：US06800917B2
公开(公告)日：2004-10-05
申请号：US10321423
申请日：2002-12-17
申请人： Sheldon D. Haynie , Steven L. Merchant , Sameer P. Pendharkar , Vladimir Bolkhovsky
发明人： Sheldon D. Haynie , Steven L. Merchant , Sameer P. Pendharkar , Vladimir Bolkhovsky
IPC分类号： H01L2176
CPC分类号： H01L29/66681 , H01L29/0657 , H01L29/4175 , H01L29/66674 , H01L29/66772 , H01L29/7824 , H01L29/78624 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes an elongated, blade-shaped semiconductor element isolated from a surrounding region of a semiconductor substrate by buried and side oxide layers. A polysilicon post disposed at one end of the element has a bottom portion extending through the buried oxide to contact the substrate, providing for electrical and thermal coupling between the element and the substrate and for gettering impurities during processing. A device fabrication process employs a selective silicon-on-insulator (SOI) technique including forming trenches in the substrate; passivating the upper portion of the element; and performing a long oxidation to create the buried oxide layer. A second oxidation is used to create an insulating oxide layer on the sidewalls of the semiconductor element, and polysilicon material is used to fill the trenches and to create the post. The process can be used with conventional bulk silicon wafers and processes, and the blade devices can be integrated with conventional planar devices formed on other areas of the wafer.
摘要翻译：半导体器件包括通过掩埋和侧面氧化物层与半导体衬底的周围区域隔离的细长的刀片状半导体元件。设置在元件的一端的多晶硅柱具有延伸穿过掩埋氧化物的底部部分以接触基板，从而提供元件和基板之间的电和热耦合以及在处理期间吸杂杂质。器件制造工艺采用选择性绝缘体上硅（SOI）技术，包括在衬底中形成沟槽; 钝化元件的上部; 并进行长时间氧化以形成掩埋氧化物层。使用第二氧化在半导体元件的侧壁上产生绝缘氧化物层，并且使用多晶硅材料填充沟槽并形成柱。该方法可以与传统的体硅晶片和工艺一起使用，并且刀片装置可以与形成在晶片的其它区域上的常规平面装置集成。

10. 发明授权

US08754469B2 Hybrid active-field gap extended drain MOS transistor 有权
标题翻译：混合有源场间隙扩展漏极MOS晶体管
公开(公告)号：US08754469B2
公开(公告)日：2014-06-17
申请号：US13281260
申请日：2011-10-25
申请人： Sameer P. Pendharkar , John Lin
发明人： Sameer P. Pendharkar , John Lin
IPC分类号： H01L29/66
CPC分类号： H01L29/66681 , H01L29/0653 , H01L29/0696 , H01L29/0882 , H01L29/402 , H01L29/41758 , H01L29/4238 , H01L29/7816
摘要： An integrated circuit includes an extended drain MOS transistor with parallel alternating active gap drift regions and field gap drift regions. The extended drain MOS transistor includes a gate having field plates over the field gap drift regions. The extended drain MOS transistor may be formed in a symmetric nested configuration. A process for forming an integrated circuit containing an extended drain MOS transistor provides parallel alternating active gap drift regions and field gap drift regions with a gate having field plates over the field gap drift regions.
摘要翻译：集成电路包括具有并行交替有源间隙漂移区和场间隙漂移区的扩展漏极MOS晶体管。扩展漏极MOS晶体管包括在场间隙漂移区域上具有场板的栅极。扩展漏极MOS晶体管可以形成为对称嵌套配置。用于形成包含延伸漏极MOS晶体管的集成电路的工艺提供并行的交替有源间隙漂移区域和场间隙漂移区域，栅极在场间隙漂移区域上具有场板。

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