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1. 发明授权

US06376349B1 Process for forming a semiconductor device and a conductive structure 有权
标题翻译：用于形成半导体器件和导电结构的工艺
公开(公告)号：US06376349B1
公开(公告)日：2002-04-23
申请号：US09487472
申请日：2000-01-19
申请人： Philip J. Tobin , Olubunmi Adetutu , Bikas Maiti
发明人： Philip J. Tobin , Olubunmi Adetutu , Bikas Maiti
IPC分类号： H01L213205
CPC分类号： H01L29/4958 , H01L21/28079
摘要： Semiconductor devices and conductive structures can be formed having a metallic layer. In one embodiment, a semiconductor device includes an amorphous metallic layer (22) and a crystalline metallic layer (42). The amorphous metallic layer (22) helps to reduce the likelihood of penetration of contaminants through the amorphous metallic layer (22). A more conductive crystalline metallic layer (42) can be formed on the amorphous metallic layer (22) to help keep resistivity relatively low. When forming a conductive structure, a metal-containing gas and a scavenger gas flow simultaneously during at least one point in time. The conductive structure may be part of a gate electrode.
摘要翻译：可以形成具有金属层的半导体器件和导电结构。在一个实施例中，半导体器件包括非晶金属层（22）和结晶金属层（42）。无定形金属层（22）有助于降低污染物穿过非晶金属层（22）的可能性。可以在非晶金属层（22）上形成更导电的晶体金属层（42），以帮助保持电阻率相对较低。当形成导电结构时，含金属的气体和清除气体在至少一个时间点内同时流动。导电结构可以是栅电极的一部分。

2. 发明授权

US6084279A Semiconductor device having a metal containing layer overlying a gate dielectric 失效
标题翻译：具有覆盖在栅极电介质上的含金属层的半导体器件
公开(公告)号：US6084279A
公开(公告)日：2000-07-04
申请号：US831287
申请日：1997-03-31
申请人： Bich-Yen Nguyen , J. Olufemi Olowolafe , Bikas Maiti , Olubunmi Adetutu , Philip J. Tobin
发明人： Bich-Yen Nguyen , J. Olufemi Olowolafe , Bikas Maiti , Olubunmi Adetutu , Philip J. Tobin
IPC分类号： H01L29/78 , H01L21/28 , H01L21/285 , H01L21/768 , H01L21/8234 , H01L21/8244 , H01L23/31 , H01L29/49 , H01L21/338
CPC分类号： H01L27/11 , H01L21/28044 , H01L21/28088 , H01L21/28568 , H01L21/76895 , H01L21/82345 , H01L23/3171 , H01L29/4925 , H01L29/4966 , H01L2924/0002
摘要： Metal semiconductor nitride gate electrodes (40, 70) are formed for use in a semiconductor device (60). The gate electrodes (40, 70) may be formed by sputter deposition, low pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD). The materials are expected to etch similar to silicon-containing compounds and may be etched in traditional halide-based etching chemistries. The metal semiconductor nitride gate electrodes (40, 70) are relatively stable, can be formed relatively thinner than traditional gate electrodes (40, 70) and work functions near the middle of the band gap for the material of the substrate (12).
摘要翻译：金属半导体氮化物栅电极（40,70）形成用于半导体器件（60）。栅电极（40,70）可以通过溅射沉积，低压化学气相沉积（LPCVD）或等离子体增强化学气相沉积（PECVD）来形成。预期这些材料将类似于含硅化合物蚀刻，并且可以在传统的基于卤化物的蚀刻化学中进行蚀刻。金属半导体氮化物栅电极（40,70）相对稳定，可以形成为比传统栅极电极（40,70）更靠近工作功能，并且靠近用于衬底（12）的材料的带隙中间的功函数。

3. 发明授权

US06255204B1 Method for forming a semiconductor device 有权
标题翻译：半导体器件形成方法
公开(公告)号：US06255204B1
公开(公告)日：2001-07-03
申请号：US09316012
申请日：1999-05-21
申请人： Philip J. Tobin , Olubunmi O. Adetutu , Rama I. Hegde , Bikas Maiti
发明人： Philip J. Tobin , Olubunmi O. Adetutu , Rama I. Hegde , Bikas Maiti
IPC分类号： H01L214763
CPC分类号： H01L29/66545 , H01L21/28079 , H01L21/28088 , H01L29/495 , H01L29/4966 , H01L29/6656 , H01L29/7842
摘要： A first metal-containing material (22) is formed over a semiconductor device substrate (10). A second metal-containing material (32) is formed over the first metal containing material (22). The combination of the second metal-containing material (32) formed over the first metal-containing material (22) forms a metal stack (34). The metal stack (34) is annealed and a post-anneal stress of the metal stack (34) is less than an individual post-anneal stress of either one of the first conductive film (22) or the second conductive film (32).
摘要翻译：第一含金属材料（22）形成在半导体器件衬底（10）上。在第一含金属材料（22）之上形成第二含金属材料（32）。形成在第一含金属材料（22）上方的第二含金属材料（32）的组合形成金属叠层（34）。金属叠层（34）退火，并且金属叠层（34）的退火后应力小于第一导电膜（22）或第二导电膜（32）中的任一个的单个后退火应力。

4. 发明授权

US6020024A Method for forming high dielectric constant metal oxides 失效
标题翻译：形成高介电常数金属氧化物的方法
公开(公告)号：US6020024A
公开(公告)日：2000-02-01
申请号：US905755
申请日：1997-08-04
申请人： Bikas Maiti , Philip J. Tobin , Rama I. Hegde , Jesus Cuellar
发明人： Bikas Maiti , Philip J. Tobin , Rama I. Hegde , Jesus Cuellar
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L29/51 , H01L29/78 , C23C16/00
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/2822 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/6659
摘要： A method for forming a metal gate (20) structure begins by providing a semiconductor substrate (12). The semiconductor substrate (12) is cleaned to reduce trap sites. A nitrided layer (14) having a thickness of less than approximately 20 Angstroms is formed over the substrate (12). This nitrided layer prevents the formation of an oxide at the substrate interface and has a dielectric constant greater than 3.9. After the formation of the nitrided layer(14), a metal oxide layer (16) having a permittivity value of greater than roughly 8.0 is formed over the nitrided layer (14). A metal gate (20) is formed over the nitrided layer whereby the remaining composite gate dielectric (14 and 16) has a larger physical thickness but a high-performance equivalent oxide thickness (EOT).
摘要翻译：一种用于形成金属栅极（20）结构的方法是通过提供半导体衬底（12）开始的。对半导体衬底（12）进行清洁以减少陷阱位置。在衬底（12）上形成厚度小于约20埃的氮化层（14）。该氮化层防止在衬底界面处形成氧化物并具有大于3.9的介电常数。在形成氮化层（14）之后，在氮化层（14）上形成介电常数值大于大约8.0的金属氧化物层（16）。在氮化层上形成金属栅极（20），由此剩余的复合栅极电介质（14和16）具有较大的物理厚度，但具有高性能的等效氧化物厚度（EOT）。

5. 发明授权

US5885870A Method for forming a semiconductor device having a nitrided oxide dielectric layer 失效
标题翻译：用于形成具有氮化氧化物介电层的半导体器件的方法
公开(公告)号：US5885870A
公开(公告)日：1999-03-23
申请号：US886927
申请日：1997-07-02
申请人： Bikas Maiti , Philip J. Tobin , Sergio A. Ajuria
发明人： Bikas Maiti , Philip J. Tobin , Sergio A. Ajuria
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/314 , H01L21/316 , H01L21/318 , H01L21/336 , H01L27/115 , H01L29/51 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28185 , H01L21/0214 , H01L21/02238 , H01L21/02255 , H01L21/02332 , H01L21/02337 , H01L21/28202 , H01L21/3144 , H01L21/31662 , H01L29/513 , H01L29/518 , H01L29/66825
摘要： In one embodiment a non-volatile memory device having improved reliability is formed by oxidizing a first portion of a semiconductor substrate (12) to form a first silicon dioxide layer (14). The first silicon dioxide layer (14) is then annealed and second portion of the silicon substrate, underlying the annealed silicon dioxide layer (16), is then oxidized to form a second silicon dioxide layer (18). The annealed silicon dioxide layer (16) and the second silicon dioxide layer (18) form a pre-oxide layer (20). The pre-oxide layer (20) is then nitrided to form a nitrided oxide dielectric layer (22). A floating gate is then formed overlying the nitrided oxide dielectric layer (22), which serves as the tunnel oxide for the device. Tunnel oxides formed with the inventive process are less susceptible to stress-induced leakage, and therefore, devices with improved data retention and endurance may be fabricated.
摘要翻译：在一个实施例中，通过氧化半导体衬底（12）的第一部分以形成第一二氧化硅层（14）来形成具有改善的可靠性的非易失性存储器件。然后退火第一二氧化硅层（14），然后氧化氧化形成第二二氧化硅层（18）的第二部分硅衬底（在退火的二氧化硅层下面）。退火的二氧化硅层（16）和第二二氧化硅层（18）形成预氧化物层（20）。然后将预氧化物层（20）氮化以形成氮化氧化物介电层（22）。然后形成覆盖氮化氧化物介电层（22）的浮栅，其用作器件的隧道氧化物。用本发明方法形成的隧道氧化物不易受到应力诱发的泄漏的影响，因此，可以制造具有改善的数据保持和耐久性的装置。

6. 发明授权

US5830802A Process for reducing halogen concentration in a material layer during semiconductor device fabrication 失效
标题翻译：在半导体器件制造期间降低材料层中的卤素浓度的方法
公开(公告)号：US5830802A
公开(公告)日：1998-11-03
申请号：US521720
申请日：1995-08-31
申请人： Hsing-Huang Tseng , Philip J. Tobin , Bikas Maiti
发明人： Hsing-Huang Tseng , Philip J. Tobin , Bikas Maiti
IPC分类号： H01L21/28 , H01L21/321 , H01L21/311
CPC分类号： H01L21/28061 , H01L21/321 , Y10S148/06 , Y10S148/147
摘要： A process for reducing halogen concentration in a material layer (56) includes the deposition of a dielectric layer (58) overlying the material layer (56). An annealing process is carried out to diffuse halogen atoms from the material layer (56) into the overlying dielectric layer (58). Once the diffusion process is complete, the dielectric layer (58) is removed.
摘要翻译：用于降低材料层（56）中的卤素浓度的方法包括沉积覆盖在材料层（56）上的介电层（58）。进行退火处理以将卤素原子从材料层（56）扩散到上覆电介质层（58）中。一旦扩散过程完成，去除电介质层（58）。

7. 发明授权

US6027961A CMOS semiconductor devices and method of formation 失效
标题翻译： CMOS半导体器件及其形成方法
公开(公告)号：US6027961A
公开(公告)日：2000-02-22
申请号：US107963
申请日：1998-06-30
申请人： Bikas Maiti , Philip J. Tobin , C. Joseph Mogab , Christopher Hobbs , Larry E. Frisa
发明人： Bikas Maiti , Philip J. Tobin , C. Joseph Mogab , Christopher Hobbs , Larry E. Frisa
IPC分类号： H01L29/78 , H01L21/28 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/43 , H01L29/49
CPC分类号： H01L21/823842 , H01L27/0922
摘要： In one embodiment, a metal layer (18) is formed over a gate dielectric layer (14, 16) on a semiconductor substrate. A masking layer (20) is patterned to mask a portion of the metal layer (18). An exposed portion of the metal layer (18) is nitrided to form a conductive nitride layer (24). The masking layer (20) is removed and the conductive nitride layer (24) is patterned to form a first gate electrode (23) having a first work function value, and the conductive layer (18) is patterned to form a second gate electrode (25) having a second work function value which is different from that of the first work function value.
摘要翻译：在一个实施例中，金属层（18）形成在半导体衬底上的栅极介电层（14,16）上。图案化掩模层（20）以掩盖金属层（18）的一部分。金属层（18）的暴露部分被氮化以形成导电氮化物层（24）。去除掩模层（20）并且对导电氮化物层（24）进行图案化以形成具有第一功函数值的第一栅电极（23），并且对导电层（18）进行图案化以形成第二栅极电极 25）具有与第一功函数值不同的第二功函数值。

8. 发明申请

US20110211382A1 HIGH DENSITY AND LOW VARIABILITY READ ONLY MEMORY 审中-公开
标题翻译：高密度和低可变性只读存储器
公开(公告)号：US20110211382A1
公开(公告)日：2011-09-01
申请号：US12714528
申请日：2010-02-28
申请人： Ashish SHARMA , Bikas Maiti , Manmohan Rana
发明人： Ashish SHARMA , Bikas Maiti , Manmohan Rana
IPC分类号： G11C17/00 , G11C7/00
CPC分类号： G11C17/18 , G11C11/5692 , G11C17/12
摘要： A read-only memory for storing two data values using a single transistor includes a word line, a pair of bit lines, a select line, and a transistor to store data corresponding to each bit lines in the pair of bit lines. The gate terminal of the transistor is connected to the word line, a first diffusion terminal of the transistor is connected to one of the first bit line and the select line based on the first data value and a second diffusion terminal of the transistor is connected to one of the second bit line and the select line based on the second data value.
摘要翻译：用于使用单个晶体管存储两个数据值的只读存储器包括字线，一对位线，选择线和晶体管，以存储对应于该对位线中的每个位线的数据。晶体管的栅极端子连接到字线，晶体管的第一扩散端基于第一数据值连接到第一位线和选择线之一，并且晶体管的第二扩散端连接到第二位线之一和基于第二数据值的选择线。

9. 发明授权

US06171910B2 Method for forming a semiconductor device 有权
标题翻译：半导体器件形成方法
公开(公告)号：US06171910B2
公开(公告)日：2001-01-09
申请号：US09358213
申请日：1999-07-21
申请人： Christopher C. Hobbs , Bikas Maiti , Wei Wu
发明人： Christopher C. Hobbs , Bikas Maiti , Wei Wu
IPC分类号： H01L21336
CPC分类号： H01L21/823842
摘要： First and second dummy structures (201 and 202) are formed over a semiconductor device substrate (10). In one embodiment, portions of the first dummy structure (201) are removed and replaced with a first conductive material (64) to form a first gate electrode (71) and portions of second dummy structure (202) are removed and replaced with a second conductive material (84) to form a second gate electrode (91). In an alternate embodiment, the dummy structures (201 and 202) are formed using a first conductive material (164) that is used to form the first electrode (71). The second electrode is then formed by removing the first conductive material (164) from dummy structures (202) and replacing it with a second conductive material (84). In accordance with embodiments of the present invention, the first conductive material and the second conductive material are different conductive materials.
摘要翻译：第一和第二虚拟结构（201和202）形成在半导体器件衬底（10）上。在一个实施例中，去除第一虚拟结构（201）的部分并用第一导电材料（64）代替以形成第一栅电极（71），并且去除第二虚拟结构（202）的部分并用第二导电材料（84）以形成第二栅电极（91）。在替代实施例中，使用用于形成第一电极（71）的第一导电材料（164）形成虚拟结构（201和202）。然后通过从虚拟结构（202）去除第一导电材料（164）并用第二导电材料（84）代替第二电极而形成第二电极。根据本发明的实施例，第一导电材料和第二导电材料是不同的导电材料。

10. 发明申请

US20110128807A1 MEMORY DEVICE AND SENSE CIRCUITRY THEREFOR 审中-公开
标题翻译：存储器件和感测电路
公开(公告)号：US20110128807A1
公开(公告)日：2011-06-02
申请号：US12697275
申请日：2010-01-31
申请人： Ashish Sharma , Lawrence F. Childs , Bikas Maiti , Manmohan Rana
发明人： Ashish Sharma , Lawrence F. Childs , Bikas Maiti , Manmohan Rana
IPC分类号： G11C7/00 , G11C7/02 , G11C8/00
CPC分类号： G11C7/08 , G11C7/227
摘要： A memory device includes a memory array, sense circuitry coupled to the memory array, and timing circuitry coupled to the sense circuitry. The timing circuitry generates a sense trigger signal to enable the sense circuitry. A strap region is formed adjacent the memory array. A reference word line is coupled to the timing circuitry. The reference word line formed in the strap region.
摘要翻译：存储器件包括存储器阵列，耦合到存储器阵列的检测电路和耦合到感测电路的定时电路。定时电路产生感测触发信号以使能感测电路。带状区域形成在存储器阵列附近。参考字线耦合到定时电路。在带区域中形成的参考字线。

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