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1. 发明授权

US08588228B1 Nonvolatile memory controller with host controller interface for retrieving and dispatching nonvolatile memory commands in a distributed manner 有权
标题翻译：具有主机控制器接口的非易失性存储器控制器，用于以分布式方式检索和调度非易失性存储器命令
公开(公告)号：US08588228B1
公开(公告)日：2013-11-19
申请号：US13052008
申请日：2011-03-18
申请人： Peter Z. Onufryk , Jayesh Patel , Ihab Jaser , Ganesh T. Seshan
发明人： Peter Z. Onufryk , Jayesh Patel , Ihab Jaser , Ganesh T. Seshan
IPC分类号： H04L12/28
CPC分类号： G06F13/24 , Y02D10/14
摘要： A nonvolatile memory controller includes a host controller interface, processors, a message networks and a data network. The host controller interface includes a command fetch module, command assembly buffers, and a command dispatch module. The command fetch module retrieves nonvolatile memory commands from a host processing unit. The command assembly buffers store the nonvolatile memory commands retrieved from the host processing unit. The command dispatch module generates request message packets including the nonvolatile memory commands. The message network routes the request message packets to the processors. The processors process the nonvolatile memory commands in the request message packets for controlling operation of the nonvolatile memory controller.
摘要翻译：非易失性存储器控制器包括主机控制器接口，处理器，消息网络和数据网络。主机控制器接口包括命令提取模块，命令汇编缓冲区和命令分派模块。命令提取模块从主机处理单元检索非易失性存储器命令。命令汇编缓冲器存储从主机处理单元检索的非易失性存储器命令。命令分派模块生成包含非易失性存储器命令的请求消息包。消息网络将请求消息数据包路由到处理器。处理器处理请求消息分组中的非易失性存储器命令，以控制非易失性存储器控制器的操作。

2. 发明授权

US08554968B1 Interrupt technique for a nonvolatile memory controller 有权
标题翻译：非易失性存储器控制器的中断技术
公开(公告)号：US08554968B1
公开(公告)日：2013-10-08
申请号：US13052388
申请日：2011-03-21
申请人： Peter Z. Onufryk , Jayesh Patel , Ihab Jaser
发明人： Peter Z. Onufryk , Jayesh Patel , Ihab Jaser
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , Y02D10/14
摘要： A nonvolatile memory controller processes a nonvolatile memory command and generates a completion status for the nonvolatile memory command. The nonvolatile memory controller transmits the completion status to a host processing unit for storage in a completion queue of the host processing unit. An interrupt manager in the nonvolatile memory controller determines the completion queue contains an unprocessed completion status and generates an interrupt message packet. The nonvolatile memory controller transmits the interrupt message packet to the host processing unit for triggering an interrupt in the host processing unit and alerting the host processing unit to the unprocessed completion status.
摘要翻译：非易失性存储器控制器处理非易失性存储器命令并且生成用于非易失性存储器命令的完成状态。非易失性存储器控制器将完成状态发送到主机处理单元以存储在主机处理单元的完成队列中。非易失性存储器控制器中的中断管理器确定完成队列包含未处理的完成状态并产生中断消息包。非易失性存储器控制器将中断消息分组发送到主机处理单元，用于触发主机处理单元中的中断，并将主机处理单元提醒到未处理的完成状态。

3. 发明授权

US08107479B2 Method and system for telephony and high-speed data access on a broadband access network 有权
标题翻译：在宽带接入网络上进行电话和高速数据接入的方法和系统
公开(公告)号：US08107479B2
公开(公告)日：2012-01-31
申请号：US10705048
申请日：2003-11-10
申请人： Steven Michael Bellovin , Joseph Henry Condon , Richard Vandervoort Cox , Alexander Gibson Fraser , Charles Robert Kalmanek, Jr. , Alan Edward Kaplan , Thomas Joseph Killian , William Todd Marshall , Peter Z. Onufryk , Kadangode K. Ramakrishnan , Norman Loren Schryer
发明人： Steven Michael Bellovin , Joseph Henry Condon , Richard Vandervoort Cox , Alexander Gibson Fraser , Charles Robert Kalmanek, Jr. , Alan Edward Kaplan , Thomas Joseph Killian , William Todd Marshall , Peter Z. Onufryk , Kadangode K. Ramakrishnan , Norman Loren Schryer
IPC分类号： H04L12/28
CPC分类号： H04Q11/0478 , H04L29/06 , H04L69/40 , H04L2012/5615 , H04L2012/5663 , H04M7/0057 , H04M7/006
摘要： A system and method for providing telephony and high-speed data access over a broadband access network, comprising a network interface unit (NIU) coupled to a backup local exchange carrier (LEC) line, the broadband access network coupled to the NIU, an intermediate point-of-presence (IPOP) coupled to the broadband access network, and at least one external access network coupled to the IPOP. The system also provides for a fail-safe mode in which the NIU supports the LEC line for lifeline services.
摘要翻译：一种用于通过宽带接入网络提供电话和高速数据接入的系统和方法，包括耦合到备用本地交换载波（LEC）线路的网络接口单元（NIU），耦合到NIU的宽带接入网络，中间耦合到宽带接入网络的接入点（IPOP）以及耦合到IPOP的至少一个外部接入网络。该系统还提供了故障安全模式，其中NIU支持用于生命线服务的LEC线路。

4. 发明授权

US07587439B1 Method and apparatus for generating a random bit stream in true random number generator fashion 有权
标题翻译：用于以真随机数发生器方式产生随机比特流的方法和装置
公开(公告)号：US07587439B1
公开(公告)日：2009-09-08
申请号：US10222543
申请日：2002-08-16
申请人： Peter Z. Onufryk , Nelson L. Yue
发明人： Peter Z. Onufryk , Nelson L. Yue
IPC分类号： G06F7/58
CPC分类号： G06F7/588
摘要： A method and apparatus for generating a random bit stream in true random number generator fashion are described. Two periodic signals are employed in generating the random bit stream. A first periodic signal having preferably an approximately fifty percent duty cycle and jitter induced by supply and substrate noise is sampled by a second periodic signal that is relatively jitter-free and of a lower frequency than the first periodic signal.
摘要翻译：描述用于以真随机数发生器方式产生随机比特流的方法和装置。在生成随机比特流时采用两个周期信号。具有优选约50％的占空比和由电源和衬底噪声引起的抖动的第一周期性信号由相对无抖动且频率比第一周期信号低的频率的第二周期信号来采样。

5. 发明授权

US06826177B1 Packet telephony appliance 有权
标题翻译：分组电话设备
公开(公告)号：US06826177B1
公开(公告)日：2004-11-30
申请号：US09594288
申请日：2000-06-15
申请人： Mike Chan , Charles D. Cranor , Raman Gopalakrishnan , Peter Z. Onufryk , Laurence W. Ruedisueli , Cormac John Sreenan
发明人： Mike Chan , Charles D. Cranor , Raman Gopalakrishnan , Peter Z. Onufryk , Laurence W. Ruedisueli , Cormac John Sreenan
IPC分类号： H04L1266
CPC分类号： H04L12/6418
摘要： A packet telephony appliance includes a Euphony network processor that integrates networking and DSP functions to provide a low cost and efficient solution in building a networked appliance. In particular, a Euphony ATM Telephone (EAT) is built around the Euphony network processor. The EAT uses a real-time operating system to provide predictable processing and networking support. The EAT implements IObufs, which provides a unified buffering scheme that allows zero-copy data movement. Furthermore, the EAT uses an Event Exchange (EVX), which provides a flexible mechanism for event distribution, allowing software modules to be composed together in an extensible manner. EVX and IObufs are used together to provide highly efficient intra-appliance communication. The EAT provides a platform that can evolve gracefully to support new protocols, advanced telephony services and enhanced user interfaces.
摘要翻译：分组电话设备包括集成网络和DSP功能的Euphony网络处理器，以在构建联网设备中提供低成本和高效的解决方案。尤其是Euphony网络处理器的Euphony ATM电话（EAT）。 EAT使用实时操作系统来提供可预测的处理和网络支持。 EAT实现IObufs，它提供了允许零拷贝数据移动的统一缓冲方案。此外，EAT使用事件交换（EVX），为事件分发提供灵活的机制，允许软件模块以可扩展的方式组合在一起。 EVX和IObufs一起使用，可提供高效的家用电器间通信。 EAT提供了一个平台，可以正常演进，以支持新协议，高级电话服务和增强的用户界面。

6. 发明授权

US08694849B1 Shuffler error correction code system and method 有权
标题翻译：洗牌机纠错码系统及方法
公开(公告)号：US08694849B1
公开(公告)日：2014-04-08
申请号：US13330573
申请日：2011-12-19
申请人： Rino Micheloni , Alessia Marelli , Peter Z. Onufryk
发明人： Rino Micheloni , Alessia Marelli , Peter Z. Onufryk
IPC分类号： H03M13/00
CPC分类号： H03M13/2906 , G06F11/1048 , G06F11/1076 , H03M13/152 , H03M13/19
摘要： A data storage device stores a data unit in a memory page of a storage block along with an error correction code unit for the data unit. Additionally, the data storage device stores an error correction code unit for the data unit in a memory page of another storage block. In various embodiments, one or both of the error correction code units form an error correction code for correcting data bit errors in the data unit. Because the memory page containing the data unit does not have a storage capacity for simultaneously storing the error correction code and the data unit, the data storage device is capable of correcting a greater number of data bit errors in the data unit by using the error correction code in comparison to using an error correction code that would fit in the memory page.
摘要翻译：数据存储装置将数据单元与数据单元的纠错码单元一起存储在存储块的存储器页中。此外，数据存储装置将用于数据单元的纠错码单元存储在另一存储块的存储器页中。在各种实施例中，纠错码单元中的一个或两个形成用于校正数据单元中的数据位错误的纠错码。由于包含数据单元的存储器页面不具有用于同时存储纠错码和数据单元的存储容量，所以数据存储装置能够通过使用纠错码来校正数据单元中更大数量的数据位错误代码与使用适合内存页面的纠错码进行比较。

7. 发明授权

US08397144B1 BCH data correction system and method 有权
标题翻译： BCH数据校正系统及方法
公开(公告)号：US08397144B1
公开(公告)日：2013-03-12
申请号：US12913716
申请日：2010-10-27
申请人： Christopher I. W. Norrie , Alessia Marelli , Rino Micheloni , Peter Z. Onufryk
发明人： Christopher I. W. Norrie , Alessia Marelli , Rino Micheloni , Peter Z. Onufryk
IPC分类号： H03M13/00
CPC分类号： H03M13/6566 , H03M13/152 , H03M13/1555 , H03M13/6561
摘要： In various embodiments, a data correction system has a data path including search modules. Each of the search modules has a respective bit error capacity for locating a number of data bit errors in a data unit based on a locator polynomial. The data correction system generates a syndrome based on an input data unit, generates a locator polynomial based on the syndrome, and determines a number of data bit errors in the input data unit based on the locator polynomial. Additionally, the data correction system selects one of the search modules having a bit error capacity of at least the number of data bit errors in the input data unit. The selected search module generates an error indicator based on the locator polynomial. The data correction system corrects each data bit error in the input data unit based on the error indicator.
摘要翻译：在各种实施例中，数据校正系统具有包括搜索模块的数据路径。每个搜索模块具有用于基于定位多项式定位数据单元中的多个数据位错误的相应位错误容量。数据校正系统基于输入数据单元产生校正子，根据校正子产生定位多项式，并根据定位多项式确定输入数据单元中的数据位错误数。此外，数据校正系统选择搜索模块中的一个具有至少输入数据单元中的数据位错误数量的位错误容量。所选择的搜索模块基于定位多项式生成错误指示符。数据校正系统根据误差指示器校正输入数据单元中的每个数据位错误。

8. 发明授权

US07386774B1 Memory unit with controller managing memory access through JTAG and CPU interfaces 有权
标题翻译：带控制器的存储单元通过JTAG和CPU接口管理存储器访问
公开(公告)号：US07386774B1
公开(公告)日：2008-06-10
申请号：US10788943
申请日：2004-02-26
申请人： Mitrajit Chatterjee , Ming Tang , Peter Z. Onufryk , Steven Chau
发明人： Mitrajit Chatterjee , Ming Tang , Peter Z. Onufryk , Steven Chau
IPC分类号： G01R31/28
CPC分类号： G06F21/575 , G06F21/79 , G06F2221/2105
摘要： A memory unit includes a memory organized into protected and non-protected areas. A controller manages access to the memory so that the protected area can be written to through a JTAG or CPU interface. Once written to, the protected area is only accessible to particular logic and cannot be over-written until the entire memory is erased. The controller is configured to allow a BCV to be stored in the memory through either the JTAG or CPU interface. The controller is also configured to allow writing to the protected area and boot configuration vector in memory before CPU boot-up by using a JTAG clock signal provided through an external pin when a system clock signal is not available. A reset circuit generates one or more initialization signals using either the BCV from memory or another BCV provided on external BCV pins, depending upon whether another external BCV pin is asserted.
摘要翻译：存储器单元包括组织成受保护区域和非保护区域的存储器。控制器管理对存储器的访问，以便可以通过JTAG或CPU接口写保护区。一旦写入，保护区只能访问特定的逻辑，并且不能被覆盖，直到整个内存被擦除。控制器配置为允许通过JTAG或CPU接口将BCV存储在存储器中。控制器还配置为在系统时钟信号不可用时，通过使用通过外部引脚提供的JTAG时钟信号，在CPU启动之前，将写入保护区域并启动存储器中的配置向量。复位电路使用来自存储器的BCV或外部BCV引脚上提供的另一个BCV产生一个或多个初始化信号，这取决于是否断言另一个外部BCV引脚。

9. 发明授权

US06671742B1 Method and apparatus for unifield control and data event exchange in a software system 有权
标题翻译：用于软件系统中的单一控制和数据事件交换的方法和装置
公开(公告)号：US06671742B1
公开(公告)日：2003-12-30
申请号：US09548893
申请日：2000-04-13
申请人： Charles D. Cranor , Raman Gopalakrishnan , Peter Z. Onufryk
发明人： Charles D. Cranor , Raman Gopalakrishnan , Peter Z. Onufryk
IPC分类号： G06F946
CPC分类号： G06F9/544 , G06F9/542 , G06F9/546
摘要： An event exchange mechanism for software systems is disclosed that utilizes a receiver-driven, publisher-subscriber model to overcome various problems in the prior art. The event exchange has a flexible addressing scheme so that a sending module need not be aware of all of its receiving modules. Yet, the event exchange still provides the ability to multicast messages to interested receivers. The system is also uniform since both data and control information can be exchanged using the same mechanism. Mechanisms for flow control are also provided so that a receiver can exert backpressure on a sender; this is especially useful for the transfer of multimedia data.
摘要翻译：公开了一种用于软件系统的事件交换机制，其利用接收机驱动的发布者订户模型来克服现有技术中的各种问题。事件交换具有灵活的寻址方案，使得发送模块不需要知道其所有的接收模块。然而，事件交换仍然提供向感兴趣的接收者组播消息的能力。系统也是统一的，因为数据和控制信息可以使用相同的机制进行交换。还提供用于流量控制的机构，使得接收器可以在发送器上施加背压; 这对于传输多媒体数据尤其有用。

10. 发明授权

US08707122B1 Nonvolatile memory controller with two-stage error correction technique for enhanced reliability 有权
标题翻译：具有两级纠错技术的非易失性存储器控制器，增强可靠性
公开(公告)号：US08707122B1
公开(公告)日：2014-04-22
申请号：US13023336
申请日：2011-02-08
申请人： Rino Micheloni , Peter Z. Onufryk , Alessia Marelli , Christopher I. W. Norrie
发明人： Rino Micheloni , Peter Z. Onufryk , Alessia Marelli , Christopher I. W. Norrie
IPC分类号： H03M13/00
CPC分类号： H03M13/2915 , G06F11/1012 , G06F11/108 , H03M13/098 , H03M13/152
摘要： A nonvolatile memory controller generates an error correction code for each data unit in a data stripe and generates a parity unit based on the data units of the data stripe. If a data unit of the data stripe has a number of data bit errors not exceeding the error correction capacity of the nonvolatile memory controller, the nonvolatile memory controller corrects any data bit errors in the data unit based on the error correction code of the data unit. Otherwise, if a data unit of the data stripe has a number of data bit error exceeding the error correction capacity of the nonvolatile memory controller, the nonvolatile memory controller recovers the data unit based on the other data units of the data stripe and the parity unit.
摘要翻译：非易失性存储器控制器为数据条带中的每个数据单元生成纠错码，并且基于数据条带的数据单位生成奇偶校验单元。如果数据条带的数据单元具有不超过非易失性存储器控制器的纠错能力的多个数据位错误，则非易失性存储器控制器基于数据单元的纠错码来校正数据单元中的任何数据位错误。否则，如果数据条带的数据单元具有超过非易失性存储器控制器的纠错能力的数据位错误数，则非易失性存储器控制器基于数据条带和奇偶校验单元的其他数据单元来恢复数据单元。

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