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1. 发明授权

US07386774B1 Memory unit with controller managing memory access through JTAG and CPU interfaces 有权
标题翻译：带控制器的存储单元通过JTAG和CPU接口管理存储器访问
公开(公告)号：US07386774B1
公开(公告)日：2008-06-10
申请号：US10788943
申请日：2004-02-26
申请人： Mitrajit Chatterjee , Ming Tang , Peter Z. Onufryk , Steven Chau
发明人： Mitrajit Chatterjee , Ming Tang , Peter Z. Onufryk , Steven Chau
IPC分类号： G01R31/28
CPC分类号： G06F21/575 , G06F21/79 , G06F2221/2105
摘要： A memory unit includes a memory organized into protected and non-protected areas. A controller manages access to the memory so that the protected area can be written to through a JTAG or CPU interface. Once written to, the protected area is only accessible to particular logic and cannot be over-written until the entire memory is erased. The controller is configured to allow a BCV to be stored in the memory through either the JTAG or CPU interface. The controller is also configured to allow writing to the protected area and boot configuration vector in memory before CPU boot-up by using a JTAG clock signal provided through an external pin when a system clock signal is not available. A reset circuit generates one or more initialization signals using either the BCV from memory or another BCV provided on external BCV pins, depending upon whether another external BCV pin is asserted.
摘要翻译：存储器单元包括组织成受保护区域和非保护区域的存储器。控制器管理对存储器的访问，以便可以通过JTAG或CPU接口写保护区。一旦写入，保护区只能访问特定的逻辑，并且不能被覆盖，直到整个内存被擦除。控制器配置为允许通过JTAG或CPU接口将BCV存储在存储器中。控制器还配置为在系统时钟信号不可用时，通过使用通过外部引脚提供的JTAG时钟信号，在CPU启动之前，将写入保护区域并启动存储器中的配置向量。复位电路使用来自存储器的BCV或外部BCV引脚上提供的另一个BCV产生一个或多个初始化信号，这取决于是否断言另一个外部BCV引脚。

2. 发明授权

US06865638B1 Apparatus and method for transferring multi-byte words in a fly-by DMA operation 有权
标题翻译：用于通过DMA操作传输多字节字的装置和方法
公开(公告)号：US06865638B1
公开(公告)日：2005-03-08
申请号：US10107503
申请日：2002-03-27
申请人： Mitrajit Chatterjee
发明人： Mitrajit Chatterjee
IPC分类号： G06F1/00 , G06F13/28
CPC分类号： G06F13/28
摘要： An apparatus and method for transferring multi-byte words having arbitrary start and end byte addresses are described. Data transfers between a memory and a PCI-bus pass through a PCI-side aligner unit, PCI FIFO, Endian swap logic, and PCI-bus interface unit under the control of a PCI FIFO controller. The PCI-side aligner unit properly aligns the data while communicating data with the memory's bus on a word-at-a-time basis, and communicating data with the PCI FIFO managed on a byte-at-a-time basis synchronous with a clock signal provided by the memory's bus. The Endian swap logic properly orients the data in big or little Endian orientation. The PCI-bus interface unit communicates data with the PCI-bus on a word-at-a-time basis, and communicates data with the PCI FIFO managed on a byte-at-a-time basis synchronous with a clock signal provided by the PCI-bus. To keep track of unread stored data in the PCI FIFO, the PCI FIFO controller includes a #Bytes logic unit that automatically accounts for wrap-around of write and read pointers for the PCI FIFO.
摘要翻译：描述用于传送具有任意开始和结束字节地址的多字节字的装置和方法。存储器和PCI总线之间的数据传输通过PCI-FIFO对准器单元，PCI FIFO，端接交换逻辑和PCI总线接口单元，在PCI FIFO控制器的控制下。 PCI侧对准器单元正确地对准数据，同时基于字时与存储器总线通信数据，并且与时钟同步地以与时钟同步的方式来管理的PCI FIFO进行数据通信信号由存储器总线提供。端接交换逻辑适当地定位大或小的Endian方向的数据。 PCI总线接口单元以一个字为单位与PCI总线通信数据，并且与一个字节同时被管理的PCI FIFO通信数据同步于由该总线提供的时钟信号 PCI总线。为了跟踪PCI FIFO中未读存储的数据，PCI FIFO控制器包括一个#Bytes逻辑单元，可自动计算PCI FIFO的写入和读取指针的循环。

3. 发明授权

US08397197B1 Integrated circuit module time delay budgeting 有权
标题翻译：集成电路模块时间延迟预算
公开(公告)号：US08397197B1
公开(公告)日：2013-03-12
申请号：US13115858
申请日：2011-05-25
申请人： Mitrajit Chatterjee , Sandeep Badida
发明人： Mitrajit Chatterjee , Sandeep Badida
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/84
摘要： A circuit analysis tool is provided, enabled as computer software instructions, for budgeting time delays between integrated circuit (IC) modules. The instructions accept a command enabling an IC floor-plan including a first module and a second module. The first module includes a first circuit element having a signal output interface, and an output port. The second module includes an input port, and a second circuit element having a signal input interface. A command is accepted defining a maximum delay value, and a first delay value is estimated between the first circuit element signal output interface and the first module output port. A second delay value is estimated between the second circuit element signal input interface and the second module input port, and a third delay value is estimated between the first module output port and the second module input port. The first, second, and third delay values are summed, creating a time budget estimate. The time budget estimate is approved if it is less than the maximum delay value.
摘要翻译：提供电路分析工具，作为计算机软件指令，用于对集成电路（IC）模块之间的时间延迟进行预算。指令接受启用包括第一模块和第二模块的IC平面图的命令。第一模块包括具有信号输出接口的第一电路元件和输出端口。第二模块包括输入端口和具有信号输入接口的第二电路元件。接受定义最大延迟值的命令，并且在第一电路元件信号输出接口和第一模块输出端口之间估计第一延迟值。在第二电路元件信号输入接口和第二模块输入端口之间估计第二延迟值，并且在第一模块输出端口和第二模块输入端口之间估计第三延迟值。将第一，第二和第三延迟值相加，创建时间预算估计。如果小于最大延迟值，则批准时间预算估算值。

4. 发明授权

US07827555B2 Scheduler for a multiprocessing computing system 有权
标题翻译：多处理计算系统的调度程序
公开(公告)号：US07827555B2
公开(公告)日：2010-11-02
申请号：US11036938
申请日：2005-01-14
申请人： Mitrajit Chatterjee , Peter Zenon Onufryk , Inna Levit
发明人： Mitrajit Chatterjee , Peter Zenon Onufryk , Inna Levit
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F2209/5018
摘要： A system and method for scheduling a thread identifies runnable threads based on precycle signals determined before the scheduling cycle. The thread indexes of the runnable threads are grouped according to the thread priorities of the runnable threads, and the thread indexes are ranked within each group. The runnable threads that will be runnable in the next scheduling cycle are identified based on same cycle signals determined during the scheduling cycle. The highest ranked thread index of the runnable threads that will also be runnable in the next scheduling cycle is selected as the scheduled thread. In another configuration, a round robin ranking and a priority ranking are determined for the thread indexes. The thread indexes are then ranked according to the round robin ranking and the priority ranking and the highest ranked thread index of a runnable thread is selected as the scheduled thread.
摘要翻译：用于调度线程的系统和方法基于在调度周期之前确定的前周期信号来识别可运行线程。可运行线程的线程索引根据可运行线程的线程优先级进行分组，线程索引在每个组内进行排序。可以在下一个调度周期中运行的可运行线程基于在调度周期期间确定的相同周期信号来识别。选择在下一个调度周期中可运行的可运行线程的最高排名线程索引作为调度线程。在另一种配置中，为线程索引确定循环排序和优先级排序。然后根据轮询排序对线索索引进行排序，选择可运行线程的优先级排名和排名最高的线索，作为调度线程。

5. 发明申请

US20060059487A1 Scheduler for a multiprocessing computing system 有权
标题翻译：多处理计算系统的调度程序
公开(公告)号：US20060059487A1
公开(公告)日：2006-03-16
申请号：US11036938
申请日：2005-01-14
申请人： Mitrajit Chatterjee , Peter Onufryk , Inna Levit
发明人： Mitrajit Chatterjee , Peter Onufryk , Inna Levit
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F2209/5018
摘要： A system and method for scheduling a thread identifies runnable threads based on precycle signals determined before the scheduling cycle. The thread indexes of the runnable threads are grouped according to the thread priorities of the runnable threads, and the thread indexes are ranked within each group. The runnable threads that will be runnable in the next scheduling cycle are identified based on same cycle signals determined during the scheduling cycle. The highest ranked thread index of the runnable threads that will also be runnable in the next scheduling cycle is selected as the scheduled thread. In another configuration, a round robin ranking and a priority ranking are determined for the thread indexes. The thread indexes are then ranked according to the round robin ranking and the priority ranking and the highest ranked thread index of a runnable thread is selected as the scheduled thread.
摘要翻译：用于调度线程的系统和方法基于在调度周期之前确定的前周期信号来识别可运行线程。可运行线程的线程索引根据可运行线程的线程优先级进行分组，线程索引在每个组内进行排序。可以在下一个调度周期中运行的可运行线程基于在调度周期期间确定的相同周期信号来识别。选择在下一个调度周期中可运行的可运行线程的最高排名线程索引作为调度线程。在另一种配置中，为线程索引确定循环排序和优先级排序。然后根据轮询排序对线索索引进行排序，选择可运行线程的优先级排名和排名最高的线索，作为调度线程。

6. 发明申请

US20080072113A1 Method of locating packet for resend from retry buffer 审中-公开
标题翻译：定位数据包以重试从重试缓冲区的方法
公开(公告)号：US20080072113A1
公开(公告)日：2008-03-20
申请号：US11514281
申请日：2006-08-30
申请人： Siukwin Tsang , Mitrajit Chatterjee
发明人： Siukwin Tsang , Mitrajit Chatterjee
IPC分类号： H04L1/18 , G08C25/02
CPC分类号： H04L1/1874
摘要： In PCI-Express and alike network systems, back-up copies of recently sent packets are kept in a retry buffer for resending if the original packet is not well received by an intended destination device. A method for locating the back-up copy in the retry buffer comprises applying a less significant portion of the sequence number of a to-be-retrieved back-up copy to an index table to obtain a start address or other locater indicating where in the retry buffer the to-be-retrieved back-up copy resides.
摘要翻译：在PCI-Express和相似的网络系统中，如果原始分组未被预期的目的地设备良好接收，则最近发送的分组的备份副本被保留在重试缓冲器中以重新发送。用于在重试缓冲器中定位备份副本的方法包括将待检索的备份副本的序列号的较不重要的部分应用于索引表以获得起始地址或其他定位符，其指示在重试缓冲区要备份的备份副本。

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