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1. 发明申请

US20070057743A1 Analog varactor 有权
标题翻译：模拟变容二极管
公开(公告)号：US20070057743A1
公开(公告)日：2007-03-15
申请号：US11227421
申请日：2005-09-14
申请人： Peter Vancorenland , Lysander Lim , Augusto Marques , Scott Willingham
发明人： Peter Vancorenland , Lysander Lim , Augusto Marques , Scott Willingham
IPC分类号： H03B5/12
CPC分类号： H03J3/185 , H03B5/1243 , H03B5/1293 , H03B2200/0062 , H03B2201/0208 , H03B2201/0266 , H03J7/10 , H03J2200/36 , H03L7/099
摘要： An oscillator includes a plurality of varactor cells to receive a control signal to control a frequency of the oscillator. Each of the varactor cells includes a switch that includes a first terninal to receive the control signal and a second terminal such that the switch operates to control a capacitance of the varactor cell in response to a voltage between the first and second terminals. The oscillator includes a bias circuit to provide a different bias voltage to each second terminal and an amplifier that is coupled to the varactor cells to generate an oscillating signal.
摘要翻译：振荡器包括多个变容二极管单元，用于接收控制信号以控制振荡器的频率。每个变容二极管单元包括开关，该开关包括用于接收控制信号的第一三极管和第二端子，使得开关操作以响应于第一和第二端子之间的电压来控制变容二极管单元的电容。振荡器包括偏置电路，以向每个第二端子提供不同的偏置电压，以及耦合到变容二极管单元以产生振荡信号的放大器。

2. 发明申请

US20050212581A1 Radio frequency CMOS buffer circuit and method 失效
标题翻译：射频CMOS缓冲电路及方法
公开(公告)号：US20050212581A1
公开(公告)日：2005-09-29
申请号：US10809195
申请日：2004-03-25
申请人： Scott Willingham , Augusto Marques
发明人： Scott Willingham , Augusto Marques
IPC分类号： G02B6/26 , H03K19/0185
CPC分类号： H03K19/018571
摘要： A buffer (40) includes a capacitor (42) having a first terminal for receiving an input signal, and a second terminal; a first transistor (44) having a first current electrode for receiving a first power supply voltage, a control electrode coupled to the second terminal of the capacitor (42), and a second current electrode for providing an output signal of the buffer (40); and a second transistor (45) having a first current electrode coupled to the second current electrode of the first transistor (44), a control electrode coupled to the second terminal of the capacitor (42), and a second current electrode for receiving a second power supply voltage. A capacitance of the capacitor (42) is chosen to reduce a peak-to-peak voltage swing of the input signal such that a peak-to-peak voltage swing at the control electrodes of the first (44) and second (45) transistors is less than or equal to a difference between the first and second power supply voltages.
摘要翻译：缓冲器（40）包括具有用于接收输入信号的第一端子的电容器（42）和第二端子; 第一晶体管（44），具有用于接收第一电源电压的第一电流电极，耦合到电容器（42）的第二端子的控制电极和用于提供缓冲器（40）的输出信号的第二电流电极， ; 以及第二晶体管（45），其具有耦合到所述第一晶体管（44）的所述第二电流电极的第一电流电极，耦合到所述电容器（42）的所述第二端子的控制电极和用于接收第二晶体管电源电压。选择电容器（42）的电容以减小输入信号的峰 - 峰电压摆幅，使得在第一（44）和第（45）晶体管的控制电极处的峰 - 峰电压摆幅小于或等于第一和第二电源电压之间的差。

3. 发明申请

US20070001657A1 Supply regulator 失效
标题翻译：供应调节器
公开(公告)号：US20070001657A1
公开(公告)日：2007-01-04
申请号：US11273695
申请日：2005-11-14
申请人： Murthy Mellachurvu , Scott Willingham , Peter Vancorenland , G. Tuttle
发明人： Murthy Mellachurvu , Scott Willingham , Peter Vancorenland , G. Tuttle
IPC分类号： G05F1/00
CPC分类号： G05F1/575 , Y10S323/901
摘要： A technique includes using a first stored energy source to generate a reference signal to circuitry of a supply regulator in response to the regulator being in a startup state. The technique includes using an output signal that is provided by the regulator to generate the reference signal in response to the regulator not being in the startup state.
摘要翻译：一种技术包括使用第一存储能量源来响应于调节器处于启动状态而向电源调节器的电路产生参考信号。该技术包括使用由调节器提供的输出信号以响应于调节器不处于启动状态而产生参考信号。

4. 发明申请

US20060003728A1 Ratiometric clock systems for integrated receivers and associated methods 有权
标题翻译：用于集成接收机和相关方法的比例时钟系统
公开(公告)号：US20060003728A1
公开(公告)日：2006-01-05
申请号：US10880483
申请日：2004-06-30
申请人： G. Tuttle , David Welland , Scott Willingham
发明人： G. Tuttle , David Welland , Scott Willingham
IPC分类号： H04B1/28
CPC分类号： H04B1/30
摘要： A ratiometric clock system for an integrated receiver and associated method are disclosed that provide an advantageous solution for combining digital signal processing (DSP) circuitry on the same integrated circuit as mixer and local oscillator (LO) generation circuitry. The generation circuitry generates an oscillation signal that is passed through a first divider to generate mixing signals for the mixer and that is passed through a second divider to generate a digital clock signal that is utilized by the DSP circuitry. This digital clock signal can be utilized by integrated analog-to-digital conversion circuitry, as well.
摘要翻译：公开了一种用于集成接收机和相关方法的比例时钟系统，其提供用于将数字信号处理（DSP）电路组合在与混频器和本地振荡器（LO）生成电路相同的集成电路上的有利解决方案。产生电路产生振荡信号，该信号通过第一分频器以产生用于混频器的混频信号，并通过第二分频器产生由DSP电路利用的数字时钟信号。该数字时钟信号也可以由集成的模数转换电路使用。

5. 发明授权

US08374296B2 Output circuitry for minimizing spurious frequency content 有权
标题翻译：用于最小化杂散频率内容的输出电路
公开(公告)号：US08374296B2
公开(公告)日：2013-02-12
申请号：US12057988
申请日：2008-03-28
申请人： Peter J. Vancorenland , Scott Willingham , Mustafa Koroglu , Jing Li
发明人： Peter J. Vancorenland , Scott Willingham , Mustafa Koroglu , Jing Li
IPC分类号： H03D1/04 , H03D1/06 , H03K5/01 , H03K6/04 , H04B1/10 , H04L1/00 , H04L25/08
CPC分类号： H04B1/1646
摘要： A system including first voltage supply circuitry configured to provide a first voltage supply with spurious frequency content and second voltage supply circuitry configured to provide a second voltage supply without the spurious frequency content is provided. The system includes signal generation circuitry configured to generate a first digital signal using a clock signal and the first voltage supply and configured to cause the spurious frequency content on the first voltage supply and output circuitry configured to generate a second digital signal from the first digital signal synchronous with the clock signal using the second voltage supply.
摘要翻译：一种包括第一电压供应电路的系统，其被配置为提供具有杂散频率内容的第一电压电源，以及第二电压供应电路，其被配置为提供没有杂散频率内容的第二电压源。该系统包括信号产生电路，其被配置为使用时钟信号和第一电压电源产生第一数字信号，并且被配置为使第一电压电源和输出电路上的杂散频率内容被配置为从第一数字信号产生第二数字信号与使用第二电压源的时钟信号同步。

6. 发明申请

US20120183102A1 Receiver Circuits and Systems for Receiving Medium Wave and Short Wave Signals 审中-公开
标题翻译：用于接收中波和短波信号的接收器电路和系统
公开(公告)号：US20120183102A1
公开(公告)日：2012-07-19
申请号：US13007572
申请日：2011-01-14
申请人： Scott Willingham , Vivek Sarda
发明人： Scott Willingham , Vivek Sarda
IPC分类号： H04B1/16 , H04L27/06
CPC分类号： H01Q7/00 , G01S3/72 , H01Q1/243 , H01Q3/24 , H01Q7/08 , H04B1/1027 , H04B1/1638 , H04B1/18
摘要： A receiver includes a first terminal for receiving an RF signal having a frequency of less than approximately 60 MHz, a second terminal, and a receive path having an input coupled to the first terminal and an output for providing a demodulated RF signal. The receiver further includes a detector coupled to the receive path for detecting a signal parameter in the RF signal and a controller coupled to the detector and to the second terminal. The controller provides the multiplex signal in a tuning state to the second terminal to selectively provide one of a first RF signal and a second RF signal to the first terminal and to determine at least one of a first parameter of the first RF signal and a second parameter of the second RF signal. The controller provides the multiplex signal in an operating state based on the first parameter and the second parameter.
摘要翻译：接收机包括用于接收具有小于大约60MHz的频率的RF信号的第一终端，第二终端和具有耦合到第一终端的输入的接收路径和用于提供解调的RF信号的输出。接收器还包括耦合到接收路径的检测器，用于检测RF信号中的信号参数，耦合到检测器和耦合到第二终端的控制器。控制器将调谐状态的多路复用信号提供给第二终端，以选择性地向第一终端提供第一RF信号和第二RF信号中的一个，并确定第一RF信号的第一参数和第二RF信号中的至少一个第二RF信号的参数。控制器基于第一参数和第二参数在操作状态下提供多路复用信号。

7. 发明授权

US07587184B2 Controlling fine frequency changes in an oscillator 有权
标题翻译：控制振荡器的精细频率变化
公开(公告)号：US07587184B2
公开(公告)日：2009-09-08
申请号：US11259910
申请日：2005-10-27
申请人： Lawrence Der , Dana Taipale , Scott Willingham
发明人： Lawrence Der , Dana Taipale , Scott Willingham
IPC分类号： H04B1/18
CPC分类号： H03B5/32 , H03B2201/025 , H03D7/165 , H03J1/0008 , H03J2200/10
摘要： In one embodiment, the present invention includes a method for determining if a frequency control instruction would cause a first capacitor bank to reach a limit and adjusting the first capacitor bank in a first direction using a calibration value and adjusting a second capacitor bank in a second direction if the first capacitor bank would reach the limit. Furthermore, the calibration value may be calculated and stored in accordance with other embodiments. In such manner, small changes in capacitance and correspondingly small changes in frequency may be effected.
摘要翻译：在一个实施例中，本发明包括一种用于确定频率控制指令是否会使第一电容器组达到限制并且使用校准值在第一方向上调整第一电容器组并在第二电容器组中调整第二电容器组的方法方向如果第一个电容器组达到极限。此外，可以根据其他实施例来计算和存储校准值。以这种方式，可以实现电容的小的变化和相应的小的频率变化。

8. 发明申请

US20070001823A1 Controlling fine frequency changes in an oscillator 有权
标题翻译：控制振荡器的精细频率变化
公开(公告)号：US20070001823A1
公开(公告)日：2007-01-04
申请号：US11259910
申请日：2005-10-27
申请人： Lawrence Der , Dana Taipale , Scott Willingham
发明人： Lawrence Der , Dana Taipale , Scott Willingham
IPC分类号： G08B3/00
CPC分类号： H03B5/32 , H03B2201/025 , H03D7/165 , H03J1/0008 , H03J2200/10
摘要： In one embodiment, the present invention includes a method for determining if a frequency control instruction would cause a first capacitor bank to reach a limit and adjusting the first capacitor bank in a first direction using a calibration value and adjusting a second capacitor bank in a second direction if the first capacitor bank would reach the limit. Furthermore, the calibration value may be calculated and stored in accordance with other embodiments. In such manner, small changes in capacitance and correspondingly small changes in frequency may be effected.
摘要翻译：在一个实施例中，本发明包括一种用于确定频率控制指令是否会使第一电容器组达到限制并且使用校准值在第一方向上调整第一电容器组并在第二电容器组中调整第二电容器组的方法方向如果第一个电容器组达到极限。此外，可以根据其他实施例来计算和存储校准值。以这种方式，可以实现电容的小的变化和相应的小的频率变化。

9. 发明申请

US20050069056A1 Receiver including an oscillation circuit for generating an image rejection calibration tone 有权
标题翻译：接收机包括用于产生镜像抑制校准色调的振荡电路
公开(公告)号：US20050069056A1
公开(公告)日：2005-03-31
申请号：US10673905
申请日：2003-09-29
申请人： Scott Willingham
发明人： Scott Willingham
IPC分类号： H04B1/30 , H03D3/18
CPC分类号： H04B1/30 , H04B17/21
摘要： A receiver circuit includes an oscillator circuit configured to generate a calibration tone and a phase locked loop (PLL) reference signal. An output frequency of the VCO may be divided by respective amounts to derive a desired calibration tone frequency and a desired PLL reference signal frequency. In addition to the oscillator circuit, the receiver circuit may further include a phase locked circuit configured to generate a PLL output signal that is phase locked in relation to the PLL reference signal. During a calibration mode, a quadrature generator may be used to generate quadrature mixer local oscillator signals dependent upon the PLL output signal, and an in-phase/quadrature mixer may be used to mix the calibration tone with the quadrature mixer LO signals.
摘要翻译：接收器电路包括被配置为产生校准音调和锁相环（PLL）参考信号的振荡器电路。可以将VCO的输出频率除以相应的量，以导出期望的校准音频率和期望的PLL参考信号频率。除了振荡器电路之外，接收器电路还可以包括被配置为产生相对于PLL参考信号锁相的PLL输出信号的锁相电路。在校准模式期间，可以使用正交发生器来产生取决于PLL输出信号的正交混频器本地振荡器信号，并且可以使用同相/正交混频器将校准音调与正交混频器LO信号混合。

10. 发明授权

US08306491B2 Controlling fine frequency changes in an oscillator 有权
标题翻译：控制振荡器的精细频率变化
公开(公告)号：US08306491B2
公开(公告)日：2012-11-06
申请号：US12504874
申请日：2009-07-17
申请人： Lawrence Der , Dana Taipale , Scott Willingham
发明人： Lawrence Der , Dana Taipale , Scott Willingham
IPC分类号： H04B1/18
CPC分类号： H03B5/32 , H03B2201/025 , H03D7/165 , H03J1/0008 , H03J2200/10
摘要： In one embodiment, the present invention includes a method for determining if a frequency control instruction would cause a first capacitor bank to reach a limit and adjusting the first capacitor bank in a first direction using a calibration value and adjusting a second capacitor bank in a second direction if the first capacitor bank would reach the limit. Furthermore, the calibration value may be calculated and stored in accordance with other embodiments. In such manner, small changes in capacitance and correspondingly small changes in frequency may be effected.
摘要翻译：在一个实施例中，本发明包括一种用于确定频率控制指令是否会使第一电容器组达到限制并且使用校准值在第一方向上调整第一电容器组并在第二电容器组中调整第二电容器组的方法方向如果第一个电容器组达到极限。此外，可以根据其他实施例来计算和存储校准值。以这种方式，可以实现电容的小的变化和相应的小的频率变化。

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