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1. 发明申请

US20080008259A1 Ratiometric clock systems for integrated receivers and associated methods 有权
标题翻译：用于集成接收机和相关方法的比例时钟系统
公开(公告)号：US20080008259A1
公开(公告)日：2008-01-10
申请号：US11900957
申请日：2007-09-14
申请人： G. Tuttle , David Welland , Scott Willingham
发明人： G. Tuttle , David Welland , Scott Willingham
IPC分类号： H04L7/027
CPC分类号： H04B1/30
摘要： A ratiometric clock system for an integrated receiver and associated method are disclosed that provide an advantageous solution for combining digital signal processing (DSP) circuitry on the same integrated circuit as mixer and local oscillator (LO) generation circuitry. The generation circuitry generates an oscillation signal that is passed through a first divider to generate mixing signals for the mixer and that is passed through a second divider to generate a digital clock signal that is utilized by the DSP circuitry. This digital clock signal can be utilized by integrated analog-to-digital conversion circuitry, as well.
摘要翻译：公开了一种用于集成接收机和相关方法的比例时钟系统，其提供用于将数字信号处理（DSP）电路组合在与混频器和本地振荡器（LO）生成电路相同的集成电路上的有利解决方案。产生电路产生振荡信号，该信号通过第一分频器以产生用于混频器的混频信号，并通过第二分频器产生由DSP电路利用的数字时钟信号。该数字时钟信号也可以由集成的模数转换电路使用。

2. 发明申请

US20060003728A1 Ratiometric clock systems for integrated receivers and associated methods 有权
标题翻译：用于集成接收机和相关方法的比例时钟系统
公开(公告)号：US20060003728A1
公开(公告)日：2006-01-05
申请号：US10880483
申请日：2004-06-30
申请人： G. Tuttle , David Welland , Scott Willingham
发明人： G. Tuttle , David Welland , Scott Willingham
IPC分类号： H04B1/28
CPC分类号： H04B1/30
摘要： A ratiometric clock system for an integrated receiver and associated method are disclosed that provide an advantageous solution for combining digital signal processing (DSP) circuitry on the same integrated circuit as mixer and local oscillator (LO) generation circuitry. The generation circuitry generates an oscillation signal that is passed through a first divider to generate mixing signals for the mixer and that is passed through a second divider to generate a digital clock signal that is utilized by the DSP circuitry. This digital clock signal can be utilized by integrated analog-to-digital conversion circuitry, as well.
摘要翻译：公开了一种用于集成接收机和相关方法的比例时钟系统，其提供用于将数字信号处理（DSP）电路组合在与混频器和本地振荡器（LO）生成电路相同的集成电路上的有利解决方案。产生电路产生振荡信号，该信号通过第一分频器以产生用于混频器的混频信号，并通过第二分频器产生由DSP电路利用的数字时钟信号。该数字时钟信号也可以由集成的模数转换电路使用。

3. 发明申请

US20070072558A1 Digital variable gain mixer 有权
标题翻译：数字可变增益混频器
公开(公告)号：US20070072558A1
公开(公告)日：2007-03-29
申请号：US11394249
申请日：2006-03-30
申请人： Srinath Sridharan , Ahmed Emira , Aria Eshraghi , David Welland
发明人： Srinath Sridharan , Ahmed Emira , Aria Eshraghi , David Welland
IPC分类号： H01Q11/12 , H04B1/04
CPC分类号： H04B1/0475
摘要： A method includes controlling a mixer gain to provide a range of selected power output levels from the mixer using a first control scheme for a low portion of the range and using a second control scheme for a high portion of the range. Using the selected mixer gain, incoming baseband signals may be upconverted in the mixer to a transmission frequency and output from the mixer at the selected power output level.
摘要翻译：一种方法包括：控制混频器增益，以使用第一控制方案从该混频器提供所选择的功率输出电平的范围，并对该范围的高部分使用第二控制方案。使用所选择的混频器增益，输入基带信号可以在混频器中上变频到传输频率，并在所选功率输出电平下从混频器输出。

4. 发明申请

US20060215771A1 Direct digital access arrangement circuitry and method for connecting to phone lines 失效
公开(公告)号：US20060215771A1
公开(公告)日：2006-09-28
申请号：US11398090
申请日：2006-04-05
申请人： Jeffrey Scott , Navdeep Sooch , David Welland
发明人： Jeffrey Scott , Navdeep Sooch , David Welland
IPC分类号： H04L25/00
CPC分类号： H04M1/573 , H04L7/033 , H04L25/0266 , H04L25/06 , H04M1/76 , H04M3/007 , H04M11/06 , H04M19/001 , H04M19/02
摘要： An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier. Finally, a bidirectional isolation system is provided whereby bidirectional communication of digital signals is accomplished using a single pair of isolation capacitors. In preferred embodiments, the digital data communicated across the barrier consists of digital delta-sigma data signals multiplexed in time with other digital control, signaling and framing information.

5. 发明申请

US20070071129A1 Edge transceiver architecture and related methods 有权
标题翻译：边缘收发器架构及相关方法
公开(公告)号：US20070071129A1
公开(公告)日：2007-03-29
申请号：US11510339
申请日：2006-08-25
申请人： David Welland
发明人： David Welland
IPC分类号： H04L27/20
CPC分类号： H04L27/0008 , H04B1/04
摘要： In one embodiment, the present invention includes an apparatus having multiple transmission paths, including a first transmission path configured to receive and process baseband data in a first mode of operation to generate a radio frequency (RF) signal for output via a common output path, and a second transmission path configured to receive and process the baseband data in a second mode of operation to generate the RF signal for output via the common output path.
摘要翻译：在一个实施例中，本发明包括具有多个传输路径的设备，包括：第一传输路径，其被配置为在第一操作模式中接收和处理基带数据，以产生用于经由公共输出路径输出的射频（RF）信号; 以及第二传输路径，其被配置为在第二操作模式中接收和处理所述基带数据，以产生所述RF信号以经由所述公共输出路径输出。

6. 发明申请

US20060008075A1 Direct digital access arrangement circuitry and method for connecting DSL circuitry to phone lines 审中-公开
标题翻译：用于将DSL电路连接到电话线的直接数字接入安排电路和方法
公开(公告)号：US20060008075A1
公开(公告)日：2006-01-12
申请号：US10886373
申请日：2004-07-07
申请人： Jeffrey Scott , Navdeep Sooch , David Welland
发明人： Jeffrey Scott , Navdeep Sooch , David Welland
IPC分类号： H04M1/00
CPC分类号： H04M1/738 , H04M11/062
摘要： An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier. A bidirectional isolation system is provided whereby bidirectional communication of digital signals is accomplished using a single pair of isolation capacitors. In preferred embodiments, the digital data communicated across the barrier consists of digital delta-sigma data signals multiplexed in time with other digital control, signaling and framing information. Finally, the isolation system may include a pulse transformer to accommodate ADSL circuitry, whereby power is transmitted through the pulse transformer.
摘要翻译：提供了一种适用于电话，医疗仪器，工业过程控制和其他应用的隔离系统。本发明的优选实施例包括电容隔离屏障，通过数字信号传送数字信号。该系统提供跨越隔离屏障的通信手段，其高度免疫幅度和相位噪声干扰。可以在隔离屏障的一侧采用时钟恢复电路，从跨屏障通信的数字信号提取定时信息，并且滤除在屏障处引入的相位噪声的影响。 Δ-Σ转换器可以设置在隔离屏障的两侧以在模拟和数字域之间转换信号。隔离电源也可以设置在屏障的隔离侧上，由此响应于穿过隔离屏障接收的数字数据产生直流电流。提供了双向隔离系统，由此使用单对隔离电容器实现数字信号的双向通信。在优选实施例中，跨屏障通信的数字数据由与其他数字控制，信令和成帧信息在时间上多路复用的数字delta-sigma数据信号组成。最后，隔离系统可以包括用于容纳ADSL电路的脉冲变压器，由此通过脉冲变压器传输功率。

7. 发明申请

US20060003706A1 Ratiometric transmit path architecture for communication systems 有权
标题翻译：通信系统的比例传输路径架构
公开(公告)号：US20060003706A1
公开(公告)日：2006-01-05
申请号：US11096133
申请日：2005-03-31
申请人： David Welland , Caiyi Wang
发明人： David Welland , Caiyi Wang
IPC分类号： H04B1/40 , H04B1/02 , H01Q11/12 , H04B1/66
CPC分类号： H04B1/403
摘要： A ratiometric transmit path architecture for communication systems and related methods are disclosed. This ratiometric transmit path architecture utilizes a single local oscillator signal and dividers to provide mixing signals for intermediate frequency (IF) mixing circuitry and feedback mixing circuitry, thereby eliminating the need for separate IF and radio frequency (RF) voltage controlled oscillators (VCOs) in prior solutions.
摘要翻译：公开了用于通信系统和相关方法的比例传输路径架构。这种比例传输路径架构利用单个本地振荡器信号和分频器来为中频（IF）混频电路和反馈混频电路提供混频信号，从而消除对单独的IF和射频（RF）压控振荡器（VCO）的需要以前的解决方案。

8. 发明授权

US07720176B2 Edge transceiver architecture and related methods 有权
标题翻译：边缘收发器架构及相关方法
公开(公告)号：US07720176B2
公开(公告)日：2010-05-18
申请号：US11510339
申请日：2006-08-25
申请人： David Welland
发明人： David Welland
IPC分类号： H04L27/12
CPC分类号： H04L27/0008 , H04B1/04
摘要： In one embodiment, the present invention includes an apparatus having multiple transmission paths, including a first transmission path configured to receive and process baseband data in a first mode of operation to generate a radio frequency (RF) signal for output via a common output path, and a second transmission path configured to receive and process the baseband data in a second mode of operation to generate the RF signal for output via the common output path.
摘要翻译：在一个实施例中，本发明包括具有多个传输路径的设备，包括：第一传输路径，其被配置为在第一操作模式中接收和处理基带数据，以产生用于经由公共输出路径输出的射频（RF）信号; 以及第二传输路径，其被配置为在第二操作模式中接收和处理所述基带数据，以产生所述RF信号以经由所述公共输出路径输出。

9. 发明申请

US20060284746A1 DIGITAL EXPANDER FOR GENERATING MULTIPLE ANALOG CONTROL SIGNALS PARTICULARLY USEFUL FOR CONTROLLING AN OSCILLATOR 有权
标题翻译：用于产生多个模拟控制信号的数字扩展器特别适用于控制振荡器
公开(公告)号：US20060284746A1
公开(公告)日：2006-12-21
申请号：US11461408
申请日：2006-07-31
申请人： Yunteng Huang , Bruno Garlepp , David Welland
发明人： Yunteng Huang , Bruno Garlepp , David Welland
IPC分类号： H03M7/00
CPC分类号： H03L7/093 , H03J2200/10 , H03L7/099 , H03L7/10 , H03L2207/06 , H03M7/3011 , H03M7/3028 , H03M7/3037
摘要： An exemplary PLL circuit includes a VCO responsive to a plurality of sub-varactor control signals. A digital loop filter for the PLL digitally generates a varactor control word, which is digitally expanded into a plurality of digital values, each of which is conveyed to a corresponding one of a plurality of DACs. A multiplexer is configured to respectively convey the DAC output signals to a group of sub-varactor control signals according to the varactor control word, and to drive remaining sub-varactor control signals to either the full-scale high value or the full-scale low value of the DAC outputs. Each of the DACs preferably includes a hybrid first order/second order sigma-delta modulator, and in certain embodiments, a NRZ-to-RZ coder circuit, and a linear filter circuit.
摘要翻译：示例性PLL电路包括响应于多个子变容二极管控制信号的VCO。用于PLL的数字环路滤波器数字地生成变容二极管控制字，其被数字地扩展成多个数字值，每个数字值被传送到多个DAC中的对应的一个。复用器被配置为根据变容二极管控制字将DAC输出信号分别传送到一组子变容二极管控制信号，并且将剩余的子变容二极管控制信号驱动到满量程高值或满量程低 DAC输出的值。每个DAC优选地包括混合一阶/二阶Σ-Δ调制器，并且在某些实施例中，NRZ至RZ编码器电路和线性滤波器电路。

10. 发明申请

US20060197847A1 Image processor circuits, systems, and methods 有权
公开(公告)号：US20060197847A1
公开(公告)日：2006-09-07
申请号：US11415000
申请日：2006-05-01
申请人： Sandra Johnson , Shih-Chung Chao , Nadi Itani , Caiyi Wang , Brannon Harris , Ash Prabala , Douglas Holberg , Alan Hansford , Syed Azim , David Welland
发明人： Sandra Johnson , Shih-Chung Chao , Nadi Itani , Caiyi Wang , Brannon Harris , Ash Prabala , Douglas Holberg , Alan Hansford , Syed Azim , David Welland
IPC分类号： H04N5/235
CPC分类号： H04N5/3575 , H04N5/335 , H04N5/361
摘要： An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample and variable gain (CDSVGA) circuit for receiving data from a CCD system and an automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit AND a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC. The processing circuitry includes an analog front end and a digital signal processing system for capturing full motion video and outputting a CCIR 601 4:2:2 YCrCb video data output for presentation on a user selected display.

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