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1. 发明授权

US06178493B1 Multiprocessor stalled store detection 失效
标题翻译：多处理器停止存储检测
公开(公告)号：US06178493B1
公开(公告)日：2001-01-23
申请号：US09026088
申请日：1998-02-19
申请人： Peter Steven Lenk , Michael J. Mayfield , Robert James Reese , Michael Thomas Vaden
发明人： Peter Steven Lenk , Michael J. Mayfield , Robert James Reese , Michael Thomas Vaden
IPC分类号： G06F1500
CPC分类号： G06F9/524
摘要： In a multiprocessor system, when a store request has stalled, a signal is generated and sent to all processors indicating such a stalled store situation. In response, all processors will postpone the sending of load, or read, requests to memory until the stalled store request has completed.
摘要翻译：在多处理器系统中，当存储请求停止时，产生信号并将其发送到所有处理器，指示这种停顿的存储情况。作为响应，所有处理器将推迟发送加载或读取请求到内存，直到停滞的存储请求完成。

2. 发明授权

US5740399A Modified L1/L2 cache inclusion for aggressive prefetch 失效
标题翻译：修改的L1 / L2缓存包含用于积极预取
公开(公告)号：US5740399A
公开(公告)日：1998-04-14
申请号：US518348
申请日：1995-08-23
申请人： Michael John Mayfield , Trinh Huy Nguyen , Robert James Reese , Michael Thomas Vaden
发明人： Michael John Mayfield , Trinh Huy Nguyen , Robert James Reese , Michael Thomas Vaden
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0897
摘要： Within a data processing system implementing L1 and L2 caches and stream filters and buffers, prefetching of cache lines is performed in a progressive manner. In one mode, data may not be prefetched. In a second mode, two cache lines are prefetched wherein one line is prefetched into the L1 cache and the next line is prefetched into a stream buffer. In a third mode, more than two cache lines are prefetched at a time. In the third mode cache lines may be prefetched to the L1 cache and not the L2 cache, resulting in no inclusion between the L1 and L2 caches.
摘要翻译：在实现L1和L2高速缓存以及流过滤器和缓冲器的数据处理系统内，以渐进方式执行高速缓存行的预取。在一种模式下，数据可能不被预取。在第二模式中，预取两条高速缓存线，其中一行被预取到L1高速缓存中，并且下一行被预取到流缓冲器中。在第三种模式下，一次预取多于两条的高速缓存行。在第三模式中，高速缓存行可以被预取到L1高速缓存，而不是L2缓存，导致L1和L2高速缓存之间不包括。

3. 发明授权

US5758119A System and method for indicating that a processor has prefetched data into a primary cache and not into a secondary cache 失效
标题翻译：用于指示处理器将数据预取到主高速缓存而不是进入二级高速缓存的系统和方法
公开(公告)号：US5758119A
公开(公告)日：1998-05-26
申请号：US518347
申请日：1995-08-23
申请人： Michael John Mayfield , Trinh Huy Nguyen , Robert James Reese , Michael Thomas Vaden
发明人： Michael John Mayfield , Trinh Huy Nguyen , Robert James Reese , Michael Thomas Vaden
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0897
摘要： Within a data processing system implementing L1 and L2 caches and stream filters and buffers, prefetching of cache lines is performed in a progressive manner. In one mode, data may not be prefetched. In a second mode, two cache lines are prefetched wherein one line is prefetched into the L1 cache and the next line is prefetched into a stream buffer. In a third mode, more than two cache lines are prefetched at a time. In the third mode cache lines may be prefetched to the L1 cache and not the L2 cache, resulting in no inclusion between the L1 and L2 caches. A directory field entry provides an indication of whether or not a particular cache line in the L1 cache is also included in the L2 cache.
摘要翻译：在实现L1和L2高速缓存以及流过滤器和缓冲器的数据处理系统内，以渐进方式执行高速缓存行的预取。在一种模式下，数据可能不被预取。在第二模式中，预取两条高速缓存线，其中一行被预取到L1高速缓存中，并且下一行被预取到流缓冲器中。在第三种模式下，一次预取多于两条的高速缓存行。在第三模式中，高速缓存行可以被预取到L1高速缓存，而不是L2缓存，导致L1和L2高速缓存之间不包括。目录字段条目提供L1高速缓存中的特定高速缓存行是否也包括在L2高速缓存中的指示。

4. 发明授权

US07362697B2 Self-healing chip-to-chip interface 失效
标题翻译：自愈芯片到芯片的接口
公开(公告)号：US07362697B2
公开(公告)日：2008-04-22
申请号：US10339757
申请日：2003-01-09
申请人： Wiren Dale Becker , Daniel Mark Dreps , Frank David Ferraiolo , Anand Haridass , Robert James Reese
发明人： Wiren Dale Becker , Daniel Mark Dreps , Frank David Ferraiolo , Anand Haridass , Robert James Reese
IPC分类号： G01R31/08
CPC分类号： H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.
摘要翻译：一种用于管理用于芯片的一组信号路径的方法，装置和计算机指令。检测用于芯片的信号路径集合内的有缺陷的信号路径。信号通过一组信号路径重新路由，使得有缺陷的信号路径从信号路径集合中移除，并使用信号路径组中的剩余数据信号路径发送信号，并且响应于检测到的信号路径有缺陷的信号路径。

5. 发明授权

US5793986A Method and system for enhanced efficiency of data transfers from memory to multiple processors in a data processing system 失效
标题翻译：用于提高数据处理系统中从存储器到多个处理器的数据传输效率的方法和系统
公开(公告)号：US5793986A
公开(公告)日：1998-08-11
申请号：US551396
申请日：1995-11-01
申请人： Michael Scott Allen , Charles Roberts Moore , Robert James Reese
发明人： Michael Scott Allen , Charles Roberts Moore , Robert James Reese
IPC分类号： G06F15/16 , G06F12/08 , G06F15/177 , G06F13/00
CPC分类号： G06F12/0831
摘要： A method and system for the enhanced efficiency of data transfers from memory to multiple processors in a data processing system. Each of the multiple processors has an associated buffer for storing data transferred via a common bus which couples the processors and memory together. Each of the multiple processors continually monitors the common bus and is capable of asserting a selected control signal in response to an attempted activity of another one of the multiple processors which would violate data coherency within the data processing system during a particular period of time following the attempted activity. Data is transferred from memory to a buffer associated with one of the multiple processors and stored in the buffer in response to a request from the processor associated with the buffer prior to expiration of the particular period of time and prior to a determination of whether or not this transfer will result in a possible data coherency problem. The common bus is continually monitored during the particular period of time. Transfer of the data from the buffer to the processor is prohibited in response to a presence on the common bus of the selected control signal prior to expiration of the particular of time. Transfer of the data from the buffer to the processor is permitted in response to an absence on the common bus of the selected control signal.
摘要翻译：一种用于在数据处理系统中从存储器到多个处理器的数据传输的增强效率的方法和系统。多个处理器中的每一个具有用于存储经由公共总线传送的数据的相关联的缓冲器，该公共总线将处理器和存储器耦合在一起。多个处理器中的每一个持续地监视公共总线，并且能够响应于多个处理器中的另一个处理器的尝试的活动来断言所选择的控制信号，这将在数据处理系统中的特定时间段内违反数据一致性尝试活动。数据从存储器传送到与多个处理器中的一个处理器相关联的缓冲器，并且响应于在特定时间段到期之前和在确定之前的处理器与缓冲器相关联的处理器的请求而被存储在缓冲器中这种传输将导致可能的数据一致性问题。公共巴士在特定时期内不断监控。响应于在特定时间到期之前在公共总线上存在所选择的控制信号，禁止将数据从缓冲器传送到处理器。响应于所选控制信号的公共总线上的不存在，允许将数据从缓冲器传送到处理器。

6. 发明授权

US5706464A Method and system for achieving atomic memory references in a multilevel cache data processing system 失效
标题翻译：用于在多级缓存数据处理系统中实现原子存储器引用的方法和系统
公开(公告)号：US5706464A
公开(公告)日：1998-01-06
申请号：US608978
申请日：1996-02-29
申请人： Charles Roberts Moore , John Stephen Muhich , Robert James Reese
发明人： Charles Roberts Moore , John Stephen Muhich , Robert James Reese
IPC分类号： G06F15/16 , G06F12/08 , G06F15/177 , G06F12/12
CPC分类号： G06F12/0811
摘要： Atomic memory references require a data processing system to present the appearance of a coherent memory system, which may be achieved in most multiprocessor systems by means of normal memory coherency systems. Writes or attempted writes to memory must be monitored by a processor in order to correctly resolve hits against the reservation state. In a two level cache system the second level cache filters bus operations and forwards to the processor any bus traffic that may involve data stored within the first level cache. This may be accomplished by enforcing an "inclusion" property wherein all data entries within the first level cache are required to be maintained within higher level caches. A problem arises when a block within a first level cache which has had a reservation pending is cast out and the second level cache no longer forwards bus traffic to the associated processor, despite the continued pendency of the reservation. This problem is avoided by setting a reservation flag each time a valid reservation is pending. Thereafter, any replacement of a data entry in a higher level cache results in the automatic deletion of the corresponding data entry within any included level of cache. The reservation flag is then reset in response to the occurrence of either a bus operation which affects the reservation address or the deletion of the cache data entry corresponding to the reservation address, permitting atomic memory references to be achieved without the necessity of distributing the reservation address.
摘要翻译：原子存储器引用要求数据处理系统呈现一个相干存储器系统的外观，这可以通过一般存储器一致性系统在大多数多处理器系统中实现。对存储器的写入或尝试写入必须由处理器监视，以便正确地解决针对预留状态的命中。在二级高速缓存系统中，第二级缓存过滤总线操作并向处理器转发可能涉及存储在第一级高速缓存内的数据的任何总线流量。这可以通过实施“包含”属性来实现，其中第一级高速缓存中的所有数据条目需要被保持在更高级别的高速缓存中。当具有预留待处理的第一级高速缓冲存储器中的块被抛弃并且尽管保留的持续性仍然存在时，第二级高速缓存不再将总线流量转发到相关联的处理器。每当一个有效的保留待定时，设置一个保留标志来避免这个问题。此后，任何替换较高级别高速缓存中的数据条目导致在任何包含的高速缓存级别内自动删除相应的数据条目。响应于影响预约地址的总线操作的发生或与预约地址相对应的高速缓存数据条目的删除，保留标志被复位，从而允许实现原子存储器引用而不需要分发预留地址。

7. 发明授权

US06735543B2 Method and apparatus for testing, characterizing and tuning a chip interface 失效
标题翻译：用于测试，表征和调整芯片接口的方法和装置
公开(公告)号：US06735543B2
公开(公告)日：2004-05-11
申请号：US09996839
申请日：2001-11-29
申请人： Steven Michael Douskey , Daniel Mark Dreps , Frank David Ferraiolo , Curtis Walter Preuss , Robert James Reese , Paul William Rudrud , James Donald Ryan , Robert Russell Williams
发明人： Steven Michael Douskey , Daniel Mark Dreps , Frank David Ferraiolo , Curtis Walter Preuss , Robert James Reese , Paul William Rudrud , James Donald Ryan , Robert Russell Williams
IPC分类号： G06F1900
CPC分类号： G01R31/31813 , G01R31/318385
摘要： An inter-chip line transmission circuit in a transmitting chip and complementary receiving circuit in a receiving chip provide the capability to characterize the inter-chip interface by separately generating identical pseudo-random test data at both chips, comparing the data, and recording errors. Preferably, one or both chips can be tuned on an individual line basis to reduce errors by altering threshold detection voltage, signal delay, and/or driver power. The receiver circuit preferably contains counters for counting test cycles and errors, which can be masked for any particular line or type of error. A tunable and characterizable interface in accordance with the preferred embodiment thus supports the accurate determination of low error rates on an individual line basis for various tuning parameter settings.
摘要翻译：传输芯片中的芯片间线路传输电路和接收芯片中的互补接收电路通过在两个芯片上分别产生相同的伪随机测试数据，比较数据和记录错误，提供表征芯片间接口的能力。优选地，可以在单独的线路基础上调整一个或两个芯片以通过改变阈值检测电压，信号延迟和/或驱动器功率来减少误差。接收机电路优选地包含用于对测试周期和错误进行计数的计数器，其可以针对任何特定线路或类型的错误被屏蔽。因此，根据优选实施例的可调谐和可表征的接口因此支持针对各种调谐参数设置在各个线路上准确地确定低错误率。

8. 发明授权

US06243776B1 Selectable differential or single-ended mode bus 失效
标题翻译：可选差分或单端模式总线
公开(公告)号：US06243776B1
公开(公告)日：2001-06-05
申请号：US09114116
申请日：1998-07-13
申请人： George McNeil Lattimore , Robert James Reese , Gus Wai-Yan Yeung
发明人： George McNeil Lattimore , Robert James Reese , Gus Wai-Yan Yeung
IPC分类号： G06F1300
CPC分类号： G06F13/4072
摘要： A bus may be configured as either a single-ended mode bus or as a differential mode bus, depending on the system environment. The bus is configured in such a way that additional lines are not required, and so that substantially the same circuitry may be used for either single-ended mode or differential mode. Further, a selectable-mode driver may be connected to a non-selectable mode receiver, and vice versa. The invention may be implemented as a selectable driver, a selectable receiver, or a selectable driver/receiver pair. The apparatus and method of the present invention apply to both uni-directional and bi-directional bus implementations. The invention uses the same bus lines (i.e. wires) and substantially the same circuitry for both single-ended and differential modes of operation. When operating in single-ended mode, the data width of the bus is twice the data width as when operating in differential mode.
摘要翻译：根据系统环境，总线可以配置为单端模式总线或差分模式总线。总线被配置为不需要额外的线路，并且因此基本上相同的电路可以用于单端模式或差分模式。此外，可选模式驱动器可以连接到不可选模式的接收器，反之亦然。本发明可以被实现为可选择的驱动器，可选接收器或可选择的驱动器/接收器对。本发明的装置和方法适用于单向和双向总线实现。本发明使用相同的总线（即电线）和用于单端和差模操作模式的基本相同的电路。当在单端模式下工作时，总线的数据宽度是在差分模式下工作时的数据宽度的两倍。

9. 发明申请

US20110010482A1 Self-Healing Chip-to-Chip Interface 失效
标题翻译：自我修复芯片到芯片接口
公开(公告)号：US20110010482A1
公开(公告)日：2011-01-13
申请号：US12886404
申请日：2010-09-20
申请人： Wiren Dale Becker , Daniel Mark Dreps , Frank David Ferraiolo , Anand Haridass , Robert James Reese
发明人： Wiren Dale Becker , Daniel Mark Dreps , Frank David Ferraiolo , Anand Haridass , Robert James Reese
IPC分类号： G06F13/00
CPC分类号： H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.
摘要翻译：一种用于管理用于芯片的一组信号路径的方法，装置和计算机指令。检测用于芯片的信号路径集合内的有缺陷的信号路径。信号通过一组信号路径重新路由，使得有缺陷的信号路径从信号路径集合中移除，并使用信号路径组中的剩余数据信号路径发送信号，并且响应于检测到的信号路径有缺陷的信号路径。

10. 发明授权

US07813266B2 Self-healing chip-to-chip interface 有权
标题翻译：自愈芯片到芯片的接口
公开(公告)号：US07813266B2
公开(公告)日：2010-10-12
申请号：US11948620
申请日：2007-11-30
申请人： Wiren Dale Becker , Daniel Mark Dreps , Frank David Ferraiolo , Anand Haridass , Robert James Reese
发明人： Wiren Dale Becker , Daniel Mark Dreps , Frank David Ferraiolo , Anand Haridass , Robert James Reese
IPC分类号： G01R31/08
CPC分类号： H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.
摘要翻译：一种用于管理用于芯片的一组信号路径的方法，装置和计算机指令。检测用于芯片的信号路径集合内的有缺陷的信号路径。信号通过一组信号路径重新路由，使得有缺陷的信号路径从信号路径集合中移除，并使用信号路径组中的剩余数据信号路径发送信号，并且响应于检测到的信号路径有缺陷的信号路径。

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