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1. 发明授权

US07687343B2 Storage capacitor, a memory device and a method of manufacturing the same 有权
标题翻译：存储电容器，存储器件及其制造方法
公开(公告)号：US07687343B2
公开(公告)日：2010-03-30
申请号：US11633090
申请日：2006-12-04
申请人： Peter Moll , Peter Baars , Till Schloesser , Rolf Weis , Klaus Muemmler
发明人： Peter Moll , Peter Baars , Till Schloesser , Rolf Weis , Klaus Muemmler
IPC分类号： H01L21/8242
CPC分类号： H01L28/90 , H01L27/10814 , H01L27/10852 , H01L27/10894 , H01L27/10897
摘要： A storage capacitor includes a first capacitor portion and a second capacitor portion, the second capacitor portion being disposed above the first capacitor portion, thereby defining a first direction. The first and the second portions each include a hollow body made of a conductive material, respectively, thereby forming a first capacitor electrode. An upper diameter of each of the hollow bodies is larger than a lower diameter of the hollow body, the diameter being measured perpendicularly with respect to the first direction. The storage capacitor also includes a second capacitor electrode and a dielectric material disposed between the first and the second capacitor electrodes. The storage capacitor also includes an insulating material disposed outside the hollow bodies, and a layer of an insulating material. A lower side of the insulating layer is disposed at a height of an upper side of the first capacitor portion.
摘要翻译：存储电容器包括第一电容器部分和第二电容器部分，第二电容器部分设置在第一电容器部分上方，从而限定第一方向。第一和第二部分分别包括由导电材料制成的中空体，从而形成第一电容器电极。每个中空体的上直径大于中空体的下直径，其直径相对于第一方向垂直地被测量。存储电容器还包括设置在第一和第二电容器电极之间的第二电容器电极和介电材料。存储电容器还包括设置在中空体外部的绝缘材料和绝缘材料层。绝缘层的下侧设置在第一电容器部分的上侧的高度处。

2. 发明申请

US20080128773A1 Storage capacitor, a memory device and a method of manufacturing the same 有权
标题翻译：存储电容器，存储器件及其制造方法
公开(公告)号：US20080128773A1
公开(公告)日：2008-06-05
申请号：US11633090
申请日：2006-12-04
申请人： Peter Moll , Peter Baars , Till Schloesser , Rolf Weis , Klaus Muemmler
发明人： Peter Moll , Peter Baars , Till Schloesser , Rolf Weis , Klaus Muemmler
IPC分类号： H01L27/108
CPC分类号： H01L28/90 , H01L27/10814 , H01L27/10852 , H01L27/10894 , H01L27/10897
摘要： A storage capacitor includes a first capacitor portion and a second capacitor portion, the second capacitor portion being disposed above the first capacitor portion, thereby defining a first direction. The first and the second portions each include a hollow body made of a conductive material, respectively, thereby forming a first capacitor electrode. An upper diameter of each of the hollow bodies is larger than a lower diameter of the hollow body, the diameter being measured perpendicularly with respect to the first direction. The storage capacitor also includes a second capacitor electrode and a dielectric material disposed between the first and the second capacitor electrodes. The storage capacitor also includes an insulating material disposed outside the hollow bodies, and a layer of an insulating material. A lower side of the insulating layer is disposed at a height of an upper side of the first capacitor portion.
摘要翻译：存储电容器包括第一电容器部分和第二电容器部分，第二电容器部分设置在第一电容器部分上方，从而限定第一方向。第一和第二部分分别包括由导电材料制成的中空体，从而形成第一电容器电极。每个中空体的上直径大于中空体的下直径，其直径相对于第一方向垂直地被测量。存储电容器还包括设置在第一和第二电容器电极之间的第二电容器电极和介电材料。存储电容器还包括设置在中空体外部的绝缘材料和绝缘材料层。绝缘层的下侧设置在第一电容器部分的上侧的高度处。

3. 发明申请

US20050088895A1 DRAM cell array having vertical memory cells and methods for fabricating a DRAM cell array and a DRAM 审中-公开
标题翻译：具有垂直存储单元的DRAM单元阵列和用于制造DRAM单元阵列和DRAM的方法
公开(公告)号：US20050088895A1
公开(公告)日：2005-04-28
申请号：US10897687
申请日：2004-07-23
申请人： Dirk Manger , Till Schloesser , Rolf Weis , Bernd Goebel , Wolfgang Mueller , Joachim Nuetzel , Klaus Muemmler
发明人： Dirk Manger , Till Schloesser , Rolf Weis , Bernd Goebel , Wolfgang Mueller , Joachim Nuetzel , Klaus Muemmler
IPC分类号： G11C11/34
CPC分类号： H01L27/10841 , H01L27/10867
摘要： Memory cells having a cell capacitor and a cell transistor, which are arranged in a vertical cell structure, are provided in the cell array of a DRAM. By means of a deep implantation or a shallow implantation with subsequent epitaxial growth of silicon, a buried source/drain layer is formed, from which lower source/drain regions of the cell transistors emerge. The upper edge of the buried source/drain layer can be aligned with respect to a lower edge of a gate electrode of the cell transistor, which consequently results in a reduction of a gate/drain capacitance and also a leakage current between the gate electrode and the lower source/drain region. A gate conductor layer structure is applied and there are formed, from the gate conductor layer structure, in a controlled transistor array, gate electrode structures of control transistors and, in the cell array, a body connection structure for the connection of body regions of the cell transistors.
摘要翻译：在DRAM的单元阵列中设置具有单元电容器和单元晶体管的存储单元，其被布置在垂直单元结构中。通过深度注入或随后的硅的外延生长的浅注入，形成掩埋源极/漏极层，电池晶体管的下部源极/漏极区域从该衬底源极/漏极层出现。掩埋源极/漏极层的上边缘可以相对于单元晶体管的栅电极的下边缘对准，这因此导致栅极/漏极电容的减小以及栅电极和漏极电极之间的漏电流较低的源极/漏极区域。施加栅极导体层结构，并且从栅极导体层结构形成受控晶体管阵列，控制晶体管的栅极电极结构以及在单元阵列中形成用于连接主体区域的主体连接结构单元晶体管。

4. 发明申请

US20070075361A1 Method for producing a trench transistor and trench transistor 失效
标题翻译：沟槽晶体管和沟槽晶体管的制造方法
公开(公告)号：US20070075361A1
公开(公告)日：2007-04-05
申请号：US11529446
申请日：2006-09-28
申请人： Richard Luyken , Hans-Peter Moll , Martin Popp , Till Schloesser , Marc Strasser , Rolf Weis
发明人： Richard Luyken , Hans-Peter Moll , Martin Popp , Till Schloesser , Marc Strasser , Rolf Weis
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L21/26586 , H01L29/66537 , H01L29/66621 , H01L29/7834
摘要： In a method for producing a trench transistor, a substrate of a first conduction type is provided and a trench in the substrate and a gate dielectric in the trench are formed. A first conductive filling in the trench as a gate electrode on the gate dielectric and first source and drain regions are formed. An etched-back first conductive filling is produced by etching back the first conductive filling down to a depth below the first source and drain regions and second source and drain regions are formed. The second source and drain regions adjoin the first source and drain regions and extend to a depth at least as far as the etched-back first conductive filling. An insulation spacer above the etched-back first conductive filling is formed in the trench and a second conductive filling is provided in the trench as an upper part of the gate electrode.
摘要翻译：在制造沟槽晶体管的方法中，提供第一导电类型的衬底，并且形成衬底中的沟槽和沟槽中的栅极电介质。形成沟槽中作为栅极电介质和第一源极和漏极区域上的栅电极的第一导电填充物。蚀刻后的第一导电填充物是通过将第一导电填料向下蚀刻回到低于第一源的深度并形成漏极区和第二源极和漏极区而产生的。第二源极和漏极区域与第一源极和漏极区域相邻并且延伸至至少与蚀刻后的第一导电填充物一样深的深度。在所述沟槽中形成有在所述蚀刻后的第一导电填充物上方的绝缘间隔物，并且在所述沟槽中设置第二导电填充物作为所述栅电极的上部。

5. 发明授权

US07605032B2 Method for producing a trench transistor and trench transistor 失效
标题翻译：沟槽晶体管和沟槽晶体管的制造方法
公开(公告)号：US07605032B2
公开(公告)日：2009-10-20
申请号：US11529446
申请日：2006-09-28
申请人： Richard Johannes Luyken , Hans-Peter Moll , Martin Popp , Till Schloesser , Marc Strasser , Rolf Weis
发明人： Richard Johannes Luyken , Hans-Peter Moll , Martin Popp , Till Schloesser , Marc Strasser , Rolf Weis
IPC分类号： H01L21/334 , H01L21/8234 , H01L27/108 , H01L29/94 , H01L21/336 , H01L27/088
CPC分类号： H01L21/26586 , H01L29/66537 , H01L29/66621 , H01L29/7834
摘要： In a method for producing a trench transistor, a substrate of a first conduction type is provided and a trench in the substrate and a gate dielectric in the trench are formed. A first conductive filling in the trench as a gate electrode on the gate dielectric and first source and drain regions are formed. An etched-back first conductive filling is produced by etching back the first conductive filling down to a depth below the first source and drain regions and second source and drain regions are formed. The second source and drain regions adjoin the first source and drain regions and extend to a depth at least as far as the etched-back first conductive filling. An insulation spacer above the etched-back first conductive filling is formed in the trench and a second conductive filling is provided in the trench as an upper part of the gate electrode.
摘要翻译：在制造沟槽晶体管的方法中，提供第一导电类型的衬底，并且形成衬底中的沟槽和沟槽中的栅极电介质。形成沟槽中作为栅极电介质和第一源极和漏极区域上的栅电极的第一导电填充物。蚀刻后的第一导电填充物是通过将第一导电填料向下蚀刻回到低于第一源的深度并形成漏极区和第二源极和漏极区而产生的。第二源极和漏极区域与第一源极和漏极区域相邻并且延伸至至少与蚀刻后的第一导电填充物一样深的深度。在所述沟槽中形成有在所述蚀刻后的第一导电填充物上方的绝缘间隔物，并且在所述沟槽中设置第二导电填充物作为所述栅电极的上部。

6. 发明授权

US08598655B1 Semiconductor device and method for manufacturing a semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08598655B1
公开(公告)日：2013-12-03
申请号：US13566742
申请日：2012-08-03
申请人： Till Schloesser , Rolf Weis , Ralf Rudolf
发明人： Till Schloesser , Rolf Weis , Ralf Rudolf
IPC分类号： H01L29/08 , H01L29/417 , H01L29/78
CPC分类号： H01L27/0883 , H01L21/823412 , H01L21/823487 , H01L29/0634 , H01L29/42368 , H01L29/7809 , H01L29/781 , H01L29/7813 , H01L29/7828 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first transistor with a first drift zone, and a plurality of second transistors, each second transistor comprising a source region, a drain region and a gate electrode. The second transistors are electrically coupled in series to form a series circuit that is electrically coupled to the first transistor, the first and the plurality of second transistors being at least partially disposed in a semiconductor substrate including a buried doped layer, wherein the source or the drain regions of the second transistors are disposed in the buried doped layer.
摘要翻译：半导体器件包括具有第一漂移区的第一晶体管和多个第二晶体管，每个第二晶体管包括源极区，漏极区和栅电极。第二晶体管串联电耦合以形成电耦合到第一晶体管的串联电路，第一和第二晶体管至少部分地设置在包括掩埋掺杂层的半导体衬底中，其中源极或第二晶体管的漏极区域设置在掩埋掺杂层中。

7. 发明申请

US20080217672A1 INTEGRATED CIRCUIT HAVING A MEMORY 审中-公开
标题翻译：具有存储器的集成电路
公开(公告)号：US20080217672A1
公开(公告)日：2008-09-11
申请号：US11684033
申请日：2007-03-09
申请人： Martin Popp , Ulrike Gruening-von Schwerin , Till Schloesser , Peter Lahnor , Rolf Weis , Odo Wunnicke
发明人： Martin Popp , Ulrike Gruening-von Schwerin , Till Schloesser , Peter Lahnor , Rolf Weis , Odo Wunnicke
IPC分类号： H01G4/40 , H01L21/62 , H01L27/01
CPC分类号： H01L27/10817 , H01G4/38 , H01G4/40 , H01L27/0207 , H01L27/10814 , H01L27/10852 , H01L27/10888 , H01L28/91
摘要： An integrated circuit having a memory arrangement including capacitor elements and further capacitor elements is disclosed. One embodiment provides a substrate layer with contact pads and further contact pads; the capacitor elements being disposed in a first level on the substrate layer and connected with the contact pads; the further capacitor elements being disposed in a second level above the first level; contact elements being disposed between the capacitor elements and connected with the further contact pads; the further capacitor elements being disposed above the contact elements and being connected with the contact elements.
摘要翻译：公开了具有包括电容器元件和其它电容器元件的存储器布置的集成电路。一个实施例提供具有接触垫和另外的接触垫的衬底层; 所述电容器元件设置在所述基底层上的第一层中并与所述接触垫相连接; 所述另外的电容器元件设置在高于所述第一电平的第二电平; 接触元件设置在电容器元件之间并与另外的接触垫连接; 另外的电容器元件设置在接触元件上方并与接触元件连接。

8. 发明授权

US07141845B2 DRAM cell array and memory cell arrangement having vertical memory cells and methods for fabricating the same 失效
标题翻译：具有垂直存储单元的DRAM单元阵列和存储单元布置及其制造方法
公开(公告)号：US07141845B2
公开(公告)日：2006-11-28
申请号：US10898706
申请日：2004-07-23
申请人： Dirk Manger , Till Schloesser , Rolf Weis , Bernd Goebel , Wolfgang Mueller
发明人： Dirk Manger , Till Schloesser , Rolf Weis , Bernd Goebel , Wolfgang Mueller
IPC分类号： H01L27/108
CPC分类号： H01L27/10867 , H01L27/10841 , H01L27/10876 , H01L27/10888 , H01L27/10891
摘要： Memory cells each having a cell capacitor and a cell transistor, which are arranged in a vertical cell structure, are provided in the cell array of a DRAM. By means of a deep implantation or a shallow implantation and subsequent epitaxial growth of silicon, a buried source/drain layer is formed, from which lower source/drain regions of the cell transistors emerge. The upper edge of the buried source/drain layer can be aligned with respect to a lower edge of a gate electrode of the cell transistor and this results in a reduction of a gate/drain capacitance and also a leakage current between the gate electrode and the lower source/drain region. A body connection plate for the connection of the channel regions is applied to the substrate surface and contact holes are introduced into the body connection plate. Upper source/drain regions of the cell transistors are formed by implantation through the contact holes.
摘要翻译：每个具有单元电容器和单元晶体管的存储单元被布置在垂直单元结构中，被提供在DRAM的单元阵列中。通过深度注入或浅注入和随后的硅的外延生长，形成掩埋源极/漏极层，电池晶体管的下部源极/漏极区域从该衬底源极/漏极层出现。掩埋源极/漏极层的上边缘可以相对于单元晶体管的栅电极的下边缘对齐，并且这导致栅极/漏极电容的减小以及栅电极和漏电极之间的漏电流较低的源极/漏极区域。用于连接通道区域的主体连接板被施加到基板表面，并且接触孔被引入主体连接板。单元晶体管的上源/漏区通过接触孔注入而形成。

9. 发明申请

US20060076602A1 Dram cell pair and dram memory cell array 失效
标题翻译：戏剧单元对和阵容记忆体单元阵列
公开(公告)号：US20060076602A1
公开(公告)日：2006-04-13
申请号：US11222273
申请日：2005-09-08
申请人： Johann Harter , Wolfgang Mueller , Wolfgang Bergner , Ulrike Schwerin , Till Schloesser , Rolf Weis
发明人： Johann Harter , Wolfgang Mueller , Wolfgang Bergner , Ulrike Schwerin , Till Schloesser , Rolf Weis
IPC分类号： H01L29/94 , H01L21/8244
CPC分类号： H01L27/108 , G11C11/404 , H01L27/0207 , H01L27/10808 , H01L27/10829 , H01L29/785
摘要： Stack and trench memory cells are provided in a DRAM memory cell array. The stack and trench memory cells are arranged so as to form identical cell pairs each having a trench capacitor, a stack capacitor and a semiconductor fin, in which the active areas of two select transistors for addressing the trench and stack capacitors are formed. The semiconductor fins are arranged in succession in the longitudinal direction to form cell rows and in this arrangement are spaced apart from one another by in each case a trench capacitor. Respectively adjacent cell rows are separated from one another by trench isolator structures and are offset with respect to one another by half the length of a cell pair. The semiconductor fins are crossed by at least two active word lines, which are orthogonal with respect to the cell rows, for addressing the select transistors realized in the semiconductor fin.
摘要翻译：堆叠和沟槽存储单元被提供在DRAM存储单元阵列中。堆叠和沟槽存储单元布置成形成相同的单元对，每个单元对具有沟槽电容器，堆叠电容器和半导体鳍片，其中形成用于寻址沟槽和堆叠电容器的两个选择晶体管的有源区。半导体鳍片沿纵向连续布置以形成单元行，并且在这种布置中，在每种情况下都是沟槽电容器彼此间隔开。相邻的单元行通过沟槽隔离器结构彼此分离，并且相对于彼此相对于单元对的长度的一半偏移。半导体鳍片被至少两个相对于单元行正交的有源字线交叉，用于寻址在半导体鳍片中实现的选择晶体管。

10. 发明申请

US20060056228A1 Transistor, memory cell array and method of manufacturing a transistor 有权
标题翻译：晶体管，存储单元阵列及制造晶体管的方法
公开(公告)号：US20060056228A1
公开(公告)日：2006-03-16
申请号：US10939255
申请日：2004-09-10
申请人： Till Schloesser , Rolf Weis , Ulrike Schwerin
发明人： Till Schloesser , Rolf Weis , Ulrike Schwerin
IPC分类号： G11C11/24 , H01L29/94
CPC分类号： G11C11/404 , H01L27/0207 , H01L27/10873 , H01L27/10879 , H01L29/66795 , H01L29/66818 , H01L29/785 , H01L29/7854
摘要： A transistor, memory cell array and method of manufacturing a transistor are disclosed. In one embodiment, the invention refers to a transistor, which is formed at least partially in a semiconductor substrate, comprising a first and a second source/drain regions, a channel region connecting said first and second source/drain regions, said channel region being disposed in said semiconductor substrate, and a gate electrode disposed along said channel region and being electrically isolated from said channel region, for controlling an electrical current flowing between said first and second source/drain regions, wherein said channel region comprises a fin-region in which the channel has the shape of a ridge, said ridge comprising a top side and two lateral sides in a cross section perpendicular to a line connecting said first and second source/drain regions, wherein said top side is disposed beneath a surface of said semiconductor substrate and said gate electrode is disposed along said top side and said two lateral sides.
摘要翻译：公开了晶体管，存储单元阵列和制造晶体管的方法。在一个实施例中，本发明涉及至少部分地形成在半导体衬底中的晶体管，包括第一和第二源极/漏极区域，连接所述第一和第二源极/漏极区域的沟道区域，所述沟道区域是设置在所述半导体衬底中，以及栅电极，沿着所述沟道区设置并与所述沟道区电隔离，用于控制在所述第一和第二源/漏区之间流动的电流，其中所述沟道区包括所述通道具有脊的形状，所述脊包括垂直于连接所述第一和第二源极/漏极区的线的横截面中的顶侧和两个侧边，其中所述顶侧设置在所述半导体的表面下方基板和所述栅电极沿着所述顶侧和所述两个横向侧面设置。

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