专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08751163B2 System and method for providing an electronic representation of a route 有权
标题翻译：用于提供路线的电子表示的系统和方法
公开(公告)号：US08751163B2
公开(公告)日：2014-06-10
申请号：US13083222
申请日：2011-04-08
申请人： Peter Mitchell
发明人： Peter Mitchell
IPC分类号： G01C21/00 , G06F19/00
CPC分类号： G01C21/3647 , G08G1/202
摘要： Disclosed is a computer systems, methods and computer program products for providing an electronic representation of a route. A display device displays a plurality of sequential displays of the ground level area representations along the recorded route including: a first display comprising an origin location area representation; a plurality of sequential displays comprising sequential location area representations along the route; and a last display of a destination location area representation. The at least one ground level image can be a photographic image. A record of a route is recorded by a GPS device.
摘要翻译：公开了一种用于提供路线的电子表示的计算机系统，方法和计算机程序产品。显示装置沿着所记录的路线显示地平面区域表示的多个顺序显示，包括：第一显示器，其包括原点位置区域表示; 多个顺序显示器，包括沿路线的顺序位置区域表示; 以及目的地位置区域表示的最后显示。所述至少一个地平面图像可以是摄影图像。路由的记录由GPS设备记录。

2. 发明授权

US08465327B2 High-speed memory connector 有权
标题翻译：高速内存连接器
公开(公告)号：US08465327B2
公开(公告)日：2013-06-18
申请号：US12905692
申请日：2010-10-15
申请人： Greg Springer , Vince Duperron , Marc Simmel , Peter Mitchell , Joshua Funamura
发明人： Greg Springer , Vince Duperron , Marc Simmel , Peter Mitchell , Joshua Funamura
IPC分类号： H01R24/00
CPC分类号： H01R13/6471 , Y10T29/49208
摘要： Structures, methods, and apparatus that provide sockets or connectors that are capable of operating at high data rates. One example provides a connector that uses a flex board to form a connection between pins of a socket or connector and a printed circuit board. In another example, one or more flex boards are used to provide a signal path between a memory device, such as an SODIMM, and a printed circuit board. Another example provides a stack of wafers, each formed of an insulated material and supporting one or more conductive pins for making an electrical connection between a memory device and a flex board.
摘要翻译：提供能够以高数据速率运行的插座或连接器的结构，方法和设备。一个例子提供了一种连接器，其使用柔性板来形成插座或连接器的引脚与印刷电路板之间的连接。在另一示例中，使用一个或多个柔性板来提供诸如SODIMM的存储器件与印刷电路板之间的信号路径。另一示例提供了一叠晶片，每个晶片由绝缘材料形成并且支撑用于在存储器件和柔性板之间进行电连接的一个或多个导电引脚。

3. 发明申请

US20130118461A1 NOx FEEDBACK FOR COMBUSTION CONTROL 有权
标题翻译：用于燃烧控制的NOx反馈
公开(公告)号：US20130118461A1
公开(公告)日：2013-05-16
申请号：US13295648
申请日：2011-11-14
申请人： Peter Mitchell , Chris Riffle , Michiel J. Van Nieuwstadt , Frank M. Korpics , Jeff Reich , Dean Pennala
发明人： Peter Mitchell , Chris Riffle , Michiel J. Van Nieuwstadt , Frank M. Korpics , Jeff Reich , Dean Pennala
IPC分类号： F02D43/00 , F02D41/14 , F02D41/30 , F02B47/08
CPC分类号： F02D21/08 , F02B37/007 , F02B2075/125 , F02D13/0207 , F02D13/0219 , F02D41/0065 , F02D41/146 , F02D41/1461 , F02D2250/36 , F02M26/05 , F02M26/06 , F02M26/08 , F02M26/15 , F02M26/24 , F02M26/38 , Y02T10/123 , Y02T10/47
摘要： A method for controlling combustion in an engine is provided. The method comprises under a first condition, adjusting an EGR amount of a total cylinder charge in response to engine out NOx levels being below a first threshold. In this way, NOx levels may be used as feedback to control combustion stability.
摘要翻译：提供一种用于控制发动机燃烧的方法。该方法包括在第一条件下，响应于发动机排出的NOx水平低于第一阈值来调整总气瓶充量的EGR量。以这种方式，可以将NOx水平用作反馈以控制燃烧稳定性。

4. 发明申请

US20080042287A1 Integrated Circuit Chip Utilizing Oriented Carbon Nanotube Conductive Layers 失效
标题翻译：集成电路芯片利用定向碳纳米管导电层
公开(公告)号：US20080042287A1
公开(公告)日：2008-02-21
申请号：US11924894
申请日：2007-10-26
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell
IPC分类号： H01L23/52
CPC分类号： H01L21/7685 , B82Y10/00 , H01L21/32051 , H01L21/76838 , H01L21/76876 , H01L21/76877 , H01L23/53276 , H01L51/0048 , H01L51/0052 , H01L2221/1094 , H01L2924/0002 , Y10S977/742 , Y10S977/762 , Y10S977/778 , Y10S977/842 , H01L2924/00
摘要： A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least one sublayer of oriented carbon nanotubes. The conductive layer sandwich preferably contains two sublayers of carbon nanotubes, in which the carbon nanotube orientation in one sublayer is substantially perpendicular to that of the other layer. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal. In one embodiment, oriented carbon nanotubes are created by forming a series of parallel surface ridges, covering the top and one side of the ridges with a catalyst inhibitor, and growing carbon nanotubes horizontally from the uncovered vertical sides of the ridges. In another embodiment, oriented carbon nanotubes are grown on the surface of a conductive material in the presence of a directional flow of reactant gases and a catalyst.
摘要翻译：集成电路中的导电层形成为具有多个子层的夹层，包括至少一个定向碳纳米管子层。导电层夹层优选含有碳纳米管的两个子层，其中一个子层中的碳纳米管取向基本上垂直于另一层的碳纳米管取向。导电层夹层优选地包含一种或多种另外的导电材料的子层，例如金属。在一个实施方案中，通过形成一系列平行的表面脊，通过用催化剂抑制剂覆盖脊的顶部和一侧并从脊的未被覆盖的垂直侧水平生长碳纳米管来产生定向碳纳米管。在另一个实施方案中，在反应物气体和催化剂的定向流的存在下，在导电材料的表面上生长取向的碳纳米管。

5. 发明申请

US20070228510A1 SHALLOW TRENCH ISOLATION FILL BY LIQUID PHASE DEPOSITION OF SiO2 有权
标题翻译：通过SiO 2的液相沉积沉积分离膜
公开(公告)号：US20070228510A1
公开(公告)日：2007-10-04
申请号：US11760477
申请日：2007-06-08
申请人： Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit
发明人： Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit
IPC分类号： H01L29/00
CPC分类号： H01L27/1203 , H01L21/76283 , H01L21/84
摘要： To isolate two active regions formed on a silicon-on-insulator (SOI) substrate, a shallow trench isolation region is filled with liquid phase deposited silicon dioxide (LPD-SiO2) while avoiding covering the active areas with the oxide. By selectively depositing the oxide in this manner, the polishing needed to planarize the wafer is significantly reduced as compared to a chemical-vapor deposited oxide layer that covers the entire wafer surface. Additionally, the LPD-SiO2 does not include the growth seams that CVD silicon dioxide does. Accordingly, the etch rate of the LPD-SiO2 is uniform across its entire expanse thereby preventing cavities and other etching irregularities present in prior art shallow trench isolation regions in which the etch rate of growth seams exceeds that of the other oxide areas.
摘要翻译：为了隔离形成在绝缘体上硅（SOI）衬底上的两个有源区，浅沟槽隔离区填充有液相沉积二氧化硅（LPD-SiO 2），同时避免覆盖有源区与氧化物。通过以这种方式选择性地沉积氧化物，与覆盖整个晶片表面的化学气相沉积氧化物层相比，平坦化晶片所需的抛光显着降低。此外，LPD-SiO 2不包括CVD二氧化硅的生长接缝。因此，LPD-SiO 2的蚀刻速率在其整个宽度上是均匀的，从而防止存在于现有技术的浅沟槽隔离区域中的空穴和其它蚀刻不规则性，其中生长接缝的蚀刻速率超过其他氧化物区域。

6. 发明申请

US20070059671A1 Career analysis method and system 失效
标题翻译：职业分析方法与制度
公开(公告)号：US20070059671A1
公开(公告)日：2007-03-15
申请号：US11224519
申请日：2005-09-12
申请人： Peter Mitchell
发明人： Peter Mitchell
IPC分类号： G09B19/18
CPC分类号： G09B7/00 , G06Q10/105 , G06Q30/0201 , G06Q50/2057
摘要： A career analysis method and system. The system comprises a computing apparatus comprising data. The data comprises a specified job title and a first list comprising a first plurality of required skills for the specified job title. Candidate data is received by the computing apparatus. Candidate data comprises a job candidate and a second list comprising plurality of skills related to a job held by the candidate. The first plurality of required skills is compared with the plurality of skills related to the job held by the candidate to determine a set of common skills. A common skills score is calculated. A first set of market valued skills from the first plurality of required skills is determined. A score is calculated based on a function of the first set of market valued skills and the first plurality of required skills.
摘要翻译：职业分析方法和制度。该系统包括包括数据的计算装置。所述数据包括指定的职位和包含所述指定职务的第一多个所需技能的第一列表。候选数据由计算装置接收。候选数据包括候选人和包括与候选人所持有的工作相关的多种技能的第二列表。将第一组所需的技能与与候选人持有的工作相关的多种技能进行比较，以确定一组共同技能。计算一个常见技能得分。确定了从头几种所需技能中获得的第一套市场价值技能。一个分数是根据第一组市场价值技能和第一批所需技能的函数计算的。

7. 发明申请

US20070048879A1 Integrated Circuit Chip Utilizing Oriented Carbon Nanotube Conductive Layers 有权
标题翻译：集成电路芯片利用定向碳纳米管导电层
公开(公告)号：US20070048879A1
公开(公告)日：2007-03-01
申请号：US11552771
申请日：2006-10-25
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell
IPC分类号： H01L21/00
CPC分类号： H01L21/7685 , B82Y10/00 , H01L21/32051 , H01L21/76838 , H01L21/76876 , H01L21/76877 , H01L23/53276 , H01L51/0048 , H01L51/0052 , H01L2221/1094 , H01L2924/0002 , Y10S977/742 , Y10S977/762 , Y10S977/778 , Y10S977/842 , H01L2924/00
摘要： A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least one sublayer of oriented carbon nanotubes. The conductive layer sandwich preferably contains two sublayers of carbon nanotubes, in which the carbon nanotube orientation in one sublayer is substantially perpendicular to that of the other layer. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal. In one embodiment, oriented carbon nanotubes are created by forming a series of parallel surface ridges, covering the top and one side of the ridges with a catalyst inhibitor, and growing carbon nanotubes horizontally from the uncovered vertical sides of the ridges. In another embodiment, oriented carbon nanotubes are grown on the surface of a conductive material in the presence of a directional flow of reactant gases and a catalyst.
摘要翻译：集成电路中的导电层形成为具有多个子层的夹层，包括至少一个定向碳纳米管子层。导电层夹层优选含有碳纳米管的两个子层，其中一个子层中的碳纳米管取向基本上垂直于另一层的碳纳米管取向。导电层夹层优选地包含一种或多种另外的导电材料的子层，例如金属。在一个实施方案中，通过形成一系列平行的表面脊，通过用催化剂抑制剂覆盖脊的顶部和一侧并从脊的未被覆盖的垂直侧水平生长碳纳米管来产生定向碳纳米管。在另一个实施方案中，在反应物气体和催化剂的定向流的存在下，在导电材料的表面上生长取向的碳纳米管。

8. 发明申请

US20060172496A1 DOUBLE-GATE FETs (FIELD EFFECT TRANSISTORS) 失效
标题翻译：双栅FET（场效应晶体管）
公开(公告)号：US20060172496A1
公开(公告)日：2006-08-03
申请号：US10905979
申请日：2005-01-28
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L29/42384 , H01L29/78648 , H01L29/78654
摘要： A method for forming transistors with mutually-aligned double gates. The method includes the steps of (a) providing a wrap-around-gate transistor structure, wherein the wrap-around-gate transistor structure includes (i) semiconductor region, and (ii) a gate electrode region wrapping around the semiconductor region, wherein the gate electrode region is electrically insulated from the semiconductor region by a gate dielectric film; and (b) removing first and second portions of the wrap-around-gate transistor structure so as to form top and bottom gate electrodes from the gate electrode region, wherein the top and bottom gate electrodes are electrically disconnected from each other.
摘要翻译：一种用于形成具有相互对准的双栅极的晶体管的方法。该方法包括以下步骤：（a）提供环绕栅极晶体管结构，其中环绕栅极晶体管结构包括（i）半导体区域和（ii）围绕半导体区域包围的栅电极区域，其中栅电极区域通过栅极电介质膜与半导体区域电绝缘; 以及（b）去除环绕栅极晶体管结构的第一和第二部分，以便从栅极电极区域形成顶部和底部栅电极，其中顶部和底部栅电极彼此电断开。

9. 发明申请

US20050286293A1 Horizontal memory gain cells 失效
标题翻译：水平记忆增益细胞
公开(公告)号：US20050286293A1
公开(公告)日：2005-12-29
申请号：US10879815
申请日：2004-06-29
申请人： Toshiharu Furukawa , Mark Hakey , David Horak , Charles Koburger , Mark Masters , Peter Mitchell
发明人： Toshiharu Furukawa , Mark Hakey , David Horak , Charles Koburger , Mark Masters , Peter Mitchell
IPC分类号： G11C11/00 , G11C13/02 , H01L21/8242 , H01L27/108
CPC分类号： G11C13/025 , B82Y10/00 , G11C13/0033 , G11C2213/17 , H01L27/108 , H01L27/10861 , H01L27/10873 , Y10S977/742
摘要： A gain cell for a memory circuit, a memory circuit formed from multiple gain cells, and methods of fabricating such gain cells and memory circuits. The memory gain cell includes a storage capacitor, a write device electrically coupled with the storage capacitor for charging and discharging the storage capacitor to define a stored electrical charge, and a read device. The read device includes one or more semiconducting carbon nanotubes each electrically coupled between a source and drain. A portion of each semiconducting carbon nanotube is gated by the read gate and the storage capacitor to thereby regulate a current flowing through each semiconducting carbon nanotube from the source to the drain. The current is proportional to the electrical charge stored by the storage capacitor. In certain embodiments, the memory gain cell may include multiple storage capacitors.
摘要翻译：用于存储器电路的增益单元，由多个增益单元形成的存储器电路，以及制造这种增益单元和存储器电路的方法。存储增益单元包括存储电容器，与存储电容器电耦合以对存储电容器进行充电和放电以定义存储的电荷的写入装置和读取装置。读取装置包括一个或多个半导体碳纳米管，每个碳纳米管电耦合在源极和漏极之间。每个半导体碳纳米管的一部分由读取栅极和存储电容器选通，从而调节从源极到漏极流过每个半导体碳纳米管的电流。电流与存储电容器存储的电荷成比例。在某些实施例中，存储器增益单元可以包括多个存储电容器。

10. 发明申请

US20050202607A1 Method of forming FinFET gates without long etches 有权
标题翻译：在没有长时间刻蚀的情况下形成FinFET栅极的方法
公开(公告)号：US20050202607A1
公开(公告)日：2005-09-15
申请号：US10798907
申请日：2004-03-11
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Hofak , Charles Koburger , Peter Mitchell , Larry Nesbit
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Hofak , Charles Koburger , Peter Mitchell , Larry Nesbit
IPC分类号： H01L21/00 , H01L21/336 , H01L29/786
CPC分类号： H01L29/785 , H01L29/66545 , H01L29/66795 , H01L29/7831
摘要： A method for forming a gate for a FinFET uses a series of selectively deposited sidewalls along with other sacrificial layers to create a cavity in which a gate can be accurately and reliably formed. This technique avoids long directional etching steps to form critical dimensions of the gate that have contributed to the difficulty of forming FinFETs using conventional techniques. In particular, a sacrificial seed layer, from which sidewalls can be accurately grown, is first deposited over a silicon fin. Once the sacrificial seed layer is etched away, the sidewalls can be surrounded by another disposable layer. Etching away the sidewalls will result in cavities being formed that straddle the fin, and gate conductor material can then be deposited within these cavities. Thus, the height and thickness of the resulting FinFET gate can be accurately controlled by avoiding a long direction etch down the entire height of the fin.
摘要翻译：用于形成用于FinFET的栅极的方法使用一系列选择性沉积的侧壁与其它牺牲层一起形成可以准确可靠地形成栅极的空腔。该技术避免了长时间的定向蚀刻步骤，以形成使用常规技术有助于形成FinFET的困难的栅极的临界尺寸。特别地，首先在硅片上沉积可以精确地生长侧壁的牺牲种子层。一旦牺牲种子层被蚀刻掉，侧壁可以被另一个一次性层包围。蚀刻侧壁将导致跨过翅片形成的空腔，然后栅极导体材料可以沉积在这些空腔内。因此，通过避免沿翅片的整个高度的长方向蚀刻，可以精确地控制所得FinFET栅极的高度和厚度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式