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1. 发明申请

US20050179029A1 Methods of fabricating vertical carbon nanotube field effect transistors for arrangement in arrays and field effect transistors and arrays formed thereby 有权
标题翻译：制造垂直碳纳米管场效应晶体管的方法，用于排列阵列和由此形成的场效应晶体管和阵列
公开(公告)号：US20050179029A1
公开(公告)日：2005-08-18
申请号：US10777576
申请日：2004-02-12
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit
IPC分类号： G11C13/02 , H01L21/336 , H01L27/28 , H01L51/05 , H01L51/30 , H01L51/40 , H01L29/06
CPC分类号： H01L51/057 , B82Y10/00 , G11C13/025 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/125 , H01L29/66409 , H01L29/772 , H01L51/0048 , Y10S977/734
摘要： A method for forming carbon nanotube field effect transistors, arrays of carbon nanotube field effect transistors, and device structures and arrays of device structures formed by the methods. The methods include forming a stacked structure including a gate electrode layer and catalyst pads each coupled electrically with a source/drain contact. The gate electrode layer is divided into multiple gate electrodes and at least one semiconducting carbon nanotube is synthesized by a chemical vapor deposition process on each of the catalyst pads. The completed device structure includes a gate electrode with a sidewall covered by a gate dielectric and at least one semiconducting carbon nanotube adjacent to the sidewall of the gate electrode. Source/drain contacts are electrically coupled with opposite ends of the semiconducting carbon nanotube to complete the device structure. Multiple device structures may be configured either as a memory circuit or as a logic circuit.
摘要翻译：一种形成碳纳米管场效应晶体管的方法，碳纳米管场效应晶体管的阵列，以及通过该方法形成的器件结构和器件结构阵列。所述方法包括形成包括栅极电极层和各个与源极/漏极接触电连接的催化剂焊盘的堆叠结构。栅极电极层被分成多个栅极电极，并且通过化学气相沉积工艺在每个催化剂焊盘上合成至少一个半导体碳纳米管。完成的器件结构包括具有由栅极电介质覆盖的侧壁的栅电极和与栅电极的侧壁相邻的至少一个半导体碳纳米管。源极/漏极触点与半导体碳纳米管的相对端电耦合以完成器件结构。多个器件结构可以被配置为存储器电路或逻辑电路。

2. 发明申请

US20050167655A1 Vertical nanotube semiconductor device structures and methods of forming the same 审中-公开
标题翻译：垂直纳米管半导体器件结构及其形成方法
公开(公告)号：US20050167655A1
公开(公告)日：2005-08-04
申请号：US10767065
申请日：2004-01-29
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit
IPC分类号： B82B1/00 , B82B3/00 , H01L27/28 , H01L51/05 , H01L51/30 , H01L51/40 , H01L29/06
CPC分类号： H01L51/057 , B82Y10/00 , H01L51/0048 , Y10S977/70 , Y10S977/734 , Y10S977/742
摘要： Vertical device structures incorporating at least one nanotube and methods for fabricating such device structures by chemical vapor deposition. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad and encased in a coating of a dielectric material. Vertical field effect transistors may be fashioned by forming a gate electrode about the encased nanotubes such that the encased nanotubes extend vertically through the thickness of the gate electrode. Capacitors may be fashioned in which the encased nanotubes and the corresponding catalyst pad bearing the encased nanotubes forms one capacitor plate.
摘要翻译：结合至少一个纳米管的垂直器件结构和通过化学气相沉积制造这种器件结构的方法。每个纳米管通过由催化剂垫催化的化学气相沉积生长并且包裹在电介质材料的涂层中。可以通过围绕封装的纳米管形成栅电极来形成垂直场效应晶体管，使得封装的纳米管垂直延伸穿过栅电极的厚度。可以形成电容器，其中包裹的纳米管和带有封装的纳米管的相应的催化剂垫片形成一个电容器板。

3. 发明申请

US20050202322A1 Methods of forming alternating phase shift masks having improved phase-shift tolerance 失效
标题翻译：形成具有改进的相移公差的交替相移掩模的方法
公开(公告)号：US20050202322A1
公开(公告)日：2005-09-15
申请号：US10798908
申请日：2004-03-11
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit
IPC分类号： G03C5/00 , G03F1/00 , G03F9/00
CPC分类号： G03F1/30
摘要： Methods for fabricating alternating phase shift masks or reticles used in semiconductor optical lithography systems. The methods generally include forming a layer of phase shift mask material on a handle substrate and patterning the layer to define recessed phase shift windows. The patterned layer is transferred from the handle wafer to a mask blank. The depth of the phase shift windows is determined by the thickness of the layer of phase shift mask material and is independent of the patterning process. In particular, the depth of the phase shift windows is not dependent upon the etch rate uniformity of an etch process across a surface of a mask blank.
摘要翻译：用于制造用于半导体光刻系统中的交替相移掩模或掩模版的方法。所述方法通常包括在手柄基板上形成一层相移掩模材料，并且图案化该层以限定凹陷的相移窗口。图案层从手柄晶片转移到掩模板。相移窗口的深度由相移掩模材料层的厚度确定，并且与图案化工艺无关。特别地，相移窗口的深度不依赖于通过掩模板的表面的蚀刻工艺的蚀刻速率均匀性。

4. 发明申请

US20050130387A1 Shallow trench isolation fill by liquid phase deposition of SiO2 失效
标题翻译：浅沟槽隔离填充SiO 2的液相沉积
公开(公告)号：US20050130387A1
公开(公告)日：2005-06-16
申请号：US10732953
申请日：2003-12-11
申请人： Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit
发明人： Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit
IPC分类号： H01L21/762 , H01L21/84 , H01L27/12 , H01L27/01 , H01L21/76 , H01L31/0392
CPC分类号： H01L27/1203 , H01L21/76283 , H01L21/84
摘要： To isolate two active regions formed on a silicon-on-insulator (SOI) substrate, a shallow trench isolation region is filled with liquid phase deposited silicon dioxide (LPD-SiO2) while avoiding covering the active areas with the oxide. By selectively depositing the oxide in this manner, the polishing needed to planarize the wafer is significantly reduced as compared to a chemical-vapor deposited oxide layer that covers the entire wafer surface. Additionally, the LPD-SiO2 does not include the growth seams that CVD silicon dioxide does. Accordingly, the etch rate of the LPD-SiO2 is uniform across its entire expanse thereby preventing cavities and other etching irregularities present in prior art shallow trench isolation regions in which the etch rate of growth seams exceeds that of the other oxide areas.
摘要翻译：为了隔离形成在绝缘体上硅（SOI）衬底上的两个有源区，浅沟槽隔离区填充有液相沉积二氧化硅（LPD-SiO 2），同时避免覆盖有源区与氧化物。通过以这种方式选择性地沉积氧化物，与覆盖整个晶片表面的化学气相沉积氧化物层相比，平坦化晶片所需的抛光显着降低。此外，LPD-SiO 2不包括CVD二氧化硅的生长接缝。因此，LPD-SiO 2的蚀刻速率在其整个宽度上是均匀的，从而防止存在于现有技术的浅沟槽隔离区域中的空穴和其它蚀刻不规则性，其中生长接缝的蚀刻速率超过其他氧化物区域。

5. 发明申请

US20070228510A1 SHALLOW TRENCH ISOLATION FILL BY LIQUID PHASE DEPOSITION OF SiO2 有权
标题翻译：通过SiO 2的液相沉积沉积分离膜
公开(公告)号：US20070228510A1
公开(公告)日：2007-10-04
申请号：US11760477
申请日：2007-06-08
申请人： Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit
发明人： Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit
IPC分类号： H01L29/00
CPC分类号： H01L27/1203 , H01L21/76283 , H01L21/84
摘要： To isolate two active regions formed on a silicon-on-insulator (SOI) substrate, a shallow trench isolation region is filled with liquid phase deposited silicon dioxide (LPD-SiO2) while avoiding covering the active areas with the oxide. By selectively depositing the oxide in this manner, the polishing needed to planarize the wafer is significantly reduced as compared to a chemical-vapor deposited oxide layer that covers the entire wafer surface. Additionally, the LPD-SiO2 does not include the growth seams that CVD silicon dioxide does. Accordingly, the etch rate of the LPD-SiO2 is uniform across its entire expanse thereby preventing cavities and other etching irregularities present in prior art shallow trench isolation regions in which the etch rate of growth seams exceeds that of the other oxide areas.
摘要翻译：为了隔离形成在绝缘体上硅（SOI）衬底上的两个有源区，浅沟槽隔离区填充有液相沉积二氧化硅（LPD-SiO 2），同时避免覆盖有源区与氧化物。通过以这种方式选择性地沉积氧化物，与覆盖整个晶片表面的化学气相沉积氧化物层相比，平坦化晶片所需的抛光显着降低。此外，LPD-SiO 2不包括CVD二氧化硅的生长接缝。因此，LPD-SiO 2的蚀刻速率在其整个宽度上是均匀的，从而防止存在于现有技术的浅沟槽隔离区域中的空穴和其它蚀刻不规则性，其中生长接缝的蚀刻速率超过其他氧化物区域。

6. 发明申请

US20060172496A1 DOUBLE-GATE FETs (FIELD EFFECT TRANSISTORS) 失效
标题翻译：双栅FET（场效应晶体管）
公开(公告)号：US20060172496A1
公开(公告)日：2006-08-03
申请号：US10905979
申请日：2005-01-28
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L29/42384 , H01L29/78648 , H01L29/78654
摘要： A method for forming transistors with mutually-aligned double gates. The method includes the steps of (a) providing a wrap-around-gate transistor structure, wherein the wrap-around-gate transistor structure includes (i) semiconductor region, and (ii) a gate electrode region wrapping around the semiconductor region, wherein the gate electrode region is electrically insulated from the semiconductor region by a gate dielectric film; and (b) removing first and second portions of the wrap-around-gate transistor structure so as to form top and bottom gate electrodes from the gate electrode region, wherein the top and bottom gate electrodes are electrically disconnected from each other.
摘要翻译：一种用于形成具有相互对准的双栅极的晶体管的方法。该方法包括以下步骤：（a）提供环绕栅极晶体管结构，其中环绕栅极晶体管结构包括（i）半导体区域和（ii）围绕半导体区域包围的栅电极区域，其中栅电极区域通过栅极电介质膜与半导体区域电绝缘; 以及（b）去除环绕栅极晶体管结构的第一和第二部分，以便从栅极电极区域形成顶部和底部栅电极，其中顶部和底部栅电极彼此电断开。

7. 发明申请

US20050130341A1 Selective synthesis of semiconducting carbon nanotubes 失效
标题翻译：半导体碳纳米管的选择性合成
公开(公告)号：US20050130341A1
公开(公告)日：2005-06-16
申请号：US10732951
申请日：2003-12-11
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit
IPC分类号： B82B3/00 , C01B31/02 , C30B25/02 , C30B29/02 , C30B29/60 , H01L29/15 , H01L29/786 , H01L51/30 , H01L21/336
CPC分类号： H01L51/0512 , B82Y10/00 , B82Y30/00 , B82Y40/00 , C01B32/162 , C01B2202/22 , C01B2202/34 , C30B25/02 , C30B29/02 , C30B29/605 , H01L51/0048 , Y10S977/854
摘要： Methods for selecting semiconducting carbon nanotubes from a random collection of conducting and semiconducting carbon nanotubes synthesized on multiple synthesis sites carried by a substrate and structures formed thereby. After an initial growth stage, synthesis sites bearing conducting carbon nanotubes are altered to discontinue synthesis at these specific synthesis sites and, thereby, halt lengthening of the conducting carbon nanotubes. Synthesis sites bearing semiconducting carbon nanotubes are unaffected by the alteration so that semiconducting carbon nanotubes may be lengthened to a greater length than the conducting carbon nanotubes.
摘要翻译：从由衬底承载的多个合成位点上合成的导电和半导体碳纳米管的随机集合以及由此形成的结构选择半导体碳纳米管的方法。在初始生长阶段之后，改变承载导电碳纳米管的合成位点，以在这些特定合成位点停止合成，从而停止导电碳纳米管的延长。具有半导体碳纳米管的合成位点不受改变的影响，使得半导体碳纳米管可以被延长到比导电碳纳米管更长的长度。

8. 发明申请

US20080044954A1 METHODS OF FABRICATING VERTICAL CARBON NANOTUBE FIELD EFFECT TRANSISTORS FOR ARRANGEMENT IN ARRAYS AND FIELD EFFECT TRANSISTORS AND ARRAYS FORMED THEREBY 有权
标题翻译：制备垂直碳纳米管场效应晶体管的方法在阵列和场效应晶体管中的布置及其形成的阵列
公开(公告)号：US20080044954A1
公开(公告)日：2008-02-21
申请号：US11926627
申请日：2007-10-29
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit
IPC分类号： H01L21/8234
CPC分类号： H01L51/057 , B82Y10/00 , G11C13/025 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/125 , H01L29/66409 , H01L29/772 , H01L51/0048 , Y10S977/734
摘要： A method for forming carbon nanotube field effect transistors, arrays of carbon nanotube field effect transistors, and device structures and arrays of device structures formed by the methods. The methods include forming a stacked structure including a gate electrode layer and catalyst pads each coupled electrically with a source/drain contact. The gate electrode layer is divided into multiple gate electrodes and at least one semiconducting carbon nanotube is synthesized by a chemical vapor deposition process on each of the catalyst pads. The completed device structure includes a gate electrode with a sidewall covered by a gate dielectric and at least one semiconducting carbon nanotube adjacent to the sidewall of the gate electrode. Source/drain contacts are electrically coupled with opposite ends of the semiconducting carbon nanotube to complete the device structure. Multiple device structures may be configured either as a memory circuit or as a logic circuit.
摘要翻译：一种形成碳纳米管场效应晶体管的方法，碳纳米管场效应晶体管的阵列，以及通过该方法形成的器件结构和器件结构阵列。所述方法包括形成包括栅极电极层和各个与源极/漏极接触电连接的催化剂焊盘的堆叠结构。栅极电极层被分成多个栅极电极，并且通过化学气相沉积工艺在每个催化剂焊盘上合成至少一个半导体碳纳米管。完成的器件结构包括具有由栅极电介质覆盖的侧壁的栅电极和与栅电极的侧壁相邻的至少一个半导体碳纳米管。源极/漏极触点与半导体碳纳米管的相对端电耦合以完成器件结构。多个器件结构可以被配置为存储器电路或逻辑电路。

9. 发明申请

US20080040696A1 Design Structures Incorporating Shallow Trench Isolation Filled by Liquid Phase Deposition of SiO2 审中-公开
标题翻译：通过液相沉积SiO 2填充的浅沟槽隔离的设计结构
公开(公告)号：US20080040696A1
公开(公告)日：2008-02-14
申请号：US11875069
申请日：2007-10-19
申请人： Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit
发明人： Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5045 , H01L21/76224
摘要： Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes shallow trench isolation filled with liquid phase deposited silicon dioxide (LPD-SiO2). The shallow trench isolation region is used to isolate two active regions formed on a silicon-on-insulator (SOI) substrate. By selectively depositing the oxide so that the active areas are not covered with the oxide, the polishing needed to planarize the wafer is significantly reduced as compared to a chemical-vapor deposited oxide layer that covers the entire wafer surface. Additionally, the LPD-SiO2 does not include the growth seams that CVD silicon dioxide does. Accordingly, the etch rate of the LPD-SiO2 is uniform across its entire expanse thereby preventing cavities and other etching irregularities present in prior art shallow trench isolation regions in which the etch rate of growth seams exceeds that of the other oxide areas.
摘要翻译：设计结构体现在用于设计，制造或测试其中设计结构包括填充有液相沉积二氧化硅（LPD-SiO 2）的浅沟槽隔离物的设计的机器可读介质中。浅沟槽隔离区用于隔离在绝缘体上硅（SOI）衬底上形成的两个有源区。通过选择性地沉积氧化物使得有源区域不被氧化物覆盖，与覆盖整个晶片表面的化学气相沉积氧化物层相比，平坦化晶片所需的抛光显着降低。此外，LPD-SiO 2不包括CVD二氧化硅的生长接缝。因此，LPD-SiO 2的蚀刻速率在其整个宽度上是均匀的，从而防止存在于现有技术的浅沟槽隔离区域中的空穴和其它蚀刻不规则性，其中生长接缝的蚀刻速率超过其他氧化物区域。

10. 发明申请

US20060060562A1 SUB-LITHOGRAPHIC IMAGING TECHNIQUES AND PROCESSES 失效
标题翻译：子图像成像技术和方法
公开(公告)号：US20060060562A1
公开(公告)日：2006-03-23
申请号：US10711458
申请日：2004-09-20
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit , James Slinkman
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit , James Slinkman
IPC分类号： C23F1/00 , B44C1/22 , G03C5/00
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338 , H01L21/32139
摘要： A method of patterning which provides images substantially smaller than that possible by lithographic techniques is provided. In the method of the invention, a substrate has a memory layer and a sacrificial layer formed thereon. An image is patterned onto the memory layer by protecting an edge during an etching step using chemical oxide removal (COR) processes, for example. Another edge is memorized in the layer. The sacrificial layer is removed to expose another memorized edge, which is used to define a pattern in an underlying layer.
摘要翻译：提供了一种通过光刻技术提供显着小于可能的图像的图案化方法。在本发明的方法中，衬底具有形成在其上的存储层和牺牲层。例如，通过使用化学氧化物去除（COR）工艺在蚀刻步骤期间保护边缘，将图像图案化到存储层上。另一个边缘被记住在图层中。去除牺牲层以露出另一个存储的边缘，其用于在下层中定义图案。

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