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1. 发明授权

US06446236B1 Reading encoded information subject to random and transient errors 有权
标题翻译：读取经过随机和瞬态错误的编码信息
公开(公告)号：US06446236B1
公开(公告)日：2002-09-03
申请号：US09418191
申请日：1999-10-13
申请人： Peter McEwen , Hossein Sedarat , Kelly Fitzpatrick
发明人： Peter McEwen , Hossein Sedarat , Kelly Fitzpatrick
IPC分类号： H03M1303
CPC分类号： G11B20/10055 , G11B5/012 , G11B5/09 , G11B20/10009 , G11B20/10296 , G11B20/1833 , G11B2005/0016 , H03M13/41 , H03M13/45 , H04L1/20
摘要： A scheme (apparatus and methods) for recovering encoded data from a data signal representing one or more data symbols and subject to random errors and transient errors. A system in accordance with this scheme includes a transient error detector, a reliability detector, an erasure flagger, and a decoder. The transient error detector is coupled to receive the data signal and is configured to identify one or more characteristics (e.g., a starting location and a midpoint location) of a transient error (e.g., a TA) in the data signal. The reliability detector is configured to compute a reliability metric for each data symbol. The erasure flagger identifies erasures based upon signals received from the transient error detector and the reliability detector. The decoder is configured to treat a data symbol as an erasure or as a valid data symbol based upon the output of the erasure flagger.
摘要翻译：用于从表示一个或多个数据符号的数据信号中恢复编码数据并受到随机误差和瞬态误差的方案（装置和方法）。根据该方案的系统包括瞬态误差检测器，可靠性检测器，擦除标志器和解码器。瞬态误差检测器被耦合以接收数据信号并且被配置为识别数据信号中的瞬态误差（例如，TA）的一个或多个特性（例如起始位置和中点位置）。可靠性检测器被配置为计算每个数据符号的可靠性度量。擦除标志符基于从瞬态误差检测器和可靠性检测器接收的信号来识别擦除。解码器被配置为基于擦除标志符的输出将数据符号视为擦除或作为有效数据符号。

2. 发明授权

US06259384B1 High rate runlength limited codes for 10-bit ECC symbols 有权
标题翻译： 10位ECC符号的高速率游程限制码
公开(公告)号：US06259384B1
公开(公告)日：2001-07-10
申请号：US09350685
申请日：1999-07-09
申请人： Peter McEwen , Kelly Fitzpatrick , Bahjat Zafar
发明人： Peter McEwen , Kelly Fitzpatrick , Bahjat Zafar
IPC分类号： H03M700
CPC分类号： H03M7/46 , G11B5/09
摘要： A methodology for designing and implementing high rate RLL codes is optimized for application to 10-bit ECC symbols, and provides rate 30/31, rate 40/41, rate 50/51 and much higher modulation code rates for use in magnetic recording channels. A relatively small subcode encoding—one easy to implement—is applied to a portion of the input stream, and the resulting base codeword is partitioned into nibbles that, in turn, are interleaved among the unencoded ECC symbols. Code constraints on the subcode word nibbles depend upon the values of adjacent unencoded symbols. The resulting codes provide excellent density and error propagation performance.
摘要翻译：用于设计和实现高速率RLL代码的方法被优化用于应用于10位ECC符号，并且提供用于磁记录通道的速率30/31，速率40/41，速率50/51和更高的调制码率。一个易于实现的相对较小的子代码编码被应用到输入流的一部分，并且所得到的基本码字被分割成半字节，其进而在未经编码的ECC符号之间进行交织。子代码字半字节上的代码约束取决于相邻未编码符号的值。所得到的代码提供了出色的密度和误差传播性能。

3. 发明授权

US07089483B2 Two stage detector having viterbi detector matched to a channel and post processor matched to a channel code 有权
标题翻译：具有与通道和后处理器匹配的维特比检测器的两级检测器与通道代码匹配
公开(公告)号：US07089483B2
公开(公告)日：2006-08-08
申请号：US10793414
申请日：2004-03-04
申请人： Peter McEwen , Kelly Fitzpatrick
发明人： Peter McEwen , Kelly Fitzpatrick
IPC分类号： H03M13/03
CPC分类号： H04L1/0071 , G11B20/18 , G11B2020/1863 , H03M13/41 , H03M13/6331 , H03M13/6343 , H03M13/6502 , H04L1/0054
摘要： A two-stage sampling data detector for a partial response channel having a channel code encoder for encoding user information sequences into blocks of code words in accordance with a predetermined channel block code characterized by a list of most likely error-events comprising impermissible code words. The detector includes a first-stage detector, such as a Viterbi detector, connected to receive samples from the partial response channel and matched to characteristics of the channel and not to the channel code, puts out unchecked bit estimates. A second stage post-processor checks the bit estimates in relation to derived detector decision metrics information and the channel block code, and puts out post-processed bit estimates to a channel code decoder after correcting detected erroneous sequences in accordance with the decision metrics information, information derived from the channel code, and the list of most likely error-events. A method for generating the channel block code is also described.
摘要翻译：一种用于部分响应信道的两级采样数据检测器，具有信道码编码器，用于根据预定信道块码将用户信息序列编码成码字块，其特征在于包含不允许码字的最可能的错误事件列表。该检测器包括第一级检测器，例如维特比检测器，其被连接以接收来自部分响应信道的样本，并且与信道的特征匹配，而不是与信道码匹配，输出未检查的比特估计。第二级后处理器相对于导出的检测器判定度量信息和信道块码检查比特估计，并且根据决策度量信息校正检测到的错误序列之后，向信道码解码器输出后处理比特估计，从信道码导出的信息，以及最可能的错误事件的列表。还描述了用于产生信道块码的方法。

4. 发明申请

US20050246614A1 Trellis-based detection process and system 有权
标题翻译：基于网格的检测过程和系统
公开(公告)号：US20050246614A1
公开(公告)日：2005-11-03
申请号：US11025769
申请日：2004-12-20
申请人： Angelo Dati , Pierandrea Savo , Ezio Iacazio , Kelly Fitzpatrick , Peter McEwen , Bahjat Zafer , John McEwen
发明人： Angelo Dati , Pierandrea Savo , Ezio Iacazio , Kelly Fitzpatrick , Peter McEwen , Bahjat Zafer , John McEwen
IPC分类号： G11B20/10 , H03M13/03
CPC分类号： G11B20/10009
摘要： A method for detecting signals affected by intersymbol interference provides for a path memory being arranged in the form of a trellis admitting survivor paths comprising a first and a second stage. The first stage includes a shift register exchange with a given number of states and a given length λ. At time k-λ, where λ is said given length, the first stage outputs a) a first state SAkk-λ on the survivor path for the best state Ak at time k, while keeping track of the parity for the state at time k-λ for each of the survivor paths in said path memory, and b) a second state SBkk-λ on the survivor path for another state Bk having the same intersymbol interference state as said best state Ak and the opposite priority state. The second stage as is a two-state shift register exchange having a respective memory length Λ, including respective first and second registers. In said respective first and second registers the survivor paths are stored leading to a respective first σ0k and second (σ1k state, the first respective state being equal to said first state SAkk-λ on said best path, whereby the respective first register contains the backend of said best survivor path, while the respective second register contains the backend of an alternative survivor path, the alternative survivor path being for the state at time k with the same intersymbol interference state as said best state and the opposite parity state.
摘要翻译：用于检测受码间干扰影响的信号的方法提供了以包含第一和第二阶段的幸存路径的格状形式布置的路径存储器。第一级包括具有给定数量的状态和给定长度λ的移位寄存器交换。在时间k-lambda，其中λ表示给定长度，第一级输出a）在幸存路径上的最佳状态A的第一状态S k-λ 并且在所述路径存储器中的每个幸存路径的时间k-λ处跟踪奇偶校验的奇偶校验，以及b）第二状态S B S，对于具有与所述最佳状态A 相同的符号间干扰状态的另一状态B 的幸存路径上的SUP>＆lt; k-lambda＆lt; 优先状态。第二级是具有相应存储器长度Lambda的双态移位寄存器交换机，包括相应的第一和第二寄存器。在所述相应的第一和第二寄存器中存储幸存路径，导致相应的第一西格尔和/或第二（sigma）状态，所述第一相应状态等于所述最佳路径上的所述第一状态，所述第一寄存器包含所述第一寄存器的后端，最佳幸存者路径，而相应的第二寄存器包含备用幸存路径的后端，替代的幸存路径用于处于与所述最佳状态和相反奇偶校验状态相同的符号间干扰状态的时间k的状态。

5. 发明授权

US06732328B1 Two stage detector having viterbi detector matched to a channel and post processor matched to a channel code 有权
标题翻译：具有与通道和后处理器匹配的维特比检测器的两级检测器与通道代码匹配
公开(公告)号：US06732328B1
公开(公告)日：2004-05-04
申请号：US09352160
申请日：1999-07-12
申请人： Peter McEwen , Kelly Fitzpatrick
发明人： Peter McEwen , Kelly Fitzpatrick
IPC分类号： H03M1303
CPC分类号： H04L1/0071 , G11B20/18 , G11B2020/1863 , H03M13/41 , H03M13/6331 , H03M13/6343 , H03M13/6502 , H04L1/0054
摘要： A two-stage sampling data detector for a partial response channel having a channel code encoder for encoding user information sequences into blocks of code words in accordance with a predetermined channel block code characterized by a list of most likely error-events comprising impermissible code words. The detector includes a first-stage detector, such as a Viterbi detector, connected to receive samples from the partial response channel and matched to characteristics of the channel and not to the channel code, puts out unchecked bit estimates. A second stage post-processor checks the bit estimates in relation to derived detector decision metrics information and the channel block code, and puts out post-processed bit estimates to a channel code decoder after correcting detected erroneous sequences in accordance with the decision metrics information, information derived from the channel code, and the list of most likely error-events. A method for generating the channel block code is also described.
摘要翻译：一种用于部分响应信道的两级采样数据检测器，具有信道码编码器，用于根据预定信道块码将用户信息序列编码成码字块，其特征在于包含不允许码字的最可能的错误事件列表。该检测器包括第一级检测器，例如维特比检测器，其被连接以接收来自部分响应信道的样本，并且与信道的特征匹配，而不是与信道码匹配，输出未检查的比特估计。第二级后处理器相对于导出的检测器判定度量信息和信道块码检查比特估计，并且根据决策度量信息校正检测到的错误序列之后，向信道码解码器输出后处理比特估计，从信道码导出的信息，以及最可能的错误事件的列表。还描述了用于产生信道块码的方法。

6. 发明授权

US06201485B1 High rate runlength limited codes for 8-bit ECC symbols 有权
标题翻译： 8位ECC符号的高速率游程限制码
公开(公告)号：US06201485B1
公开(公告)日：2001-03-13
申请号：US09350767
申请日：1999-07-09
申请人： Peter McEwen , Bahjat Zafar , Kelly Fitzpatrick
发明人： Peter McEwen , Bahjat Zafar , Kelly Fitzpatrick
IPC分类号： H03M700
CPC分类号： H03M7/00 , G11B5/09 , G11B20/10055 , G11B20/1813 , H03M7/46 , H03M13/31
摘要： A methodology for designing and implementing high rate RLL codes is optimized for application to 8-bit ECC symbols, and provides modulation code rates including rate 32/33; rate 48/49; rate 56/57; rate 72/73; rate 80/81 and other code rates for use in magnetic recording channels. A relatively small subcode encoding—one easy to implement—is applied to a portion of the input stream, and the resulting base codeword is partitioned into nibbles that, in turn, are interleaved among the unencoded ECC symbols. Code constraints on the subcode word nibbles depend upon the values of adjacent unencoded symbols. The resulting codes provide excellent density and error propagation performance.
摘要翻译：用于设计和实现高速率RLL码的方法适用于8位ECC符号，并提供包括速率32/33的调制码率; 率48/49; 率56/57; 率72/73; 速率80/81和用于磁记录通道的其他代码率。一个易于实现的相对较小的子代码编码被应用到输入流的一部分，并且所得到的基本码字被分割成半字节，其进而在未经编码的ECC符号之间进行交织。子代码字半字节上的代码约束取决于相邻未编码符号的值。所得到的代码提供了出色的密度和误差传播性能。

7. 发明授权

US07430704B2 Trellis-based detection process and system 有权
标题翻译：基于网格的检测过程和系统
公开(公告)号：US07430704B2
公开(公告)日：2008-09-30
申请号：US11025769
申请日：2004-12-20
申请人： Angelo Dati , Pierandrea Savo , Ezio Iacazio , Kelly Fitzpatrick , John J. McEwen, legal representative , Bahjat Zafer
发明人： Peter McEwen
IPC分类号： H03M13/03
CPC分类号： G11B20/10009
摘要： A method for detecting signals affected by intersymbol interference provides for a path memory in the form of a trellis admitting survivor paths comprising a first and a second stage. The first stage includes a shift register exchange with a given number of states and a given length λ. The first stage outputs a first state SAkk-λ on the survivor path for the best state Ak, and a second state SBkk-λ on the survivor path for another state Bk. The second stage is configured as a two-state shift register exchange having a respective memory length Λ, including respective first and second registers. In the respective first and second registers the survivor paths are stored leading to a respective first σ0k and second σ1k state, whereby the respective first register contains the backend of the best survivor path, while the respective second register contains the backend of an alternative survivor path.
摘要翻译：用于检测由符号间干扰影响的信号的方法提供以包含第一和第二阶段的遗体路径形式的网格形式的路径存储器。第一级包括具有给定数量的状态和给定长度λ的移位寄存器交换。第一级在幸存路径上输出最佳状态A N的第一状态S K 和第二状态S < 在另一状态B 的幸存路径上的SUP> Bk k-lambda 。第二级被配置为具有各自的存储器长度Lambda的双态移位寄存器交换机，包括相应的第一和第二寄存器。在相应的第一和第二寄存器中存储了幸存路径，导致相应的第一西格尔＆lt; 0＆gt;和第二西格尔＆lt; 1＆gt; / SUB>状态，由此相应的第一寄存器包含最佳幸存路径的后端，而相应的第二寄存器包含备用幸存路径的后端。

8. 发明授权

US06810485B2 Determining the timing of a data signal 失效
标题翻译：确定数据信号的时序
公开(公告)号：US06810485B2
公开(公告)日：2004-10-26
申请号：US09755252
申请日：2001-01-04
申请人： Peter McEwen , Ara Patapoutian , Ke Han
发明人： Peter McEwen , Ara Patapoutian , Ke Han
IPC分类号： G06F104
CPC分类号： G11B20/1403 , G11B20/10296 , G11B20/1426
摘要： Determining a phase error in a data signal includes detecting bits in an original data signal, determining a phase error in the original data signal based on the detected bits, adjusting a clock signal based on the phase error, sampling the original data signal with the clock signal to produce a sampled data signal, and repeating detecting, determining, adjusting and sampling using the sampled data signal instead of the original data signal.
摘要翻译：确定数据信号中的相位误差包括检测原始数据信号中的位，基于检测到的位确定原始数据信号中的相位误差，基于相位误差调整时钟信号，用时钟采样原始数据信号信号以产生采样数据信号，并且使用采样数据信号代替原始数据信号来重复检测，确定，调整和采样。

9. 发明授权

US06738205B1 Self-writing of servo patterns in disk drives 有权
标题翻译：在磁盘驱动器中自动写入伺服模式
公开(公告)号：US06738205B1
公开(公告)日：2004-05-18
申请号：US09903445
申请日：2001-07-08
申请人： Patrick Moran , Tim Everett , Peter McEwen , Mike Moser , Stan Shepherd , Eduardo Gentile Veiga , Murat Erkocevic , Bill Baker
发明人： Patrick Moran , Tim Everett , Peter McEwen , Mike Moser , Stan Shepherd , Eduardo Gentile Veiga , Murat Erkocevic , Bill Baker
IPC分类号： G11B586
CPC分类号： G11B5/865 , G11B5/59633
摘要： A method and system for self-servo writing a disk drive by transferring a servo reference pattern by magnetic printing onto at least one storage surface of a reference disk, wherein a resulting printed reference pattern includes embedded servo information providing servo timing and transducer head position information; assembling the disk drive including the steps of installing at least said disk into the disk drive and enclosing said disk and the data transducers within a housing sealed against particulate contamination from an eternal ambient environment; reading the printed reference pattern from said disk via at least one transducer head to generate a readback signal; sampling the readback signal at a sampling rate to generate a sampled signal; processing the sampled signal waveform specturm to generate a recovered signal including the embedded servo information and a fundamental frequency of the sampled signal; using the servo information from the recovered signal to precisely position and maintain the data transducers at concentric track locations of disk storage surfaces; and self-writing disk drive servo patterns onto the storage surfaces at the concentric track locations with the data transducers in accordance with disk drive servo pattern features.
摘要翻译：一种用于通过磁性印刷将伺服参考图案转移到参考盘的至少一个存储表面上来自动伺服写入磁盘驱动器的方法和系统，其中所得到的打印参考图案包括提供伺服定时和换能器头部位置信息的嵌入式伺服信息 ; 组装磁盘驱动器包括以下步骤：至少将所述磁盘安装到磁盘驱动器中，并将所述磁盘和数据传感器封装在壳体内，密封以防止来自永恒环境环境的颗粒污染物; 经由至少一个换能器头从所述盘读取打印的参考图案以产生回读信号; 以采样率对回读信号进行采样以产生采样信号; 处理采样信号波形谱以产生包括嵌入伺服信息和采样信号的基频的恢复信号; 使用来自恢复信号的伺服信息来精确地将数据传感器定位并保持在盘存储表面的同心轨迹位置; 以及根据磁盘驱动器伺服模式特征，使用数据传感器在同心轨道位置的存储表面上自写盘驱动器伺服模式。

10. 发明授权

US06882604B2 Method and apparatus for utilizing modulation codes that produce maximized sample timing information 有权
标题翻译：用于利用产生最大化采样定时信息的调制码的方法和装置
公开(公告)号：US06882604B2
公开(公告)日：2005-04-19
申请号：US09953845
申请日：2001-09-17
申请人： Ara Patapoutian , Peter McEwen
发明人： Ara Patapoutian , Peter McEwen
IPC分类号： G11B5/09 , G11B20/10 , G11B20/14 , G11B20/18 , G11B7/00 , H04J13/02
CPC分类号： G11B20/10037 , G11B5/09 , G11B20/10009 , G11B20/10296 , G11B20/1403 , G11B20/1426 , G11B20/1833
摘要： The invention is a modulation system that encodes symbols in accordance with a modulation code which, for a given communications channel, produces a signal that at the decoder includes maximized sample timing information in each encoded symbol. For systems that use PLLs to control a sample timing clock, the sample timing information is the average or squared slope. The modulation code used for a given system is selected based on the target response h(x) of the associated communications channel, such that h (x)*rk exceeds a predetermined threshold value, where “*” represents convolution and rk is a modulation code symbol. To reduce the bit overhead, or code rate, the inventive modulation system provides more modulation code symbols at the start of a data block, or sector, when system jitter is expected to be relatively high in response, for example, to the movement of a read head. The system then includes fewer modulation code symbols later in the block, when the system jitter associated with a read or receive operation is reduced. The system thus provides sufficient timing information to minimize PLL jitter.
摘要翻译：本发明是一种调制系统，其根据调制码对符号进行编码，对于给定的通信信道，调制码产生一个在解码器处包括每个编码符号中的最大化采样定时信息的信号。对于使用PLL来控制采样定时时钟的系统，采样定时信息是平均或平方斜率。用于给定系统的调制码基于相关通信信道的目标响应h（x）被选择，使得h（x）* r≠k超过预定阈值，其中“* “表示卷积，r＆lt; k＆gt;是调制码符号。为了减少比特开销或码率，本发明的调制系统在数据块或扇区的开始处提供更多的调制码符号，当系统抖动被预期相对较高时，例如对于a的移动读头当与读取或接收操作相关联的系统抖动减小时，该系统随后在块中包括更少的调制码符号。因此，该系统提供足够的定时信息以最小化PLL抖动。

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