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1. 发明申请

US20050246614A1 Trellis-based detection process and system 有权
标题翻译：基于网格的检测过程和系统
公开(公告)号：US20050246614A1
公开(公告)日：2005-11-03
申请号：US11025769
申请日：2004-12-20
申请人： Angelo Dati , Pierandrea Savo , Ezio Iacazio , Kelly Fitzpatrick , Peter McEwen , Bahjat Zafer , John McEwen
发明人： Angelo Dati , Pierandrea Savo , Ezio Iacazio , Kelly Fitzpatrick , Peter McEwen , Bahjat Zafer , John McEwen
IPC分类号： G11B20/10 , H03M13/03
CPC分类号： G11B20/10009
摘要： A method for detecting signals affected by intersymbol interference provides for a path memory being arranged in the form of a trellis admitting survivor paths comprising a first and a second stage. The first stage includes a shift register exchange with a given number of states and a given length λ. At time k-λ, where λ is said given length, the first stage outputs a) a first state SAkk-λ on the survivor path for the best state Ak at time k, while keeping track of the parity for the state at time k-λ for each of the survivor paths in said path memory, and b) a second state SBkk-λ on the survivor path for another state Bk having the same intersymbol interference state as said best state Ak and the opposite priority state. The second stage as is a two-state shift register exchange having a respective memory length Λ, including respective first and second registers. In said respective first and second registers the survivor paths are stored leading to a respective first σ0k and second (σ1k state, the first respective state being equal to said first state SAkk-λ on said best path, whereby the respective first register contains the backend of said best survivor path, while the respective second register contains the backend of an alternative survivor path, the alternative survivor path being for the state at time k with the same intersymbol interference state as said best state and the opposite parity state.
摘要翻译：用于检测受码间干扰影响的信号的方法提供了以包含第一和第二阶段的幸存路径的格状形式布置的路径存储器。第一级包括具有给定数量的状态和给定长度λ的移位寄存器交换。在时间k-lambda，其中λ表示给定长度，第一级输出a）在幸存路径上的最佳状态A的第一状态S k-λ 并且在所述路径存储器中的每个幸存路径的时间k-λ处跟踪奇偶校验的奇偶校验，以及b）第二状态S B S，对于具有与所述最佳状态A 相同的符号间干扰状态的另一状态B 的幸存路径上的SUP>＆lt; k-lambda＆lt; 优先状态。第二级是具有相应存储器长度Lambda的双态移位寄存器交换机，包括相应的第一和第二寄存器。在所述相应的第一和第二寄存器中存储幸存路径，导致相应的第一西格尔和/或第二（sigma）状态，所述第一相应状态等于所述最佳路径上的所述第一状态，所述第一寄存器包含所述第一寄存器的后端，最佳幸存者路径，而相应的第二寄存器包含备用幸存路径的后端，替代的幸存路径用于处于与所述最佳状态和相反奇偶校验状态相同的符号间干扰状态的时间k的状态。

2. 发明授权

US07089483B2 Two stage detector having viterbi detector matched to a channel and post processor matched to a channel code 有权
标题翻译：具有与通道和后处理器匹配的维特比检测器的两级检测器与通道代码匹配
公开(公告)号：US07089483B2
公开(公告)日：2006-08-08
申请号：US10793414
申请日：2004-03-04
申请人： Peter McEwen , Kelly Fitzpatrick
发明人： Peter McEwen , Kelly Fitzpatrick
IPC分类号： H03M13/03
CPC分类号： H04L1/0071 , G11B20/18 , G11B2020/1863 , H03M13/41 , H03M13/6331 , H03M13/6343 , H03M13/6502 , H04L1/0054
摘要： A two-stage sampling data detector for a partial response channel having a channel code encoder for encoding user information sequences into blocks of code words in accordance with a predetermined channel block code characterized by a list of most likely error-events comprising impermissible code words. The detector includes a first-stage detector, such as a Viterbi detector, connected to receive samples from the partial response channel and matched to characteristics of the channel and not to the channel code, puts out unchecked bit estimates. A second stage post-processor checks the bit estimates in relation to derived detector decision metrics information and the channel block code, and puts out post-processed bit estimates to a channel code decoder after correcting detected erroneous sequences in accordance with the decision metrics information, information derived from the channel code, and the list of most likely error-events. A method for generating the channel block code is also described.
摘要翻译：一种用于部分响应信道的两级采样数据检测器，具有信道码编码器，用于根据预定信道块码将用户信息序列编码成码字块，其特征在于包含不允许码字的最可能的错误事件列表。该检测器包括第一级检测器，例如维特比检测器，其被连接以接收来自部分响应信道的样本，并且与信道的特征匹配，而不是与信道码匹配，输出未检查的比特估计。第二级后处理器相对于导出的检测器判定度量信息和信道块码检查比特估计，并且根据决策度量信息校正检测到的错误序列之后，向信道码解码器输出后处理比特估计，从信道码导出的信息，以及最可能的错误事件的列表。还描述了用于产生信道块码的方法。

3. 发明授权

US06259384B1 High rate runlength limited codes for 10-bit ECC symbols 有权
标题翻译： 10位ECC符号的高速率游程限制码
公开(公告)号：US06259384B1
公开(公告)日：2001-07-10
申请号：US09350685
申请日：1999-07-09
申请人： Peter McEwen , Kelly Fitzpatrick , Bahjat Zafar
发明人： Peter McEwen , Kelly Fitzpatrick , Bahjat Zafar
IPC分类号： H03M700
CPC分类号： H03M7/46 , G11B5/09
摘要： A methodology for designing and implementing high rate RLL codes is optimized for application to 10-bit ECC symbols, and provides rate 30/31, rate 40/41, rate 50/51 and much higher modulation code rates for use in magnetic recording channels. A relatively small subcode encoding—one easy to implement—is applied to a portion of the input stream, and the resulting base codeword is partitioned into nibbles that, in turn, are interleaved among the unencoded ECC symbols. Code constraints on the subcode word nibbles depend upon the values of adjacent unencoded symbols. The resulting codes provide excellent density and error propagation performance.
摘要翻译：用于设计和实现高速率RLL代码的方法被优化用于应用于10位ECC符号，并且提供用于磁记录通道的速率30/31，速率40/41，速率50/51和更高的调制码率。一个易于实现的相对较小的子代码编码被应用到输入流的一部分，并且所得到的基本码字被分割成半字节，其进而在未经编码的ECC符号之间进行交织。子代码字半字节上的代码约束取决于相邻未编码符号的值。所得到的代码提供了出色的密度和误差传播性能。

4. 发明授权

US06732328B1 Two stage detector having viterbi detector matched to a channel and post processor matched to a channel code 有权
标题翻译：具有与通道和后处理器匹配的维特比检测器的两级检测器与通道代码匹配
公开(公告)号：US06732328B1
公开(公告)日：2004-05-04
申请号：US09352160
申请日：1999-07-12
申请人： Peter McEwen , Kelly Fitzpatrick
发明人： Peter McEwen , Kelly Fitzpatrick
IPC分类号： H03M1303
CPC分类号： H04L1/0071 , G11B20/18 , G11B2020/1863 , H03M13/41 , H03M13/6331 , H03M13/6343 , H03M13/6502 , H04L1/0054
摘要： A two-stage sampling data detector for a partial response channel having a channel code encoder for encoding user information sequences into blocks of code words in accordance with a predetermined channel block code characterized by a list of most likely error-events comprising impermissible code words. The detector includes a first-stage detector, such as a Viterbi detector, connected to receive samples from the partial response channel and matched to characteristics of the channel and not to the channel code, puts out unchecked bit estimates. A second stage post-processor checks the bit estimates in relation to derived detector decision metrics information and the channel block code, and puts out post-processed bit estimates to a channel code decoder after correcting detected erroneous sequences in accordance with the decision metrics information, information derived from the channel code, and the list of most likely error-events. A method for generating the channel block code is also described.
摘要翻译：一种用于部分响应信道的两级采样数据检测器，具有信道码编码器，用于根据预定信道块码将用户信息序列编码成码字块，其特征在于包含不允许码字的最可能的错误事件列表。该检测器包括第一级检测器，例如维特比检测器，其被连接以接收来自部分响应信道的样本，并且与信道的特征匹配，而不是与信道码匹配，输出未检查的比特估计。第二级后处理器相对于导出的检测器判定度量信息和信道块码检查比特估计，并且根据决策度量信息校正检测到的错误序列之后，向信道码解码器输出后处理比特估计，从信道码导出的信息，以及最可能的错误事件的列表。还描述了用于产生信道块码的方法。

5. 发明授权

US06446236B1 Reading encoded information subject to random and transient errors 有权
标题翻译：读取经过随机和瞬态错误的编码信息
公开(公告)号：US06446236B1
公开(公告)日：2002-09-03
申请号：US09418191
申请日：1999-10-13
申请人： Peter McEwen , Hossein Sedarat , Kelly Fitzpatrick
发明人： Peter McEwen , Hossein Sedarat , Kelly Fitzpatrick
IPC分类号： H03M1303
CPC分类号： G11B20/10055 , G11B5/012 , G11B5/09 , G11B20/10009 , G11B20/10296 , G11B20/1833 , G11B2005/0016 , H03M13/41 , H03M13/45 , H04L1/20
摘要： A scheme (apparatus and methods) for recovering encoded data from a data signal representing one or more data symbols and subject to random errors and transient errors. A system in accordance with this scheme includes a transient error detector, a reliability detector, an erasure flagger, and a decoder. The transient error detector is coupled to receive the data signal and is configured to identify one or more characteristics (e.g., a starting location and a midpoint location) of a transient error (e.g., a TA) in the data signal. The reliability detector is configured to compute a reliability metric for each data symbol. The erasure flagger identifies erasures based upon signals received from the transient error detector and the reliability detector. The decoder is configured to treat a data symbol as an erasure or as a valid data symbol based upon the output of the erasure flagger.
摘要翻译：用于从表示一个或多个数据符号的数据信号中恢复编码数据并受到随机误差和瞬态误差的方案（装置和方法）。根据该方案的系统包括瞬态误差检测器，可靠性检测器，擦除标志器和解码器。瞬态误差检测器被耦合以接收数据信号并且被配置为识别数据信号中的瞬态误差（例如，TA）的一个或多个特性（例如起始位置和中点位置）。可靠性检测器被配置为计算每个数据符号的可靠性度量。擦除标志符基于从瞬态误差检测器和可靠性检测器接收的信号来识别擦除。解码器被配置为基于擦除标志符的输出将数据符号视为擦除或作为有效数据符号。

6. 发明授权

US06201485B1 High rate runlength limited codes for 8-bit ECC symbols 有权
标题翻译： 8位ECC符号的高速率游程限制码
公开(公告)号：US06201485B1
公开(公告)日：2001-03-13
申请号：US09350767
申请日：1999-07-09
申请人： Peter McEwen , Bahjat Zafar , Kelly Fitzpatrick
发明人： Peter McEwen , Bahjat Zafar , Kelly Fitzpatrick
IPC分类号： H03M700
CPC分类号： H03M7/00 , G11B5/09 , G11B20/10055 , G11B20/1813 , H03M7/46 , H03M13/31
摘要： A methodology for designing and implementing high rate RLL codes is optimized for application to 8-bit ECC symbols, and provides modulation code rates including rate 32/33; rate 48/49; rate 56/57; rate 72/73; rate 80/81 and other code rates for use in magnetic recording channels. A relatively small subcode encoding—one easy to implement—is applied to a portion of the input stream, and the resulting base codeword is partitioned into nibbles that, in turn, are interleaved among the unencoded ECC symbols. Code constraints on the subcode word nibbles depend upon the values of adjacent unencoded symbols. The resulting codes provide excellent density and error propagation performance.
摘要翻译：用于设计和实现高速率RLL码的方法适用于8位ECC符号，并提供包括速率32/33的调制码率; 率48/49; 率56/57; 率72/73; 速率80/81和用于磁记录通道的其他代码率。一个易于实现的相对较小的子代码编码被应用到输入流的一部分，并且所得到的基本码字被分割成半字节，其进而在未经编码的ECC符号之间进行交织。子代码字半字节上的代码约束取决于相邻未编码符号的值。所得到的代码提供了出色的密度和误差传播性能。

7. 发明申请

US20130111297A1 Systems and Methods for Symbol Selective Scaling in a Data Processing Circuit 审中-公开
标题翻译：数据处理电路中符号选择性缩放的系统和方法
公开(公告)号：US20130111297A1
公开(公告)日：2013-05-02
申请号：US13284826
申请日：2011-10-28
申请人： Weijun Tan , Kelly Fitzpatrick , Shaohua Yang , Fan Zhang
发明人： Weijun Tan , Kelly Fitzpatrick , Shaohua Yang , Fan Zhang
IPC分类号： H03M13/09
CPC分类号： H03M13/1128 , H03M13/1171 , H03M13/3723 , H03M13/3746 , H03M13/3753 , H03M13/41 , H03M13/6331 , H03M13/6337 , H03M13/658
摘要： Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing system is discussed that includes: a data detector circuit, a symbol selective scaling circuit, and a data decoder circuit. The data detector circuit is operable to apply a data detection algorithm to a data input guided by a first data set derived from a decoded output to yield a detected output. The symbol selective scaling circuit is operable to selectively scale one or more symbols of a second data set derived from the detected output to yield a scaled data set. The data decoder circuit operable to apply a data decode algorithm to a third data set derived from the scaled data set to yield the decoded output.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。作为示例，讨论了包括数据检测器电路，符号选择缩放电路和数据解码器电路的数据处理系统。数据检测器电路可操作以将数据检测算法应用于由从解码输出导出的第一数据集引导的数据输入，以产生检测到的输出。符号选择性缩放电路可操作以选择性地缩放从检测到的输出导出的第二数据集的一个或多个符号，以产生缩放的数据集。数据解码器电路可操作以将数据解码算法应用于从缩放数据集导出的第三数据集，以产生解码输出。

8. 发明申请

US20110029837A1 Systems and Methods for Phase Dependent Data Detection in Iterative Decoding 有权
标题翻译：迭代解码中相关数据检测的系统和方法
公开(公告)号：US20110029837A1
公开(公告)日：2011-02-03
申请号：US12512235
申请日：2009-07-30
申请人： Shaohua Yang , Zongwang Li , Weijun Tan , Kelly Fitzpatrick
发明人： Shaohua Yang , Zongwang Li , Weijun Tan , Kelly Fitzpatrick
IPC分类号： H03M13/00 , G11C29/00
CPC分类号： G11B20/1803 , G11B20/10222 , G11B2020/10722 , G11B2020/10759 , G11B2020/1287 , G11B2020/1289 , G11B2020/185 , H03M13/1105 , H03M13/27 , H03M13/2732 , H03M13/3905 , H03M13/4146 , H03M13/458 , H03M13/6343
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes a first data detection circuit that applies a phase dependent data detection algorithm to a data set such that a first output of the first data detection circuit varies depending upon a phase of the data set presented to the first data detection circuit. A first phase of the data set is presented to the first data detection circuit. The circuits further include a decoder circuit that applies a decoding algorithm to the first output to yield a decoded output, and a phase shift circuit that phase shifts the decoded output such that a second phase of the data set is provided as a phase shifted output. A second detection circuit applies a phase dependent data detection algorithm to the phase shifted output such that a second output of the second data detection circuit varies from the first output at least in part due to a different phase of the data set presented to the second data detection circuit.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了一种数据处理电路，其包括第一数据检测电路，该第一数据检测电路将相关数据检测算法应用于数据组，使得第一数据检测电路的第一输出根据所呈现的数据集的相位而变化第一数据检测电路。将数据集的第一阶段呈现给第一数据检测电路。这些电路还包括对第一输出应用解码算法以产生解码输出的解码器电路，以及相位移动电路，使得解码输出相移，使得提供数据组的第二相作为相移输出。第二检测电路将相位相关数据检测算法应用于相移输出，使得第二数据检测电路的第二输出至少部分地由于呈现给第二数据的数据集的相位而从第一输出变化检测电路。

9. 发明授权

US08773790B2 Systems and methods for dynamic scaling in a read data processing system 有权
标题翻译：读取数据处理系统中动态缩放的系统和方法
公开(公告)号：US08773790B2
公开(公告)日：2014-07-08
申请号：US13126748
申请日：2009-04-28
申请人： Weijun Tan , Shaohua Yang , Kelly Fitzpatrick , Zongwang Li , Hao Zhong
发明人： Weijun Tan , Shaohua Yang , Kelly Fitzpatrick , Zongwang Li , Hao Zhong
IPC分类号： G11B5/09 , G11B20/10 , G11B7/00 , G06F7/00 , G06F15/00
CPC分类号： G11B20/1803 , G11B20/10222 , G11B2020/10722 , G11B2020/10759 , G11B2020/1287 , G11B2020/1289 , G11B2020/185 , H03M13/1111 , H03M13/112 , H03M13/2957 , H03M13/3746 , H03M13/6343
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a decoder circuit providing a decoded output, and a dynamic scalar calculation circuit that determines a first dynamic scaling value and a second dynamic scaling value based at least in part on the decoded output. A first multiplier circuit multiplies the decoded output by the first dynamic scaling value and provides a first scaled output. A detector circuit receives the first scaled output and provides a detected output. A second multiplier circuit multiplies the detected output by the second dynamic scaling value and provides a second scaled output.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了包括提供解码输出的解码器电路的数据处理系统，以及至少部分地基于解码输出来确定第一动态缩放值和第二动态缩放值的动态标量计算电路。第一乘法器电路将解码输出乘以第一动态缩放值并提供第一缩放输出。检测器电路接收第一缩放输出并提供检测输出。第二乘法器电路将检测到的输出乘以第二动态缩放值，并提供第二缩放输出。

10. 发明申请

US20090235116A1 Systems and Methods for Regenerating Data from a Defective Medium 失效
标题翻译：从有缺陷的介质再生数据的系统和方法
公开(公告)号：US20090235116A1
公开(公告)日：2009-09-17
申请号：US12111902
申请日：2008-04-29
申请人： Weijun Tan , Shaohua Yang , George Mathew , Kelly Fitzpatrick , Hao Zhong , Yuan Xing Lee
发明人： Weijun Tan , Shaohua Yang , George Mathew , Kelly Fitzpatrick , Hao Zhong , Yuan Xing Lee
IPC分类号： G06F11/07
CPC分类号： G06F11/0793 , G06F11/0727 , G11B20/1816
摘要： Various embodiments of the present invention provide systems and methods for data regeneration. For example, a system for data regeneration is disclosed that includes a data input derived from the medium. A data detector and a data recovery system receive the data input. The data detector provides a first soft output, and the data recovery system provides a second soft output. The first soft output and the second soft output are provided to a multiplexer. A media defect detector performs a media defect detection process, and provides a defect flag that indicates whether the data input is derived form a defective portion of the medium. The defect flag is provided to the multiplexer where it is used to select whether the first soft output or the second soft output is provides as an extrinsic output.
摘要翻译：本发明的各种实施例提供了用于数据再生的系统和方法。例如，公开了一种用于数据再生的系统，其包括从介质导出的数据输入。数据检测器和数据恢复系统接收数据输入。数据检测器提供第一软输出，数据恢复系统提供第二软输出。第一软输出和第二软输出被提供给多路复用器。介质缺陷检测器执行介质缺陷检测处理，并且提供指示数据输入是否从介质的缺陷部分导出的缺陷标志。缺陷标志被提供给多路复用器，其中它用于选择第一软输出或第二软输出是作为外在输出提供。

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