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1. 发明授权

US08042260B2 Methods of forming inductors on integrated circuits 有权
标题翻译：在集成电路上形成电感器的方法
公开(公告)号：US08042260B2
公开(公告)日：2011-10-25
申请号：US12250385
申请日：2008-10-13
申请人： Peter J. Hopper , Peter Johnson , Peter Smeys , Andrei Papou
发明人： Peter J. Hopper , Peter Johnson , Peter Smeys , Andrei Papou
IPC分类号： H01F7/06
CPC分类号： H01L23/5227 , H01F17/0006 , H01F41/046 , H01L2924/0002 , Y10T29/4902 , Y10T29/49071 , Y10T29/49073 , Y10T29/49075 , Y10T29/49124 , Y10T29/4913 , H01L2924/00
摘要： The claimed invention pertains to methods of forming one or more inductors on a semiconductor substrate. In one embodiment, a method of forming an array of inductor core elements on a semiconductor substrate that includes integrated circuits is disclosed. A first set of spaced apart metallic core elements are formed over the substrate. Isolation sidewalls are then formed on side surfaces of the core elements. Afterward, a second set of metallic core elements are formed over the substrate. The first and second sets of core elements are substantially co-planar and interleaved such that only the isolation sidewalls separate adjacent core elements. Particular embodiments involve other processing operations, such as the selective electroplating of different types of metal to form core elements and/or the deposition and etching away of an isolation layer to form isolation sidewalls on the core elements.
摘要翻译：所要求保护的发明涉及在半导体衬底上形成一个或多个电感器的方法。在一个实施例中，公开了一种在包括集成电路的半导体衬底上形成电感器芯元件阵列的方法。第一组间隔开的金属芯元件形成在衬底上。然后在芯元件的侧表面上形成隔离侧壁。之后，在衬底上形成第二组金属芯元件。第一和第二组芯元件基本上是共面的和交错的，使得只有隔离侧壁分隔相邻的芯元件。具体实施例涉及其他处理操作，例如不同类型的金属的选择性电镀以形成核心元件和/或沉积和蚀刻离开隔离层以在核心元件上形成隔离侧壁。

2. 发明授权

US07755463B2 Integrated circuits with inductors 有权
标题翻译：集成电路与电感器
公开(公告)号：US07755463B2
公开(公告)日：2010-07-13
申请号：US12250382
申请日：2008-10-13
申请人： Peter J. Hopper , Peter Johnson , Peter Smeys , Andrei Papou
发明人： Peter J. Hopper , Peter Johnson , Peter Smeys , Andrei Papou
IPC分类号： H01F5/00 , H01F27/28 , H01F21/06 , H01F27/30 , H01F27/24 , H02M1/00 , G05F1/00
CPC分类号： H01L23/5227 , H01F17/0006 , H01F41/046 , H01L2924/0002 , Y10T29/4902 , Y10T29/49071 , Y10T29/49073 , Y10T29/49075 , Y10T29/49124 , Y10T29/4913 , H01L2924/00
摘要： The claimed invention relates to arrangements of inductors and integrated circuit dice. One embodiment pertains to an integrated circuit die that has an inductor formed thereon. The inductor includes an inductor winding having a winding input and a winding output. The inductor also comprises an inductor core array having at least first and second sets of inductor core elements that are magnetically coupled with the inductor winding. Each inductor core element in the first set of inductor core elements is formed from a first metallic material. Each inductor core element in the second set of inductor core elements is formed from a second metallic material that has a different magnetic coercivity than the first magnetic material. The inductor further comprises a set of spacers that electrically isolate the inductor core elements. Some embodiments involve multiple inductor windings and/or multiple inductor core elements that magnetically interact in various ways. Particular embodiments involve core elements having different compositions and/or sizes.
摘要翻译：所要求保护的发明涉及电感器和集成电路芯片的布置。一个实施例涉及其上形成有电感器的集成电路管芯。电感器包括具有绕组输入和绕组输出的电感器绕组。电感器还包括电感器芯阵列，其具有与电感器绕组磁耦合的至少第一组和第二组电感器芯体元件。第一组电感器芯元件中的每个电感器芯体元件由第一金属材料形成。第二组电感器芯元件中的每个电感器芯体元件由具有与第一磁性材料不同的磁矫顽力的第二金属材料形成。电感器还包括一组将电感器芯元件电隔离的间隔件。一些实施例涉及以各种方式磁性相互作用的多个电感器绕组和/或多个电感器核心元件。具体实施方案涉及具有不同组成和/或尺寸的核心元件。

3. 发明申请

US20090040000A1 INTEGRATED CIRCUITS WITH INDUCTORS 有权
标题翻译：集成电路与电感器
公开(公告)号：US20090040000A1
公开(公告)日：2009-02-12
申请号：US12250382
申请日：2008-10-13
申请人： Peter J. Hopper , Peter Johnson , Peter Smeys , Andrei Papou
发明人： Peter J. Hopper , Peter Johnson , Peter Smeys , Andrei Papou
IPC分类号： H01F5/00
CPC分类号： H01L23/5227 , H01F17/0006 , H01F41/046 , H01L2924/0002 , Y10T29/4902 , Y10T29/49071 , Y10T29/49073 , Y10T29/49075 , Y10T29/49124 , Y10T29/4913 , H01L2924/00
摘要： The claimed invention relates to arrangements of inductors and integrated circuit dice. One embodiment pertains to an integrated circuit die that has an inductor formed thereon. The inductor includes an inductor winding having a winding input and a winding output. The inductor also comprises an inductor core array having at least first and second sets of inductor core elements that are magnetically coupled with the inductor winding. Each inductor core element in the first set of inductor core elements is formed from a first metallic material. Each inductor core element in the second set of inductor core elements is formed from a second metallic material that has a different magnetic coercivity than the first magnetic material. The inductor further comprises a set of spacers that electrically isolate the inductor core elements. Some embodiments involve multiple inductor windings and/or multiple inductor core elements that magnetically interact in various ways. Particular embodiments involve core elements having different compositions and/or sizes.
摘要翻译：所要求保护的发明涉及电感器和集成电路芯片的布置。一个实施例涉及其上形成有电感器的集成电路管芯。电感器包括具有绕组输入和绕组输出的电感器绕组。电感器还包括电感器芯阵列，其具有与电感器绕组磁耦合的至少第一组和第二组电感器芯体元件。第一组电感器芯元件中的每个电感器芯体元件由第一金属材料形成。第二组电感器芯元件中的每个电感器芯体元件由具有与第一磁性材料不同的磁矫顽力的第二金属材料形成。电感器还包括一组将电感器芯元件电隔离的间隔件。一些实施例涉及以各种方式磁性相互作用的多个电感器绕组和/或多个电感器核心元件。具体实施方案涉及具有不同组成和/或尺寸的核心元件。

4. 发明授权

US07468899B1 Apparatus and method for wafer level fabrication of high value inductors on semiconductor integrated circuits 有权
标题翻译：用于在半导体集成电路上制造高价值电感器的晶片级的装置和方法
公开(公告)号：US07468899B1
公开(公告)日：2008-12-23
申请号：US11621424
申请日：2007-01-09
申请人： Peter J. Hopper , Peter Johnson , Peter Smeys , Andrei Papou
发明人： Peter J. Hopper , Peter Johnson , Peter Smeys , Andrei Papou
IPC分类号： G05F1/59 , G05F1/618
CPC分类号： H01L23/5227 , H01F17/0006 , H01F41/046 , H01L2924/0002 , Y10T29/4902 , Y10T29/49071 , Y10T29/49073 , Y10T29/49075 , Y10T29/49124 , Y10T29/4913 , H01L2924/00
摘要： An apparatus and method for wafer level fabrication of high value inductors directly on top of semiconductor integrated circuits is disclosed. The integrated circuit includes a plurality of regulator circuits, each of the regulator circuits having an input node configured to receive a plurality of pulsed input signals having a predetermined duty cycle and a plurality of inductor windings associated with each of the plurality of regulator circuits respectively. The integrated circuit also includes a core array having a plurality of core elements. The plurality of core elements are positioned adjacent to and magnetically coupled with one or more of the plurality of inductor windings. An output node is electrically coupled to the plurality of inductor windings. The output signal at the output node is the sum of the instantaneous voltage on each of the inductor windings associated with the plurality of regulator circuits respectively. The integrated circuit also includes a phase control circuit coupled to the plurality of regulator circuits. The phase control circuit controls the phase of the plurality of pulsed input signals received at the plurality of the regulator circuits to control the output signal at the output node.
摘要翻译：公开了一种直接在半导体集成电路之上晶圆级制造高值电感器的装置和方法。集成电路包括多个调节器电路，每个调节器电路具有被配置为分别接收具有预定占空比的多个脉冲输入信号和与多个调节器电路中的每一个相关联的多个电感器绕组的输入节点。集成电路还包括具有多个核心元件的芯阵列。多个芯元件被定位成与多个电感器绕组中的一个或多个相邻并且磁耦合。输出节点电耦合到多个电感器绕组。输出节点处的输出信号分别是与多个调节器电路相关联的每个电感器绕组上的瞬时电压之和。集成电路还包括耦合到多个调节器电路的相位控制电路。相位控制电路控制在多个调节器电路处接收的多个脉冲输入信号的相位，以控制输出节点处的输出信号。

5. 发明授权

US07897472B2 Apparatus and method for wafer level fabrication of high value inductors on semiconductor integrated circuits 有权
标题翻译：用于在半导体集成电路上制造高价值电感器的晶片级的装置和方法
公开(公告)号：US07897472B2
公开(公告)日：2011-03-01
申请号：US12624259
申请日：2009-11-23
申请人： Peter J. Hopper , Peter Johnson , Kyuwoon Hwang , Andrei Papou
发明人： Peter J. Hopper , Peter Johnson , Kyuwoon Hwang , Andrei Papou
IPC分类号： H01L21/20
CPC分类号： H01L23/645 , H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/19015 , H01L2924/19104 , H01L2924/00
摘要： Methods for forming multiple inductors on a semiconductor wafer are described. A plating layer and a photoresist layer are applied over a semiconductor wafer. Recess regions are etched in the photoresist layer using photolithographic techniques, which exposes portions of the underlying plating layer. Metal is electroplated into the recess regions in the photoresist layer to form multiple magnetic core inductor members. A dielectric insulating layer is applied over the magnetic core inductor members. Additional plating and photoresist layers are applied over the dielectric insulating layer. Recess regions are formed in the newly applied photoresist layer. Electroplating is used to form inductor windings in the recess regions. Optionally, a magnetic paste can be applied over the inductor coils.
摘要翻译：描述了在半导体晶片上形成多个电感器的方法。将镀层和光致抗蚀剂层施加在半导体晶片上。使用光刻技术在光致抗蚀剂层中蚀刻凹陷区域，其暴露下面的镀层的部分。将金属电镀到光致抗蚀剂层的凹陷区域中以形成多个磁芯电感器构件。介质绝缘层施加在磁芯电感器部件上。在电介质绝缘层上施加附加的电镀和光致抗蚀剂层。在新施加的光致抗蚀剂层中形成凹陷区域。电镀用于在凹陷区域形成电感线圈。可选地，可以在电感线圈上施加磁性糊。

6. 发明授权

US08205324B2 Method of fabricating an inductor structure 有权
标题翻译：制造电感器结构的方法
公开(公告)号：US08205324B2
公开(公告)日：2012-06-26
申请号：US12275599
申请日：2008-11-21
申请人： Peter Smeys , Peter Johnson , Andrei Papou
发明人： Peter Smeys , Peter Johnson , Andrei Papou
IPC分类号： H01F3/00 , H01F41/02
CPC分类号： H01F17/0006 , H01F41/046 , H01F2017/0066 , H01L23/5227 , H01L2924/0002 , Y10T29/49005 , Y10T29/4902 , Y10T29/49069 , Y10T29/49071 , Y10T29/49073 , Y10T29/49144 , H01L2924/00
摘要： A damascene process is utilized to fabricate the segmented magnetic core elements of an integrated circuit inductor structure. The magnetic core is electroplated from a seed layer that is conformal with a permanent dielectric mold that results in sidewall plating defining an easy magnetic axis. The hard axis runs parallel to the longitudinal axis of the core and the inductor coils are orthogonal to the core's longitudinal axis. The magnetic field generated by the inductor coils is, therefore, parallel and self-aligned to the hard magnetic axis. The easy axis is enhanced by electroplating in an applied magnetic field parallel to the easy axis.
摘要翻译：利用镶嵌工艺来制造集成电路电感器结构的分段磁芯元件。磁芯从与保持永久介电模具的种子层电镀，导致侧壁镀层限定易磁轴。硬轴平行于芯的纵轴延伸，并且电感线圈与芯的纵向轴线正交。因此，由电感线圈产生的磁场与硬磁轴平行和自对准。通过在平行于容易轴的施加磁场中电镀来增强易轴。

7. 发明授权

US07584533B2 Method of fabricating an inductor structure on an integrated circuit structure 有权
标题翻译：在集成电路结构上制造电感器结构的方法
公开(公告)号：US07584533B2
公开(公告)日：2009-09-08
申请号：US11973861
申请日：2007-10-10
申请人： Peter Smeys , Peter Johnson , Andrei Papou
发明人： Peter Smeys , Peter Johnson , Andrei Papou
IPC分类号： H01F3/00 , H01F41/02
CPC分类号： H01F17/0006 , H01F41/046 , H01F2017/0066 , H01L23/5227 , H01L2924/0002 , Y10T29/49005 , Y10T29/4902 , Y10T29/49069 , Y10T29/49071 , Y10T29/49073 , Y10T29/49144 , H01L2924/00
摘要： A damascene process is utilized to fabricate the segmented magnetic core elements of an integrated circuit inductor structure. The magnetic core is electroplated from a seed layer that is conformal with a permanent dielectric mold that results in sidewall plating defining an easy magnetic axis. The hard axis runs parallel to the longitudinal axis of the core and the inductor coils are orthogonal to the core's longitudinal axis. The magnetic field generated by the inductor coils is, therefore, parallel and self-aligned to the hard magnetic axis. The easy axis can be enhanced by electroplating in an applied magnetic field parallel to the easy axis.
摘要翻译：利用镶嵌工艺来制造集成电路电感器结构的分段磁芯元件。磁芯从与保持永久介电模具的种子层电镀，导致侧壁镀层限定易磁轴。硬轴平行于芯的纵轴延伸，并且电感线圈与芯的纵向轴线正交。因此，由电感线圈产生的磁场与硬磁轴平行和自对准。可以通过在平行于容易轴的施加磁场中电镀来增强易轴。

8. 发明授权

US08314676B1 Method of making a controlled seam laminated magnetic core for high frequency on-chip power inductors 有权
标题翻译：制造用于高频片上功率电感器的可控缝层压磁芯的方法
公开(公告)号：US08314676B1
公开(公告)日：2012-11-20
申请号：US13098656
申请日：2011-05-02
申请人： Peter Smeys , Andrei Papou , Peter Johnson , Anuraag Mohan
发明人： Peter Smeys , Andrei Papou , Peter Johnson , Anuraag Mohan
IPC分类号： H01F5/00 , H01F7/06 , H01L27/08
CPC分类号： H01F17/0033 , H01F41/046 , Y10T29/4902 , Y10T29/49075 , Y10T29/49078
摘要： A controlled seam magnetic core lamination utilizable in an inductor structure includes a magnetic base and first and second spaced-apart magnetic sidewalls extending substantially orthogonally from the base to define a seam therebetween. The controlled seam magnetic core lamination is utilizable in an inductor structure that includes: a non-conductive lower mold; a plurality of spaced-apart controlled seam lower laminations formed in the lower mold, each magnetic lower lamination having a horizontal base and first and second spaced-apart sidewalls extending substantially vertically upward from the base to define a seam therebetween; a non-conductive isolation layer formed on the lower mold and the magnetic lower laminations; a conductive trace formed on the isolation layer; a non-conductive upper mold formed over the isolation layer and the conductive trace; and a plurality of spaced-apart controlled seam magnetic upper laminations formed in the upper mold, each magnetic upper lamination having a horizontal base and first and second spaced-apart sidewalls that extend substantially vertically upward from the base to define a seam therebetween.
摘要翻译：可用于电感器结构的受控接缝磁芯层叠体包括磁性基座和从基座基本正交地延伸的第一和第二隔开的磁性侧壁，以在其间限定接缝。受控接缝磁芯层叠可用于电感器结构，其包括：非导电下模; 形成在下模具中的多个间隔开的受控接缝下层叠片，每个磁下层层叠件具有水平底座以及从底座基本垂直向上延伸的第一和第二间隔开的侧壁，以在其间限定接缝; 形成在下模具和磁性下层叠板上的非导电隔离层; 形成在隔离层上的导电迹线; 形成在隔离层和导电迹线上的非导电上模; 以及形成在上模具中的多个间隔开的受控接缝磁性上层叠片，每个磁性上层压板具有水平底座和第一和第二隔开的侧壁，其从基座基本上垂直向上延伸以在其间限定接缝。

9. 发明申请

US20120280781A1 METHOD OF MAKING A CONTROLLED SEAM LAMINATED MAGNETIC CORE FOR HIGH FREQUENCY ON-CHIP POWER INDUCTORS 有权
标题翻译：制造用于高频片上功率电感器的受控海绵层压磁芯的方法
公开(公告)号：US20120280781A1
公开(公告)日：2012-11-08
申请号：US13098656
申请日：2011-05-02
申请人： Peter Smeys , Andrei Papou , Peter Johnson , Anuraag Mohan
发明人： Peter Smeys , Andrei Papou , Peter Johnson , Anuraag Mohan
IPC分类号： H01F27/24 , H01F41/02
CPC分类号： H01F17/0033 , H01F41/046 , Y10T29/4902 , Y10T29/49075 , Y10T29/49078
摘要： A controlled seam magnetic core lamination utilizable in an inductor structure includes a magnetic base and first and second spaced-apart magnetic sidewalls extending substantially orthogonally from the base to define a seam therebetween. The controlled seam magnetic core lamination is utilizable in an inductor structure that includes: a non-conductive lower mold; a plurality of spaced-apart controlled seam lower laminations formed in the lower mold, each magnetic lower lamination having a horizontal base and first and second spaced-apart sidewalls extending substantially vertically upward from the base to define a seam therebetween; a non-conductive isolation layer formed on the lower mold and the magnetic lower laminations; a conductive trace formed on the isolation layer; a non-conductive upper mold formed over the isolation layer and the conductive trace; and a plurality of spaced-apart controlled seam magnetic upper laminations formed in the upper mold, each magnetic upper lamination having a horizontal base and first and second spaced-apart sidewalls that extend substantially vertically upward from the base to define a seam therebetween.
摘要翻译：可用于电感器结构的受控接缝磁芯层叠体包括磁性基座和从基座基本正交地延伸的第一和第二隔开的磁性侧壁，以在其间限定接缝。受控接缝磁芯层叠可用于电感器结构，其包括：非导电下模; 形成在下模具中的多个间隔开的受控接缝下层叠片，每个磁下层片具有水平底座和第一和第二间隔开的侧壁，从侧面基本垂直向上延伸以在其间限定接缝; 形成在下模具和磁性下层叠板上的非导电隔离层; 形成在隔离层上的导电迹线; 形成在隔离层和导电迹线上的非导电上模; 以及形成在上模具中的多个间隔开的受控接缝磁性上层叠片，每个磁性上层压板具有水平底座和第一和第二隔开的侧壁，其从基座基本上垂直向上延伸以在其间限定接缝。

10. 发明授权

US08531002B2 Apparatus and method for wafer level fabrication of high value inductors on semiconductor integrated circuits 有权
标题翻译：用于在半导体集成电路上制造高价值电感器的晶片级的装置和方法
公开(公告)号：US08531002B2
公开(公告)日：2013-09-10
申请号：US12899384
申请日：2010-10-06
申请人： Peter J. Hopper , Peter Johnson , Kyuwoon Hwang , Andrei Papou
发明人： Peter J. Hopper , Peter Johnson , Kyuwoon Hwang , Andrei Papou
IPC分类号： H01L27/08
CPC分类号： H01L23/5227 , C23C28/023 , C25D5/022 , C25D7/123 , C25D17/001 , H01L27/0207 , H01L28/10 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An apparatus and method for wafer level fabrication of high value inductors directly on top of semiconductor integrated circuits. The apparatus and method includes fabricating a semiconductor wafer including a plurality of dice, each of the dice including power circuitry and a switching node. Once the wafer is fabricated, then a plurality of inductors are fabricated directly onto the plurality of dice on the wafer respectively. Each inductor is fabricated by forming a plurality of magnetic core inductor members on an interconnect dielectric layer formed on the wafer. An insulating layer, and then inductor coils, are then formed over the plurality of magnetic core inductor members over each die. A plated magnetic layer is formed over the plurality of inductors respectively to raise the permeability and inductance of the structure.
摘要翻译：用于直接在半导体集成电路之上晶圆级制造高值电感器的装置和方法。该装置和方法包括制造包括多个骰子的半导体晶片，每个骰子包括电源电路和开关节点。一旦制造晶片，则分别将多个电感器直接制造在晶片上的多个晶片上。每个电感器通过在形成在晶片上的互连电介质层上形成多个磁芯电感器构件来制造。然后在每个管芯上方的多个磁芯电感器部件上形成绝缘层，然后形成电感器线圈。分别在多个电感器上形成电镀磁性层，以提高结构的磁导率和电感。

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