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1. 发明授权

US5987544A System interface protocol with optional module cache 失效
标题翻译：具有可选模块缓存的系统接口协议
公开(公告)号：US5987544A
公开(公告)日：1999-11-16
申请号：US525114
申请日：1995-09-08
申请人： Peter J. Bannon , Anil K. Jain , John H. Edmondson , Ruben William Sixtus Castelino
发明人： Peter J. Bannon , Anil K. Jain , John H. Edmondson , Ruben William Sixtus Castelino
IPC分类号： G06F12/08 , G06F12/06
CPC分类号： G06F12/0831
摘要： A computer system includes a plurality of processor modules coupled to a system bus with each of said processor modules including a processor interfaced to the system bus. The processor module has a backup cache memory and tag store. An index bus is coupled between the processor and the backup cache and backup cache tag store with said bus carrying only an index portion of a memory address to said backup cache and said tag store. A duplicate tag store is coupled to an interface with the duplicate tag memory including means for storing duplicate tag addresses and duplicate tag valid, shared and dirty bits. The duplicate tag store and the separate index bus provide higher performance from the processor by minimizing external interrupts to the processor to check on cache status and also allows other processors access to the processor's duplicate tag while the processor is processing other transactions.
摘要翻译：计算机系统包括耦合到系统总线的多个处理器模块，每个所述处理器模块包括与系统总线接口的处理器。处理器模块具有备份高速缓存和标签存储。索引总线耦合在处理器和备份高速缓存和备份高速缓存标签存储之间，所述总线仅将存储器地址的索引部分携带到所述备份高速缓存和所述标签存储。重复标签存储器与重复标签存储器耦合到接口，包括用于存储重复标签地址和重复标签有效，共享和脏位的装置。重复标签存储和单独的索引总线通过最小化处理器的外部中断来检查高速缓存状态，从处理器提供更高的性能，并且还允许其他处理器在处理器处理其他事务时访问处理器的重复标签。

2. 发明授权

US5615167A Method for increasing system bandwidth through an on-chip address lock register 失效
标题翻译：通过片上地址锁定寄存器增加系统带宽的方法
公开(公告)号：US5615167A
公开(公告)日：1997-03-25
申请号：US525106
申请日：1995-09-08
申请人： Anil K. Jain , John H. Edmondson , Peter J. Bannon
发明人： Anil K. Jain , John H. Edmondson , Peter J. Bannon
IPC分类号： G06F9/46 , G11C13/00
CPC分类号： G06F9/526 , G06F9/3004 , G06F9/30072 , G06F9/30087
摘要： A computer system comprising one or more processor modules. Each processor module comprising a central processing unit comprising a storage element disposed in the central processing unit dedicated for storing a semaphore address lock value and a semaphore lock flag value, a cache memory system for storing data and instruction values used by the central processing unit, a system bus interface for communicating with other processor modules over a system bus, a memory system implemented as a common system resource available to the processor modules for storing data and instructions, an IO system implemented as a common system resource available to the plurality of processor modules for each to communicate with data input devices and data output devices, and a system bus connecting the processor module to the memory system and to the IO system.
摘要翻译：一种包括一个或多个处理器模块的计算机系统。每个处理器模块包括中央处理单元，该中央处理单元包括设置在专用于存储信号量地址锁定值和信号量锁定标志值的中央处理单元中的存储元件，用于存储由中央处理单元使用的数据和指令值的高速缓冲存储器系统，用于通过系统总线与其他处理器模块通信的系统总线接口，被实现为用于存储数据和指令的处理器模块可用的公共系统资源的存储器系统，被实现为可用于多个处理器的公共系统资源的IO系统每个模块用于与数据输入设备和数据输出设备通信，以及将处理器模块连接到存储器系统和IO系统的系统总线。

3. 发明授权

US08352685B2 Combining write buffer with dynamically adjustable flush metrics 有权
标题翻译：将写入缓冲区与动态可调整的flush指标相结合
公开(公告)号：US08352685B2
公开(公告)日：2013-01-08
申请号：US12860505
申请日：2010-08-20
申请人： Peter J. Bannon , Andrew J. Beaumont-Smith , Ramesh Gunna , Wei-han Lien , Brian P. Lilly , Jaidev P. Patwardhan , Shih-Chieh R. Wen , Tse-Yu Yeh
发明人： Peter J. Bannon , Andrew J. Beaumont-Smith , Ramesh Gunna , Wei-han Lien , Brian P. Lilly , Jaidev P. Patwardhan , Shih-Chieh R. Wen , Tse-Yu Yeh
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0891 , G06F12/0804
摘要： In an embodiment, a combining write buffer is configured to maintain one or more flush metrics to determine when to transmit write operations from buffer entries. The combining write buffer may be configured to dynamically modify the flush metrics in response to activity in the write buffer, modifying the conditions under which write operations are transmitted from the write buffer to the next lower level of memory. For example, in one implementation, the flush metrics may include categorizing write buffer entries as “collapsed.” A collapsed write buffer entry, and the collapsed write operations therein, may include at least one write operation that has overwritten data that was written by a previous write operation in the buffer entry. In another implementation, the combining write buffer may maintain the threshold of buffer fullness as a flush metric and may adjust it over time based on the actual buffer fullness.
摘要翻译：在一个实施例中，组合写缓冲器被配置为维护一个或多个刷新度量以确定何时从缓冲器条目发送写入操作。组合写缓冲器可以被配置为响应于写缓冲器中的活动来动态地修改刷新度量，修改写操作从写缓冲器发送到下一较低级存储器的条件。例如，在一个实现中，刷新度量可以包括将写缓冲器条目分类为折叠。折叠的写缓冲器条目及其中的折叠写入操作可以包括至少一个写入操作，该写入操作已经覆盖由缓冲器条目中的先前写入操作写入的数据。在另一实现中，组合写缓冲器可以将缓冲器充满度的阈值保持为刷新度量，并且可以基于实际的缓冲器充满度随时间调整缓冲器充满度。

4. 发明授权

US08301843B2 Data cache block zero implementation 有权
标题翻译：数据缓存块零实现
公开(公告)号：US08301843B2
公开(公告)日：2012-10-30
申请号：US12650075
申请日：2009-12-30
申请人： Ramesh Gunna , Sudarshan Kadambi , Peter J. Bannon
发明人： Ramesh Gunna , Sudarshan Kadambi , Peter J. Bannon
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0808 , G06F9/30047 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F9/3861 , G06F12/0815 , G06F2212/507
摘要： In one embodiment, a processor comprises a core configured to execute a data cache block write instruction and an interface unit coupled to the core and to an interconnect on which the processor is configured to communicate. The core is configured to transmit a request to the interface unit in response to the data cache block write instruction. If the request is speculative, the interface unit is configured to issue a first transaction on the interconnect. On the other hand, if the request is non-speculative, the interface unit is configured to issue a second transaction on the interconnect. The second transaction is different from the first transaction. For example, the second transaction may be an invalidate transaction and the first transaction may be a probe transaction. In some embodiments, the processor may be in a system including the interconnect and one or more caching agents.
摘要翻译：在一个实施例中，处理器包括被配置为执行数据高速缓存块写入指令的核心和耦合到所述核心和所述处理器被配置为在其上进行通信的互连的接口单元。核心被配置为响应于数据高速缓存块写入指令向接口单元发送请求。如果请求是推测性的，则接口单元被配置为在互连上发布第一事务。另一方面，如果请求是非推测性的，则接口单元被配置为在互连上发布第二事务。第二个交易与第一笔交易不同。例如，第二事务可以是无效事务，并且第一事务可以是探查事务。在一些实施例中，处理器可以在包括互连和一个或多个高速缓存代理的系统中。

5. 发明申请

US20120047332A1 Combining Write Buffer with Dynamically Adjustable Flush Metrics 有权
标题翻译：将写入缓冲区与动态调整冲洗指标相结合
公开(公告)号：US20120047332A1
公开(公告)日：2012-02-23
申请号：US12860505
申请日：2010-08-20
申请人： Peter J. Bannon , Andrew J. Beaumont-Smith , Ramesh Gunna , Wei-han Lien , Brian P. Lilly , Jaidev P. Patwardhan , Shih-Chieh R. Wen , Tse-Yu Yeh
发明人： Peter J. Bannon , Andrew J. Beaumont-Smith , Ramesh Gunna , Wei-han Lien , Brian P. Lilly , Jaidev P. Patwardhan , Shih-Chieh R. Wen , Tse-Yu Yeh
IPC分类号： G06F12/08 , G06F3/00 , G06F12/00
CPC分类号： G06F12/0891 , G06F12/0804
摘要： In an embodiment, a combining write buffer is configured to maintain one or more flush metrics to determine when to transmit write operations from buffer entries. The combining write buffer may be configured to dynamically modify the flush metrics in response to activity in the write buffer, modifying the conditions under which write operations are transmitted from the write buffer to the next lower level of memory. For example, in one implementation, the flush metrics may include categorizing write buffer entries as “collapsed.” A collapsed write buffer entry, and the collapsed write operations therein, may include at least one write operation that has overwritten data that was written by a previous write operation in the buffer entry. In another implementation, the combining write buffer may maintain the threshold of buffer fullness as a flush metric and may adjust it over time based on the actual buffer fullness.
摘要翻译：在一个实施例中，组合写缓冲器被配置为维护一个或多个刷新度量以确定何时从缓冲器条目发送写入操作。组合写缓冲器可以被配置为响应于写缓冲器中的活动来动态地修改刷新度量，修改写操作从写缓冲器发送到下一较低级存储器的条件。例如，在一个实现中，刷新度量可以包括将写缓冲器条目分类为“折叠”。折叠的写入缓冲器条目及其中的折叠的写入操作可以包括至少一个写入操作，该写入操作已覆盖由以前的写入操作在缓冲区条目中。在另一实现中，组合写缓冲器可以将缓冲器充满度的阈值保持为刷新度量，并且可以基于实际的缓冲器充满度随时间调整缓冲器充满度。

6. 发明授权

US07707361B2 Data cache block zero implementation 有权
标题翻译：数据缓存块零实现
公开(公告)号：US07707361B2
公开(公告)日：2010-04-27
申请号：US11281840
申请日：2005-11-17
申请人： Ramesh Gunna , Sudarshan Kadambi , Peter J. Bannon
发明人： Ramesh Gunna , Sudarshan Kadambi , Peter J. Bannon
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0808 , G06F9/30047 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F9/3861 , G06F12/0815 , G06F2212/507
摘要： In one embodiment, a processor comprises a core configured to execute a data cache block write instruction and an interface unit coupled to the core and to an interconnect on which the processor is configured to communicate. The core is configured to transmit a request to the interface unit in response to the data cache block write instruction. If the request is speculative, the interface unit is configured to issue a first transaction on the interconnect. On the other hand, if the request is non-speculative, the interface unit is configured to issue a second transaction on the interconnect. The second transaction is different from the first transaction. For example, the second transaction may be an invalidate transaction and the first transaction may be a probe transaction. In some embodiments, the processor may be in a system including the interconnect and one or more caching agents.
摘要翻译：在一个实施例中，处理器包括被配置为执行数据高速缓存块写入指令的核心和耦合到所述核心和所述处理器被配置为在其上进行通信的互连的接口单元。核心被配置为响应于数据高速缓存块写入指令向接口单元发送请求。如果请求是推测性的，则接口单元被配置为在互连上发布第一事务。另一方面，如果请求是非推测性的，则接口单元被配置为在互连上发布第二事务。第二个交易与第一笔交易不同。例如，第二事务可以是无效事务，并且第一事务可以是探查事务。在一些实施例中，处理器可以在包括互连和一个或多个高速缓存代理的系统中。

7. 发明授权

US6047357A High speed method for maintaining cache coherency in a multi-level, set associative cache hierarchy 失效
标题翻译：用于在多级，组合关联高速缓存层级中维护高速缓存一致性的高速方法
公开(公告)号：US6047357A
公开(公告)日：2000-04-04
申请号：US379048
申请日：1995-01-27
申请人： Peter J. Bannon , Elizabeth M. Cooper
发明人： Peter J. Bannon , Elizabeth M. Cooper
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0811 , G06F12/0831 , G06F2212/601
摘要： A cache memory system includes multiple cache levels arranged in a hierarchical fashion. A data item stored in a higher level cache level is also stored in all lower level caches. The most recent version of a data item is detected during an initial lookup of a higher level cache. The initial lookup of a higher level cache includes a comparison of address bits for the next lower level cache. Thus the most recent version of a data item is able to be detected without additional lookups to the lower level cache.
摘要翻译：高速缓冲存储器系统包括以分层方式布置的多个高速缓存级别。存储在较高级别高速缓存级别的数据项目也存储在所有较低级别的高速缓存中。在较高级别的缓存的初始查找期间检测到最新版本的数据项。较高级别高速缓存的初始查找包括下一级较低级缓存的地址位的比较。因此，能够检测数据项的最新版本，而无需对下一级缓存进行附加查找。

8. 发明授权

US09280352B2 Lookahead scanning and cracking of microcode instructions in a dispatch queue 有权
标题翻译：在调度队列中扫描和破解微码指令
公开(公告)号：US09280352B2
公开(公告)日：2016-03-08
申请号：US13307969
申请日：2011-11-30
申请人： Ramesh B. Gunna , Peter J. Bannon , Rajat Goel
发明人： Ramesh B. Gunna , Peter J. Bannon , Rajat Goel
IPC分类号： G06F9/22 , G06F9/28 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3836 , G06F9/22 , G06F9/28 , G06F9/30145 , G06F9/3017 , G06F9/3814
摘要： An apparatus and method for avoiding bubbles and maintaining a maximum instruction throughput rate when cracking microcode instructions. A lookahead pointer scans the newest entries of a dispatch queue for microcode instructions. A detected microcode instruction is conveyed to a microcode engine to be cracked into a sequence of micro-ops. Then, the sequence of micro-ops is placed in a queue, and when the original microcode instruction entry in the dispatch queue is selected for dispatch, the sequence of micro-ops is dispatched to the next stage of the processor pipeline.
摘要翻译：一种用于在破解微代码指令时避免气泡并保持最大指令吞吐率的装置和方法。先行指针扫描调度队列的最新条目以获取微代码指令。检测到的微代码指令被传送到微代码引擎以被破解成微操作序列。然后，将微操作序列放置在队列中，并且当调度队列中的原始微代码指令条目被选择用于分派时，微操作序列被分派到处理器管线的下一个阶段。

9. 发明申请

US20120290818A1 Split Scheduler 有权
标题翻译：拆分计划程序
公开(公告)号：US20120290818A1
公开(公告)日：2012-11-15
申请号：US13557725
申请日：2012-07-25
申请人： Andrew J. Beaumont-Smith , Honkai Tam , Daniel C. Murray , John H. Mylius , Peter J. Bannon , Pradeep Kanapathipillai
发明人： Andrew J. Beaumont-Smith , Honkai Tam , Daniel C. Murray , John H. Mylius , Peter J. Bannon , Pradeep Kanapathipillai
IPC分类号： G06F9/30
CPC分类号： G06F9/3838 , G06F9/384 , G06F9/3857
摘要： In an embodiment, a scheduler implements a first dependency array that tracks dependencies on instruction operations (ops) within a distance N of a given op and which are short execution latency ops. Other dependencies are tracked in a second dependency array. The first dependency array may evaluate quickly, to support back-to-back issuance of short execution latency ops and their dependent ops. The second array may evaluate more slowly than the first dependency array.
摘要翻译：在一个实施例中，调度器实现第一依赖性数组，其跟踪给定操作的距离N内的指令操作（操作）的依赖性，并且其是短执行延迟操作。其他依赖关系在第二个依赖关系数组中被跟踪。第一个依赖数组可以快速评估，以支持短执行延迟操作及其依赖操作的背对背发布。第二个数组可能比第一个依赖数组慢得多。

10. 发明授权

US08285937B2 Fused store exclusive/memory barrier operation 有权
标题翻译：融合商店独家/内存屏障操作
公开(公告)号：US08285937B2
公开(公告)日：2012-10-09
申请号：US12711941
申请日：2010-02-24
申请人： Peter J. Bannon , Po-Yung Chang
发明人： Peter J. Bannon , Po-Yung Chang
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F9/3004 , G06F9/30087 , G06F9/3017 , G06F9/3834 , G06F9/3842 , G06F9/3857 , G06F9/3859 , G06F9/522 , G06F9/526 , G06F2209/521
摘要： In an embodiment, a processor may be configured to detect a store exclusive operation followed by a memory barrier operation in a speculative instruction stream being executed by the processor. The processor may fuse the store exclusive operation and the memory barrier operation, creating a fused operation. The fused operation may be transmitted and globally ordered, and the processor may complete both the store exclusive operation and the memory barrier operation in response to the fused operation. As the fused operation progresses through the processor and one or more other components (e.g. caches in the cache hierarchy) to the ordering point in the system, the fused operation may push previous memory operations to effect the memory barrier operation. In some embodiments, the latency for completing the store exclusive operation and the subsequent data memory barrier operation may be reduced if the store exclusive operation is successful at the ordering point.
摘要翻译：在一个实施例中，处理器可以被配置为在由处理器执行的推测性指令流中检测存储排他操作，随后进行存储器障碍操作。处理器可以融合存储专有操作和存储器屏障操作，创建融合操作。可以传输和全局排序融合操作，并且响应于融合操作，处理器可以完成存储排他操作和存储器屏障操作两者。当融合操作通过处理器和一个或多个其它组件（例如高速缓存层级中的高速缓存）进行到系统中的订购点时，融合操作可以推动先前的存储器操作来实现存储器屏障操作。在一些实施例中，如果存储排他操作在订购点成功，则可以减少完成存储排他操作和后续数据存储器屏障操作的等待时间。

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