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1. 发明申请

US20120290818A1 Split Scheduler 有权
标题翻译：拆分计划程序
公开(公告)号：US20120290818A1
公开(公告)日：2012-11-15
申请号：US13557725
申请日：2012-07-25
申请人： Andrew J. Beaumont-Smith , Honkai Tam , Daniel C. Murray , John H. Mylius , Peter J. Bannon , Pradeep Kanapathipillai
发明人： Andrew J. Beaumont-Smith , Honkai Tam , Daniel C. Murray , John H. Mylius , Peter J. Bannon , Pradeep Kanapathipillai
IPC分类号： G06F9/30
CPC分类号： G06F9/3838 , G06F9/384 , G06F9/3857
摘要： In an embodiment, a scheduler implements a first dependency array that tracks dependencies on instruction operations (ops) within a distance N of a given op and which are short execution latency ops. Other dependencies are tracked in a second dependency array. The first dependency array may evaluate quickly, to support back-to-back issuance of short execution latency ops and their dependent ops. The second array may evaluate more slowly than the first dependency array.
摘要翻译：在一个实施例中，调度器实现第一依赖性数组，其跟踪给定操作的距离N内的指令操作（操作）的依赖性，并且其是短执行延迟操作。其他依赖关系在第二个依赖关系数组中被跟踪。第一个依赖数组可以快速评估，以支持短执行延迟操作及其依赖操作的背对背发布。第二个数组可能比第一个依赖数组慢得多。

2. 发明授权

US08364936B2 Processor employing split scheduler in which near, low latency operation dependencies are tracked separate from other operation dependencies 有权
标题翻译：采用分割调度器的处理器，跟踪跟随其他操作相关性的低延迟操作相关性
公开(公告)号：US08364936B2
公开(公告)日：2013-01-29
申请号：US13557725
申请日：2012-07-25
申请人： Andrew J. Beaumont-Smith , Honkai Tam , Daniel C. Murray , John H. Mylius , Peter J. Bannon , Pradeep Kanapathipillai
发明人： Andrew J. Beaumont-Smith , Honkai Tam , Daniel C. Murray , John H. Mylius , Peter J. Bannon , Pradeep Kanapathipillai
IPC分类号： G06F9/30
CPC分类号： G06F9/3838 , G06F9/384 , G06F9/3857
摘要： In an embodiment, a scheduler implements a first dependency array that tracks dependencies on instruction operations (ops) within a distance N of a given op and which are short execution latency ops. Other dependencies are tracked in a second dependency array. The first dependency array may evaluate quickly, to support back-to-back issuance of short execution latency ops and their dependent ops. The second array may evaluate more slowly than the first dependency array.
摘要翻译：在一个实施例中，调度器实现第一依赖性数组，其跟踪给定操作的距离N内的指令操作（操作）的依赖性，并且其是短执行延迟操作。其他依赖关系在第二个依赖关系数组中被跟踪。第一个依赖数组可以快速评估，以支持短执行延迟操作及其依赖操作的背对背发布。第二个数组可能比第一个依赖数组慢得多。

3. 发明授权

US08255671B2 Processor employing split scheduler in which near, low latency operation dependencies are tracked separate from other operation dependencies 有权
标题翻译：采用分割调度器的处理器，跟踪跟随其他操作相关性的低延迟操作相关性
公开(公告)号：US08255671B2
公开(公告)日：2012-08-28
申请号：US12338769
申请日：2008-12-18
申请人： Andrew J. Beaumont-Smith , Honkai Tam , Daniel C. Murray , John H. Mylius , Peter J. Bannon , Pradeep Kanapathipillai
发明人： Andrew J. Beaumont-Smith , Honkai Tam , Daniel C. Murray , John H. Mylius , Peter J. Bannon , Pradeep Kanapathipillai
IPC分类号： G06F9/30
CPC分类号： G06F9/3838 , G06F9/384 , G06F9/3857
摘要： In an embodiment, a scheduler implements a first dependency array that tracks dependencies on instruction operations (ops) within a distance N of a given op and which are short execution latency ops. Other dependencies are tracked in a second dependency array. The first dependency array may evaluate quickly, to support back-to-back issuance of short execution latency ops and their dependent ops. The second array may evaluate more slowly than the first dependency array.
摘要翻译：在一个实施例中，调度器实现第一依赖性数组，其跟踪给定操作的距离N内的指令操作（操作）的依赖性，并且其是短执行延迟操作。其他依赖关系在第二个依赖关系数组中被跟踪。第一个依赖数组可以快速评估，以支持短执行延迟操作及其依赖操作的背对背发布。第二个数组可能比第一个依赖数组慢得多。

4. 发明申请

US20100162262A1 Split Scheduler 有权
标题翻译：拆分计划程序
公开(公告)号：US20100162262A1
公开(公告)日：2010-06-24
申请号：US12338769
申请日：2008-12-18
申请人： Andrew J. Beaumont-Smith , Honkai Tam , Daniel C. Murray , John H. Mylius , Peter J. Bannon , Pradeep Kanapathipillai
发明人： Andrew J. Beaumont-Smith , Honkai Tam , Daniel C. Murray , John H. Mylius , Peter J. Bannon , Pradeep Kanapathipillai
IPC分类号： G06F9/46
CPC分类号： G06F9/3838 , G06F9/384 , G06F9/3857
摘要： In an embodiment, a scheduler implements a first dependency array that tracks dependencies on instruction operations (ops) within a distance N of a given op and which are short execution latency ops. Other dependencies are tracked in a second dependency array. The first dependency array may evaluate quickly, to support back-to-back issuance of short execution latency ops and their dependent ops. The second array may evaluate more slowly than the first dependency array.
摘要翻译：在一个实施例中，调度器实现第一依赖性数组，其跟踪给定操作的距离N内的指令操作（操作）的依赖性，并且其是短执行延迟操作。其他依赖关系在第二个依赖关系数组中被跟踪。第一个依赖数组可以快速评估，以支持短执行延迟操作及其依赖操作的背对背发布。第二个数组可能比第一个依赖数组慢得多。

5. 发明授权

US09009451B2 Instruction type issue throttling upon reaching threshold by adjusting counter increment amount for issued cycle and decrement amount for not issued cycle 有权
标题翻译：指令类型问题通过调整发行周期的计数器增量量和未发布周期的减量量来达到阈值
公开(公告)号：US09009451B2
公开(公告)日：2015-04-14
申请号：US13285361
申请日：2011-10-31
申请人： Daniel C. Murray , Andrew J. Beaumont-Smith , John H. Mylius , Peter J. Bannon , Toshi Takayanagi , Jung Wook Cho
发明人： Daniel C. Murray , Andrew J. Beaumont-Smith , John H. Mylius , Peter J. Bannon , Toshi Takayanagi , Jung Wook Cho
IPC分类号： G06F9/30 , G06F1/32 , G06F9/38 , G06F11/30
CPC分类号： G06F9/3836 , G06F1/3206 , G06F1/329 , G06F9/3838 , G06F9/384 , G06F9/3869 , G06F11/30 , G06F11/3024 , G06F11/3062 , G06F2201/81 , G06F2201/88 , H01L2924/0002 , Y02D10/24 , H01L2924/00
摘要： A system and method for reducing power consumption through issue throttling of selected problematic instructions. A power throttle unit within a processor maintains instruction issue counts for associated instruction types. The instruction types may be a subset of supported instruction types executed by an execution core within the processor. The instruction types may be chosen based on high power consumption estimates for processing instructions of these types. The power throttle unit may determine a given instruction issue count exceeds a given threshold. In response, the power throttle unit may select given instruction types to limit a respective issue rate. The power throttle unit may choose an issue rate for each one of the selected given instruction types and limit an associated issue rate to a chosen issue rate. The selection of given instruction types and associated issue rate limits is programmable.
摘要翻译：一种通过发布限制所选问题指令来降低功耗的系统和方法。处理器内的功率节流单元维持相关指令类型的指令发出计数。指令类型可以是由处理器内的执行核执行的支持的指令类型的子集。可以基于用于处理这些类型的指令的高功耗估计来选择指令类型。功率节流单元可以确定给定的指令发出次数超过给定的阈值。作为响应，功率节流单元可以选择给定的指令类型以限制相应的发行率。功率节流单元可以选择所选择的给定指令类型中的每一个的发布率，并将相关的发行率限制为所选择的发行率。给定的指令类型和相关的发行率限制的选择是可编程的。

6. 发明申请

US20130111191A1 PROCESSOR INSTRUCTION ISSUE THROTTLING 有权
标题翻译：加工者指导问题
公开(公告)号：US20130111191A1
公开(公告)日：2013-05-02
申请号：US13285361
申请日：2011-10-31
申请人： Daniel C. Murray , Andrew J. Beaumont-Smith , John H. Mylius , Peter J. Bannon , Toshi Takayanagi , Jung Wook Cho
发明人： Daniel C. Murray , Andrew J. Beaumont-Smith , John H. Mylius , Peter J. Bannon , Toshi Takayanagi , Jung Wook Cho
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F1/3206 , G06F1/329 , G06F9/3838 , G06F9/384 , G06F9/3869 , G06F11/30 , G06F11/3024 , G06F11/3062 , G06F2201/81 , G06F2201/88 , H01L2924/0002 , Y02D10/24 , H01L2924/00
摘要： A system and method for reducing power consumption through issue throttling of selected problematic instructions. A power throttle unit within a processor maintains instruction issue counts for associated instruction types. The instruction types may be a subset of supported instruction types executed by an execution core within the processor. The instruction types may be chosen based on high power consumption estimates for processing instructions of these types. The power throttle unit may determine a given instruction issue count exceeds a given threshold. In response, the power throttle unit may select given instruction types to limit a respective issue rate. The power throttle unit may choose an issue rate for each one of the selected given instruction types and limit an associated issue rate to a chosen issue rate. The selection of given instruction types and associated issue rate limits is programmable.
摘要翻译：一种通过发布限制所选问题指令来降低功耗的系统和方法。处理器内的功率节流单元维持相关指令类型的指令发出计数。指令类型可以是由处理器内的执行核执行的支持的指令类型的子集。可以基于用于处理这些类型的指令的高功耗估计来选择指令类型。功率节流单元可以确定给定的指令发出次数超过给定的阈值。作为响应，功率节流单元可以选择给定的指令类型以限制相应的发布率。功率节流单元可以选择所选择的给定指令类型中的每一个的发布率，并将相关的发行率限制为所选择的发行率。给定指令类型的选择和相关的发行率限制是可编程的。

7. 发明授权

US08356221B2 Transition delay test function logic 有权
标题翻译：转换延迟测试功能逻辑
公开(公告)号：US08356221B2
公开(公告)日：2013-01-15
申请号：US12861991
申请日：2010-08-24
申请人： Mark T. Kuo , Michael Howard , Daniel C. Murray
发明人： Mark T. Kuo , Michael Howard , Daniel C. Murray
IPC分类号： G01R31/28
CPC分类号： G01R31/31858 , G01R31/318544 , G11C29/32
摘要： A method and apparatus for conducting transition testing using scan elements are disclosed. In one embodiment, an integrated circuit (IC) includes a scan chain having first and second subsets of scannable flops, the first subset having respective data inputs coupled to a memory array. The scannable flops of the second subset may each have a respective data input coupled to circuitry other than the memory array (e.g., to a logic circuit). The scannable flops of the first subset may be enabled for scan shifting during a transition test mode. The scannable flops of the second subset are inhibited from scanning during the transition test mode. The transition test mode may include at least two functional clock cycles in which the scannable flops of the first subset provide complementary first and second logic values to logic circuits coupled to respective data outputs.
摘要翻译：公开了一种使用扫描元件进行转换测试的方法和装置。在一个实施例中，集成电路（IC）包括具有可扫描触发器的第一和第二子集的扫描链，第一子集具有耦合到存储器阵列的相应数据输入。第二子集的可扫描触发器可以各自具有耦合到除了存储器阵列之外的电路（例如，到逻辑电路）的相应数据输入。在转换测试模式期间，可以启用第一子集的可扫描的触发器用于扫描移位。在转换测试模式期间禁止第二子集的可扫描触发器扫描。转换测试模式可以包括至少两个功能时钟周期，其中第一子集的可扫描触发器为耦合到相应数据输出的逻辑电路提供互补的第一和第二逻辑值。

8. 发明授权

US07760559B2 Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage 有权
标题翻译：具有不同于逻辑电路电源电压的存储器的单独电源电压的集成电路
公开(公告)号：US07760559B2
公开(公告)日：2010-07-20
申请号：US12325476
申请日：2008-12-01
申请人： Brian J. Campbell , Vincent R. von Kaenel , Daniel C. Murray , Gregory S. Scott , Sribalan Santhanam
发明人： Brian J. Campbell , Vincent R. von Kaenel , Daniel C. Murray , Gregory S. Scott , Sribalan Santhanam
IPC分类号： G11C7/00
CPC分类号： G11C11/419 , G11C5/143 , G11C7/00 , G11C7/12 , G11C8/08 , G11C11/417 , H03K3/35613 , H03K19/018528
摘要： In one embodiment, an integrated circuit comprises at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method comprises a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.
摘要翻译：在一个实施例中，集成电路包括由第一电源电压提供的至少一个逻辑电路和耦合到逻辑电路并由第二电源电压提供的至少一个存储器电路。即使在使用期间第一电源电压小于第二电源电压，存储器电路被配置为响应于逻辑电路被读取和写入。在另一个实施例中，一种方法包括读取存储单元的逻辑电路，由第一电源电压提供的逻辑电路; 并且所述存储单元响应于所读取的使用参考于所述第一电源电压的信号，其中所述存储单元被提供在使用期间大于所述第一电源电压的第二电源电压。

9. 发明申请

US20100169619A1 Efficient Encoding for Detecting Load Dependency on Store with Misalignment 有权
标题翻译：高效编码，用于检测负载依赖关系，存储不对齐
公开(公告)号：US20100169619A1
公开(公告)日：2010-07-01
申请号：US12721164
申请日：2010-03-10
申请人： Tse-yu Yeh , Daniel C. Murray , Po Yung Chang , Anup S. Mehta
发明人： Tse-yu Yeh , Daniel C. Murray , Po Yung Chang , Anup S. Mehta
IPC分类号： G06F9/305 , G06F12/08 , G06F12/00 , G06F9/00
CPC分类号： G06F12/0607
摘要： In one embodiment, an apparatus comprises a queue comprising a plurality of entries and a control unit coupled to the queue. The control unit is configured to allocate a first queue entry to a store memory operation, and is configured to write a first even offset, a first even mask, a first odd offset, and a first odd mask corresponding to the store memory operation to the first entry. A group of contiguous memory locations are logically divided into alternately-addressed even and odd byte ranges. A given store memory operation writes at most one even byte range and one adjacent odd byte range. The first even offset identifies a first even byte range that is potentially written by the store memory operation, and the first odd offset identifies a first odd byte range that is potentially written by the store memory operation. The first even mask identifies bytes within the first even byte range that are written by the store memory operation, and wherein the first odd mask identifies bytes within the first odd byte range that are written by the store memory operation.
摘要翻译：在一个实施例中，装置包括包括多个条目的队列和耦合到队列的控制单元。控制单元被配置为将第一队列条目分配给存储存储器操作，并且被配置为将对应于存储存储器操作的第一偶数偏移，第一偶数掩码，第一奇数偏移和第一奇数掩码写入到第一次入场一组连续的存储器位置在逻辑上被划分为交替寻址的偶数和奇数字节范围。给定的存储器操作写入至多一个偶数字节范围和一个相邻的奇数字节范围。第一偶数偏移识别由存储器存储器操作潜在地写入的第一偶数字节范围，并且第一奇数偏移识别潜在地由存储器存储器操作写入的第一奇数字节范围。第一偶数掩模识别由存储器存储器操作写入的第一偶数字节范围内的字节，并且其中第一奇数掩码标识由存储器存储器操作写入的第一奇数字节范围内的字节。

10. 发明授权

US07721066B2 Efficient encoding for detecting load dependency on store with misalignment 有权
标题翻译：高效编码，用于检测不对齐存储的负载依赖性
公开(公告)号：US07721066B2
公开(公告)日：2010-05-18
申请号：US11758193
申请日：2007-06-05
申请人： Tse-yu Yeh , Daniel C. Murray , Po-Yung Chang , Anup S. Mehta
发明人： Tse-yu Yeh , Daniel C. Murray , Po-Yung Chang , Anup S. Mehta
IPC分类号： G06F12/00
CPC分类号： G06F12/0607
摘要： In one embodiment, an apparatus comprises a queue comprising a plurality of entries and a control unit coupled to the queue. The control unit is configured to allocate a first queue entry to a store memory operation, and is configured to write a first even offset, a first even mask, a first odd offset, and a first odd mask corresponding to the store memory operation to the first entry. A group of contiguous memory locations are logically divided into alternately-addressed even and odd byte ranges. A given store memory operation writes at most one even byte range and one adjacent odd byte range. The first even offset identifies a first even byte range that is potentially written by the store memory operation, and the first odd offset identifies a first odd byte range that is potentially written by the store memory operation. The first even mask identifies bytes within the first even byte range that are written by the store memory operation, and wherein the first odd mask identifies bytes within the first odd byte range that are written by the store memory operation.
摘要翻译：在一个实施例中，装置包括包括多个条目的队列和耦合到队列的控制单元。控制单元被配置为将第一队列条目分配给存储存储器操作，并且被配置为将对应于存储存储器操作的第一偶数偏移，第一偶数掩码，第一奇数偏移和第一奇数掩码写入到第一次入场一组连续的存储器位置在逻辑上被划分为交替寻址的偶数和奇数字节范围。给定的存储器操作写入至多一个偶数字节范围和一个相邻的奇数字节范围。第一偶数偏移识别由存储器存储器操作潜在地写入的第一偶数字节范围，并且第一奇数偏移识别潜在地由存储器存储器操作写入的第一奇数字节范围。第一偶数掩模识别由存储器存储器操作写入的第一偶数字节范围内的字节，并且其中第一奇数掩码标识由存储器存储器操作写入的第一奇数字节范围内的字节。

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