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1. 发明授权

US08605526B2 Memory reliability verification techniques 有权
标题翻译：内存可靠性验证技术
公开(公告)号：US08605526B2
公开(公告)日：2013-12-10
申请号：US13118687
申请日：2011-05-31
申请人： Peter Huber , Joel Hatsch , Karl Hofmann , Siegmar Koeppe
发明人： Peter Huber , Joel Hatsch , Karl Hofmann , Siegmar Koeppe
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C29/12 , G11C29/50 , G11C2029/1204
摘要： Rather than merely carrying out a BIST test by verifying whether a memory cell accurately stores a “1” or “0” under normal read/write conditions, aspects of the present discloser relate to BIST tests that test the read and/or write margins of a cell. During this BIST testing, the read and/or write margins can be incrementally stressed until a failure point is determined for the cell. In this way, “weak” memory cells in an array can be identified and appropriate action can be taken, if necessary, to deal with these weak cells.
摘要翻译：而不是仅仅通过验证存储器单元在正常读/写条件下是否准确地存储“1”或“0”来进行BIST测试，而本发明的方面涉及测试读取和/或写入边缘的BIST测试一个单元格在此BIST测试期间，读取和/或写入边距可以递增应力，直到为单元格确定故障点。以这种方式，可以识别阵列中的“弱”存储单元，并且如果需要可以采取适当的动作来处理这些弱电池。

2. 发明申请

US20120307579A1 MEMORY RELIABILITY VERIFICATION TECHNIQUES 有权
标题翻译：记忆可靠性验证技术
公开(公告)号：US20120307579A1
公开(公告)日：2012-12-06
申请号：US13118687
申请日：2011-05-31
申请人： Peter Huber , Joel Hatsch , Karl Hofmann , Siegmar Koeppe
发明人： Peter Huber , Joel Hatsch , Karl Hofmann , Siegmar Koeppe
IPC分类号： G11C29/12
CPC分类号： G11C29/12 , G11C29/50 , G11C2029/1204
摘要： Some embodiments of the present disclosure relate to improved reliability verification techniques for semiconductor memories. Rather than merely carrying out a BIST test by verifying whether a memory cell accurately stores a “1” or “0” under normal read/write conditions, aspects of the present invention relate to BIST tests that test the read and/or write margins of a cell. During this BIST testing, the read and/or write margins can be incrementally stressed until a failure point is determined for the cell. In this way, “weak” memory cells in an array can be identified and appropriate action can be taken, if necessary, to deal with these weak cells.
摘要翻译：本公开的一些实施例涉及用于半导体存储器的改进的可靠性验证技术。不是通过验证存储器单元在正常读/写条件下是否准确地存储1或0来执行BIST测试，而是本发明的方面涉及测试单元的读取和/或写入边缘的BIST测试。在此BIST测试期间，读取和/或写入边距可以递增应力，直到为单元格确定故障点。以这种方式，可以识别阵列中的弱记忆单元，并且如果需要，可以采取适当的动作来处理这些弱细胞。

3. 发明授权

US08854866B2 Identification circuit and method for generating an identification bit 有权
标题翻译：用于产生识别位的识别电路和方法
公开(公告)号：US08854866B2
公开(公告)日：2014-10-07
申请号：US13163131
申请日：2011-06-17
申请人： Peter Huber , Winfried Kamp , Joel Hatsch , Michel d'Argouges , Siegmar Koeppe , Thomas Kuenemund
发明人： Peter Huber , Winfried Kamp , Joel Hatsch , Michel d'Argouges , Siegmar Koeppe , Thomas Kuenemund
IPC分类号： G11C11/00 , G06F21/72 , H04L9/08
CPC分类号： H04L9/0866 , G06F21/72
摘要： A semiconductor device includes an identification circuit. The identification circuit includes a memory cell which includes a first transistor having a first value of a switching characteristic and a second transistor having a second value of the switching characteristic. The identification circuit is operable to generate a memory-cell-specific identification bit which is dependent on production-dictated differences in the first switching characteristic of the first transistor and the second switching characteristic of the second transistor. The identification circuit further includes a drive circuit for the memory cell. The drive circuit is operable to connect or isolate an upper supply potential and a lower supply potential of the semiconductor device to or from the memory cell independently of one another.
摘要翻译：半导体器件包括识别电路。识别电路包括存储单元，其包括具有第一开关特性值的第一晶体管和具有第二开关特性值的第二晶体管。识别电路可操作以产生依赖于第一晶体管的第一开关特性和第二晶体管的第二开关特性中生产规定的差异的存储单元特定的识别位。识别电路还包括用于存储单元的驱动电路。驱动电路可操作以独立于彼此连接或隔离半导体器件的上电源电位和较低电源电压到存储器单元或从存储器单元隔离。

4. 发明申请

US20120020145A1 Identification Circuit and Method for Generating an Identification Bit 有权
标题翻译：识别电路和产生识别位的方法
公开(公告)号：US20120020145A1
公开(公告)日：2012-01-26
申请号：US13163131
申请日：2011-06-17
申请人： Peter Huber , Winfried Kamp , Joel Hatsch , Michel d'Argouges , Siegmar Koeppe
发明人： Peter Huber , Winfried Kamp , Joel Hatsch , Michel d'Argouges , Siegmar Koeppe
IPC分类号： G11C11/40 , G11C8/08
CPC分类号： H04L9/0866 , G06F21/72
摘要： A semiconductor device includes an identification circuit. The identification circuit includes a memory cell which includes a first transistor having a first value of a switching characteristic and a second transistor having a second value of the switching characteristic. The identification circuit is operable to generate a memory-cell-specific identification bit which is dependent on production-dictated differences in the first switching characteristic of the first transistor and the second switching characteristic of the second transistor. The identification circuit further includes a drive circuit for the memory cell. The drive circuit is operable to connect or isolate an upper supply potential and a lower supply potential of the semiconductor device to or from the memory cell independently of one another.
摘要翻译：半导体器件包括识别电路。识别电路包括存储单元，其包括具有第一开关特性值的第一晶体管和具有第二开关特性值的第二晶体管。识别电路可操作以产生依赖于第一晶体管的第一开关特性和第二晶体管的第二开关特性中生产规定的差异的存储单元特定的识别位。识别电路还包括用于存储单元的驱动电路。驱动电路可操作以独立于彼此连接或隔离半导体器件的上电源电位和较低电源电压到存储器单元或从存储器单元隔离。

5. 发明申请

US20060294178A1 Carry-ripple adder 审中-公开
标题翻译：进位纹波加法器
公开(公告)号：US20060294178A1
公开(公告)日：2006-12-28
申请号：US11203445
申请日：2005-08-12
申请人： Marc Bernhardt , Joel Hatsch , Winfried Kamp , Siegmar Koeppe
发明人： Marc Bernhardt , Joel Hatsch , Winfried Kamp , Siegmar Koeppe
IPC分类号： G06F7/50
CPC分类号： G06F7/607 , G06F7/509 , G06F7/5318 , G06F2207/3872
摘要： A carry-ripple adder having inputs for supplying three input bits of equal significance 2n that are to be summed and two carry bits of equal significance 2n+1 that are also to be summed. A calculated sum bit of significance 2n and two calculated carry bits of equal significance 2n+1 which are higher than the significance 2n of the sum bit are provided at outputs. A final carry-ripple stage VMA may be used even after a reduction to three bits.
摘要翻译：具有输入的输入纹波加法器，其具有用于提供要求和的三个等号有效值的输入比特和两个相等重要性的两个进位比特2 n + 1，也是被总结。计算出的有效值的和位2＆lt; n＆gt;和两个具有相同重要性的计算的进位位2＆lt; n + 1＆lt; / 2＆gt;其高于在输出端提供和位。即使在减少到三位之后，也可以使用最终的进位纹波级VMA。

6. 发明授权

US08243555B2 Apparatus and system with a time delay path and method for propagating a timing event 有权
标题翻译：具有时间延迟路径的装置和系统以及用于传播定时事件的方法
公开(公告)号：US08243555B2
公开(公告)日：2012-08-14
申请号：US12187404
申请日：2008-08-07
申请人： Stephan Henzler , Siegmar Koeppe
发明人： Stephan Henzler , Siegmar Koeppe
IPC分类号： G04F8/00 , G04F10/00 , H03L7/00 , H03H11/26
CPC分类号： G04F10/00 , G04F10/005 , H03K5/133 , H03K2005/00123 , H03K2005/0013 , H03K2005/00143
摘要： Implementations are presented herein that include a time delay path.
摘要翻译：这里给出了包括时间延迟路径的实现。

7. 发明授权

US5610531A Testing method for semiconductor circuit levels 失效
标题翻译：半导体电路级的测试方法
公开(公告)号：US5610531A
公开(公告)日：1997-03-11
申请号：US369391
申请日：1995-01-06
申请人： Werner Weber , Siegmar Koeppe , Helmut Klose , Holger Huebner
发明人： Werner Weber , Siegmar Koeppe , Helmut Klose , Holger Huebner
IPC分类号： G01R31/26 , G01R31/28 , H01L21/66 , H01L21/70 , H01L23/544
CPC分类号： H01L22/34 , H01L2924/0002
摘要： A function test is implemented for an individual circuit level (1) that is provided for vertical integration in a semiconductor component. Stacks of circuit levels respectively provided over or under this circuit level in the finished component are simulated as test heads (2, 3). These test heads are provided with terminal contacts for reversible contacting. The circuit level (1) under test is connected to these test heads (2, 3) during the function test, and the test heads are removed after the test.
摘要翻译：对于为半导体部件中的垂直集成提供的单独电路电平（1）实现功能测试。在完成的部件中分别设置在该电路电平以下或以下的电路电平的堆叠被模拟为测试头（2,3）。这些测试头设置有用于可逆接触的端子触点。在功能测试期间，被测线路电平（1）连接到这些测试头（2,3），并在测试之后移除测试头。

8. 发明申请

US20120057411A1 Latch Based Memory Device 有权
标题翻译：基于锁存器的存储器件
公开(公告)号：US20120057411A1
公开(公告)日：2012-03-08
申请号：US12876560
申请日：2010-09-07
申请人： Siegmar Koeppe , Winfried Kamp , Julie Aunis
发明人： Siegmar Koeppe , Winfried Kamp , Julie Aunis
IPC分类号： G11C7/10 , G11C29/00
CPC分类号： G11C29/10 , G11C7/10 , G11C11/41 , G11C19/28 , G11C29/022 , G11C29/32
摘要： A latch based memory device includes a plurality of latches and a method of testing the latch based memory device that includes serially connecting the latches with each other so as to form a shift register chain. A bit sequence is input into the shift register chain to shift the bit sequence through the shift register chain. A bit sequence is outputted and shifted through the shift register chain, and the input bit sequence is compared with the output sequence to evaluate the functionality of the latches in a first test phase and to test the remaining structures of the latch based memory device in a second test phase by using, e.g., a conventional scan test approach.
摘要翻译：一种基于锁存器的存储器件包括多个锁存器和一种测试基于锁存器的存储器件的方法，该存储器件包括将锁存器彼此串联连接以形成移位寄存器链。一个位序列被输入到移位寄存器链中，以通过移位寄存器链来移位比特序列。输出比特序列并通过移位寄存器链进行移位，并将输入比特序列与输出序列进行比较，以评估第一个测试阶段的锁存器的功能，并测试基于锁存器的存储器件的剩余结构通过使用例如常规扫描测试方法的第二测试阶段。

9. 发明授权

US07492187B2 Circuit arrangement for supplying configuration data in FPGA devices 有权
标题翻译：用于在FPGA器件中提供配置数据的电路布置
公开(公告)号：US07492187B2
公开(公告)日：2009-02-17
申请号：US11437421
申请日：2006-05-19
申请人： Winfried Kamp , Siegmar Koeppe , Michael Scheppler
发明人： Winfried Kamp , Siegmar Koeppe , Michael Scheppler
IPC分类号： H03K19/177
CPC分类号： H03K19/17748 , H03K19/1776
摘要： A circuit arrangement for supplying configuration data in an FPGA device includes a plurality of output flip flops allocated to respective configurable logic cells of the FGPGA device. Each output flip flop comprises at least one data input and one data output and a data input of a first output flip flop of the plurality of output flip flops is switchably connected to a data output of a second output flip flop of the plurality of output flip flops for forming a shift register by means of a switching device integrated in the FPGA device.
摘要翻译：用于在FPGA器件中提供配置数据的电路装置包括分配给FGPGA器件的各个可配置逻辑单元的多个输出触发器。每个输出触发器包括至少一个数据输入和一个数据输出，并且多个输出触发器的第一输出触发器的数据输入可切换地连接到多个输出触发器的第二输出触发器的数据输出用于通过集成在FPGA器件中的开关器件形成移位寄存器。

10. 发明授权

US4852093A Method for simulating a fault in a logic circuit and a simulation model for the implementation of the method 失效
标题翻译：用于模拟逻辑电路中的故障的方法和用于实现该方法的仿真模型
公开(公告)号：US4852093A
公开(公告)日：1989-07-25
申请号：US56896
申请日：1987-06-03
申请人： Siegmar Koeppe
发明人： Siegmar Koeppe
IPC分类号： H03K19/00 , G06F11/25 , G06F11/26 , G06F17/50 , G06F19/00 , H01L21/8234 , H01L27/088
CPC分类号： G06F11/261
摘要： A method for simulating an erroneously-delayed signal switching at the output of the logic circuit utilizing a modified simulation model which is inherently suited for the simulation of a stuck-open fault and which, in particular, comprises an output stage which takes the signal storage appearing given this fault into consideration is disclosed. The modification is comprised in that the storage behavior of the output stage is suppressed after one clock period.
摘要翻译：一种用于模拟在逻辑电路的输出处的错误延迟的信号切换的方法，该方法利用本来适合于卡尔开式故障的模拟的修改的模拟模型，并且其特别地包括一个输出级，其将信号存储公开了考虑到这个错误的出现。该修改包括在一个时钟周期之后抑制输出级的存储行为。

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