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1. 发明申请

US20070061771A1 METHOD FOR RETICLE SHAPES ANALYSIS AND CORRECTION 失效
标题翻译：用于形式分析和校正的方法
公开(公告)号：US20070061771A1
公开(公告)日：2007-03-15
申请号：US11162586
申请日：2005-09-15
申请人： Peter Habitz , David Hathaway , Jerry Hayes , Anthony Polson , Tad Wilder
发明人： Peter Habitz , David Hathaway , Jerry Hayes , Anthony Polson , Tad Wilder
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method for reticle design correction and electrical parameter extraction of a multi-cell reticle design. The method including: selecting a subset of cell designs of a multi-cell reticle design, each cell design of the subset of cell designs having a corresponding shape to process, for each cell design of the subset of cell designs determining a respective cell design location of the corresponding shape; determining a common shapes processing rule for all corresponding shapes of each cell design based on the respective cell design locations of each of the corresponding shapes; and performing shapes processing of the corresponding shape only of a single cell design of the subset of cell designs to generate resulting data for the subset of cell designs. Also a computer usable medium including computer readable program code having an algorithm adapted to implement the method for reticle design correction and electrical extraction.
摘要翻译：一种多光栅掩模版设计的掩模版设计校正和电参数提取的方法。该方法包括：选择多小区掩模版设计的小区设计的子集，小区设计子集的每个小区设计具有相应的处理形状，用于确定相应小区设计位置的小区设计子集的每个小区设计的相应形状; 基于每个相应形状的相应单元设计位置，确定每个单元设计的所有对应形状的共同形状处理规则; 以及仅对单元设计的子集的单个单元设计执行相应形状的形状处理，以生成用于所述单元设计的子集的结果数据。还有一种包括计算机可读程序代码的计算机可用介质，其具有适于实现掩模版设计校正和电提取的方法的算法。

2. 发明申请

US20060248488A1 METHOD OF GENERATING WIRING ROUTES WITH MATCHING DELAY IN THE PRESENCE OF PROCESS VARIATION 有权
标题翻译：在过程变化存在下产生匹配延迟的接线方法
公开(公告)号：US20060248488A1
公开(公告)日：2006-11-02
申请号：US10908102
申请日：2005-04-27
申请人： Peter Habitz , David Hathaway , Jerry Hayes , Anthony Polson
发明人： Peter Habitz , David Hathaway , Jerry Hayes , Anthony Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.
摘要翻译：电路设计中的平衡延迟的方法和服务从通过布线设计连接在一起的节点开始，或通过提供要被改变的初始布线设计。布线设计将具有许多布线路径，例如第一布线路径，第二布线路径等。两条或多条布线路径被设计成具有匹配的定时，使得信号沿着第一布线路径行进所需的时间信号沿着第二布线路径，第三路径等移动所需的大致相同的时间。该方法/服务设计一个或所有布线路径，以使路径穿过大约相同长度的线段，并且在第一布线路径和第二布线路径横越的各布线层内。此外，该处理使得第一布线路径和第二布线路径在第一布线路径和第二布线路径横越的各布线层内以相同的顺序横穿线段。

3. 发明申请

US20050246116A1 METHOD AND SYSTEM FOR EVALUATING TIMING IN AN INTEGRATED CIRCUIT 失效
标题翻译：用于评估集成电路中的时序的方法和系统
公开(公告)号：US20050246116A1
公开(公告)日：2005-11-03
申请号：US10709361
申请日：2004-04-29
申请人： Eric Foreman , Peter Habitz , David Hathaway , Jerry Hayes , Anthony Polson
发明人： Eric Foreman , Peter Habitz , David Hathaway , Jerry Hayes , Anthony Polson
IPC分类号： G01M99/00 , G01R13/00 , G01R31/30
CPC分类号： G01R31/3016
摘要： Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An adjusted timing slack is calculated using the delay contributions of elements having dissimilar delays. In some embodiments, the delay contributions of elements having dissimilar delays are root sum squared. Embodiments of the invention provide methods for reducing the pessimism due to both cell-based and wire-dependent delays. The delays considered in embodiments of the invention may include delays due to the location of elements in a path.
摘要翻译：用于分析集成电路中的定时并减少静态时序分析（STA）中定时松弛计算中的悲观情况的方法。该方法涉及分组和消除在早期和晚期电路路径中具有类似延迟的元件的延迟贡献。使用具有不同延迟的元件的延迟贡献来计算调整的定时松弛。在一些实施例中，具有不同延迟的元件的延迟贡献是根和平方。本发明的实施例提供了用于减少由于基于单元和线依赖的延迟引起的悲观的方法。在本发明的实施例中考虑的延迟可以包括由于路径中的元件的位置而导致的延迟。

4. 发明申请

US20080052656A1 SLACK SENSITIVITY TO PARAMETER VARIATION BASED TIMING ANALYSIS 失效
标题翻译：对参数变化的时序分析的灵敏度
公开(公告)号：US20080052656A1
公开(公告)日：2008-02-28
申请号：US11930924
申请日：2007-10-31
申请人： Eric Foreman , Peter Habitz , David Hathaway , Jerry Hayes , Jeffrey Oppold , Anthony Polson
发明人： Eric Foreman , Peter Habitz , David Hathaway , Jerry Hayes , Jeffrey Oppold , Anthony Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.
摘要翻译：公开了一种用于改进IC设计的方法，系统和程序产品，其优先考虑根据其故障概率导致校正的松弛故障系数。通过确定的一组独立参数，当参数变化时，通过注意时序上的差异，通常在端点松弛时，对每个参数执行灵敏度分析。对于每个独立参数重复此步骤。然后从参考松弛和每个定时端点的松弛的灵敏度计算失效系数，并且确定至少一个定时端点是否失败阈值测试。然后将失败的定时终点根据其故障系数进行优先级修改。所需的总运行次数是一次运行，用作参考运行，每个参数再运行一次运行。

5. 发明申请

US20060195807A1 METHOD AND SYSTEM FOR EVALUATING TIMING IN AN INTEGATED CIRCUIT 有权
标题翻译：用于在整流电路中评估时序的方法和系统
公开(公告)号：US20060195807A1
公开(公告)日：2006-08-31
申请号：US11383353
申请日：2006-05-15
申请人： Eric Foreman , Peter Habitz , David Hathaway , Jerry Hayes , Anthony Polson
发明人： Eric Foreman , Peter Habitz , David Hathaway , Jerry Hayes , Anthony Polson
IPC分类号： G06F17/50
CPC分类号： G01R31/3016
摘要： Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An adjusted timing slack is calculated using the delay contributions of elements having dissimilar delays. In some embodiments, the delay contributions of elements having dissimilar delays are root sum squared. Embodiments of the invention provide methods for reducing the pessimism due to both cell-based and wire-dependent delays. The delays considered in embodiments of the invention may include delays due to the location of elements in a path.
摘要翻译：用于分析集成电路中的定时并减少静态时序分析（STA）中定时松弛计算中的悲观情况的方法。该方法涉及分组和消除在早期和晚期电路路径中具有类似延迟的元件的延迟贡献。使用具有不同延迟的元件的延迟贡献来计算调整的定时松弛。在一些实施例中，具有不同延迟的元件的延迟贡献是根和平方。本发明的实施例提供了用于减少由于基于单元和线依赖的延迟引起的悲观的方法。在本发明的实施例中考虑的延迟可以包括由于路径中的元件的位置而导致的延迟。

6. 发明申请

US20060101361A1 SLACK SENSITIVITY TO PARAMETER VARIATION BASED TIMING ANALYSIS 有权
标题翻译：对参数变化的时序分析的灵敏度
公开(公告)号：US20060101361A1
公开(公告)日：2006-05-11
申请号：US10904309
申请日：2004-11-03
申请人： Eric Foreman , Peter Habitz , David Hathaway , Jerry Hayes , Jeffrey Oppold , Anthony Polson
发明人： Eric Foreman , Peter Habitz , David Hathaway , Jerry Hayes , Jeffrey Oppold , Anthony Polson
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.
摘要翻译：公开了一种用于改进IC设计的方法，系统和程序产品，其优先考虑根据其故障概率导致校正的松弛故障系数。通过确定的一组独立参数，当参数变化时，通过注意时序上的差异，通常在端点松弛时，对每个参数执行灵敏度分析。对于每个独立参数重复此步骤。然后从参考松弛和每个定时端点的松弛的灵敏度计算失效系数，并且确定至少一个定时端点是否失败阈值测试。然后将失败的定时终点根据其故障系数进行优先级修改。所需的总运行次数是一次运行，用作参考运行，每个参数再运行一次运行。

7. 发明申请

US20050246117A1 SYSTEM AND METHOD OF ANALYZING TIMING EFFECTS OF SPATIAL DISTRIBUTION IN CIRCUITS 有权
标题翻译：分析电路中空间分布的时序效应的系统与方法
公开(公告)号：US20050246117A1
公开(公告)日：2005-11-03
申请号：US10709362
申请日：2004-04-29
申请人： David Hathaway , Jerry Hayes , Anthony Polson
发明人： David Hathaway , Jerry Hayes , Anthony Polson
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5031
摘要： Systems and methods are provided for analyzing the timing of circuits, including integrated circuits, by taking into account the location of cells or elements in the paths or logic cones of the circuit. In one embodiment, a bounding region may be defined around cells or elements of interest, and the size of the bounding region may be used to calculate a timing slack variation factor. The size of the bounding region may be adjusted to account for variability in timing delays. In other embodiments, centroids may be calculated using either the location or the delay-weighted location of elements or cells within the path or cone and the centroids used to calculate timing slack variation factor. The timing slack variation factors are used to calculate a new timing slack for the path or logic cone of the circuit.
摘要翻译：提供了系统和方法，用于通过考虑电路的路径或逻辑锥中的单元或元件的位置来分析电路的定时，包括集成电路。在一个实施例中，可以围绕感兴趣的细胞或元件限定边界区域，并且可以使用边界区域的大小来计算定时松弛变化因子。可以调整边界区域的大小以考虑定时延迟的变化。在其他实施例中，可以使用路径或锥体内的元件或单元的位置或延迟加权位置以及用于计算定时松弛变化因子的质心来计算质心。定时松弛变化因子用于计算电路的路径或逻辑锥的新的定时松弛。

8. 发明申请

US20080072184A1 Method of Achieving Timing Closure in Digital Integrated Circuits by Optimizing Individual Macros 失效
标题翻译：通过优化单个宏来实现数字集成电路中的定时闭合的方法
公开(公告)号：US20080072184A1
公开(公告)日：2008-03-20
申请号：US11942034
申请日：2007-11-19
申请人： Jun Zhou , David Hathaway , Chandramouli Visweswariah , Patrick Williams
发明人： Jun Zhou , David Hathaway , Chandramouli Visweswariah , Patrick Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/505 , G06F2217/84
摘要： Disclosed is a method for enhanced efficiency and effectiveness in achieving closure of large, complex, high-performance digital integrated circuits. Circuit macros are re-optimized and re-tuned in the timing closure loop by means of a reformulated objective function that allows the optimizer to improve the slack of all signals rather than just the most critical one(s). The incentive to improve the timing of a sub-critical signal is a diminishing function of the criticality of the signal. Thus all signals are improved during the optimization, with the highest incentive to improve on the most critical signals, leading to faster and more effective overall timing closure.
摘要翻译：公开了一种用于提高大型，复杂，高性能数字集成电路闭合的效率和有效性的方法。电路宏通过重新配置的目标函数在时序闭合循环中重新优化和重新调整，允许优化器改善所有信号的松弛，而不仅仅是最关键的。改善次临界信号时序的动机是信号临界性的递减函数。因此，在优化期间，所有信号都得到改进，最高激励措施可以改善最关键的信号，从而实现更快更有效的整体时序收敛。

9. 发明申请

US20060265684A1 THE USE OF REDUNDANT ROUTES TO INCREASE THE YIELD AND RELIABILITY OF A VLSI LAYOUT 有权
标题翻译：使用冗余路由增加VLSI布局的可靠性
公开(公告)号：US20060265684A1
公开(公告)日：2006-11-23
申请号：US10908593
申请日：2005-05-18
申请人： Markus Buehler , John Cohn , David Hathaway , Jason Hibbeler , Juergen Koehl
发明人： Markus Buehler , John Cohn , David Hathaway , Jason Hibbeler , Juergen Koehl
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068
摘要： Disclosed is a method and system for inserting redundant paths into an integrated circuit. Particularly, the invention provides a method for identifying a single via in a first path connecting two elements, determining if an alternate route is available for connecting the two elements (other than a redundant via), and for inserting a second path into the available alternate route. The combination of the first and second paths provides greater redundancy than inserting a redundant via alone. More importantly, such redundant paths provide for redundancy when congestion prevents a redundant via from being inserted adjacent to the single via. An embodiment of the method further comprises removing the single via and any redundant wire segments, if all of the additional vias used to form the second path can be made redundant.
摘要翻译：公开了一种将冗余路径插入到集成电路中的方法和系统。特别地，本发明提供了一种用于在连接两个元件的第一路径中识别单个通孔的方法，确定替代路线是否可用于连接两个元件（不同于冗余通路），以及用于将第二路径插入到可用交替路线。第一和第二路径的组合提供了比单独插入冗余通道更大的冗余。更重要的是，当拥塞阻止冗余通道被插入邻近单个通道时，这种冗余路径提供了冗余。如果用于形成第二路径的所有附加通孔都可以是冗余的，则该方法的实施例还包括去除单个通孔和任何冗余线段。

10. 发明申请

US20080074147A1 WIRING OPTIMIZATIONS FOR POWER 有权
标题翻译：电力接线优化
公开(公告)号：US20080074147A1
公开(公告)日：2008-03-27
申请号：US11952544
申请日：2007-12-07
申请人： John Cohn , Alvar Dean , Amir Farrahi , David Hathaway , Thomas Lepsic , Jagannathan Narasimhan , Scott Tetreault , Sebastian Ventrone
发明人： John Cohn , Alvar Dean , Amir Farrahi , David Hathaway , Thomas Lepsic , Jagannathan Narasimhan , Scott Tetreault , Sebastian Ventrone
IPC分类号： H03K19/00 , G06F17/50
CPC分类号： G06F17/5072 , G06F17/5022 , G06F17/5077
摘要： An electrical wiring structure and a computer system for designing the electrical wiring structure. The electrical wiring structure includes a wire pair. The wire pair includes a first wire and a second wire. The second wire is slated for being tri-stated. The wire pair has a same-direction switching probability φSD per clock cycle that is no less than a pre-selected minimum same-direction switching probability φSD,MIN or has an opposite-direction switching probability φOD per clock cycle that is no less than a pre-selected minimum opposite-direction switching probability φOD,MIN. The first wire and the second wire satisfies at least one mathematical relationship involving LCOMMON and WSPACING, where WSPACING is defined as a spacing between the first wire and the second wire, and LCOMMON is defined as a common run length of the first wire and the second wire.
摘要翻译：一种用于设计电气布线结构的电气布线结构和计算机系统。电气配线结构包括电线对。线对包括第一线和第二线。第二根电线被预定为三态。线对具有不小于预先选择的最小相同方向切换概率phi，SD，MIN或/或具有相同方向的切换概率，每时钟周期每个时钟周期的相反方向切换概率Φ不小于预先选择的最小相对方向切换概率φi，MIN 。第一线和第二线满足至少一个数学关系，其涉及公平和平坦，其中，W SPACING 被定义为第一线和第二线，以及公共被定义为第一线和第二线的公共行程长度。

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