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1. 发明申请

US20050287786A1 Device and method using isotopically enriched silicon 失效
标题翻译：使用同位素富集硅的装置和方法
公开(公告)号：US20050287786A1
公开(公告)日：2005-12-29
申请号：US10875029
申请日：2004-06-23
申请人： Peter Gammel , Bailey Jones , Isik Kizilyalli , Hugo Safar
发明人： Peter Gammel , Bailey Jones , Isik Kizilyalli , Hugo Safar
IPC分类号： H01L21/20 , H01L21/322 , H01L21/336 , H01L21/4763 , H01L21/8234 , H01L21/8238 , H01L29/10 , H01L29/16 , H01L29/167 , H01L29/78
CPC分类号： H01L29/16 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/322 , H01L21/823412 , H01L21/823807 , H01L29/1033 , H01L29/167 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a process for manufacturing a semiconductor device that can be incorporated into an integrated circuit. The method includes, forming a first doped layer of isotopically enriched silicon over a foundational substrate, forming a second layer of an isotopically enriched semiconductor material silicon over the first doped layer, and constructing active devices on the second layer. The device includes a first doped layer of an isotopically enriched semiconductor material and a second layer of an isotopically enriched semiconductor material located over the first doped layer, and active devices located on the second layer.
摘要翻译：本发明提供一种可并入集成电路的半导体器件的制造方法。该方法包括：在基底衬底上形成同位素富集的硅的第一掺杂层，在第一掺杂层上形成同位素富集的半导体材料硅的第二层，以及在第二层上构建有源器件。该器件包括同位素富集的半导体材料的第一掺杂层和位于第一掺杂层上方的同位素富集的半导体材料的第二层以及位于第二层上的有源器件。

2. 发明申请

US20050077552A1 Metal-oxide-semiconductor device with enhanced source electrode 有权
标题翻译：具有增强型源电极的金属氧化物半导体器件
公开(公告)号：US20050077552A1
公开(公告)日：2005-04-14
申请号：US10673539
申请日：2003-09-29
申请人： Frank Baiocchi , Bailey Jones , Muhammed Shibib , Shuming Xu
发明人： Frank Baiocchi , Bailey Jones , Muhammed Shibib , Shuming Xu
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/08 , H01L29/417 , H01L29/45 , H01L29/76 , H01L29/78 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7835 , H01L29/0847 , H01L29/402 , H01L29/4175 , H01L29/456
摘要： An MOS device is formed including a semiconductor layer of a first conductivity type, a first source/drain region of a second conductivity type formed in the semiconductor layer, and a second source/drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the first source/drain region. A gate is formed proximate an upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. The MOS device further includes at least one contact, the at least one contact including a silicide layer formed on and in electrical connection with at least a portion of the first source/drain region, the silicide layer extending laterally away from the gate. The contact further includes at least one insulating layer formed directly on the silicide layer.
摘要翻译：形成MOS器件，其包括形成在半导体层中的第一导电类型的半导体层，第二导电类型的第一源极/漏极区域和形成在半导体层中的第二导电类型的第二源极/漏极区域，以及与第一源极/漏极区间隔开。栅极形成在半导体层的上表面附近并且至少部分地形成在第一和第二源/漏区之间。所述MOS器件还包括至少一个触点，所述至少一个触点包括在所述第一源极/漏极区域的至少一部分上形成并且与所述第一源极/漏极区域的至少一部分电连接的硅化物层，所述硅化物层从所述栅极横向延伸。触点还包括直接形成在硅化物层上的至少一个绝缘层。

3. 发明申请

US20060226552A1 Semiconductor structure formed using a sacrificial structure 有权
标题翻译：使用牺牲结构形成的半导体结构
公开(公告)号：US20060226552A1
公开(公告)日：2006-10-12
申请号：US11094975
申请日：2005-03-31
申请人： Bailey Jones , Sean Lian , Simon Molloy
发明人： Bailey Jones , Sean Lian , Simon Molloy
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L29/66681 , H01L21/76816 , H01L21/76838 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/42368 , H01L29/7816
摘要： A method of forming a buried conductive structure in a semiconductor device includes the steps of forming a first insulating layer on a semiconductor layer; forming a sacrificial structure on at least a portion of the first insulating layer; forming a second insulating layer on at least a portion of the sacrificial structure; forming at least one opening through the second insulating layer to at least partially expose the sacrificial structure; substantially removing the sacrificial structure, leaving a cavity; and substantially filling the cavity and the at least one opening with a conductive material. The sacrificial structure may be substantially removed by etching the sacrificial structure using an isotropic etchant.
摘要翻译：在半导体器件中形成掩埋导电结构的方法包括以下步骤：在半导体层上形成第一绝缘层; 在所述第一绝缘层的至少一部分上形成牺牲结构; 在所述牺牲结构的至少一部分上形成第二绝缘层; 通过所述第二绝缘层形成至少一个开口以至少部分地暴露所述牺牲结构; 基本上去除牺牲结构，留下空腔; 并且用导电材料基本上填充空腔和至少一个开口。可以通过使用各向同性蚀刻剂蚀刻牺牲结构来基本上去除牺牲结构。

4. 发明申请

US20050221563A1 Enhanced substrate contact for a semiconductor device 有权
标题翻译：用于半导体器件的增强的衬底接触
公开(公告)号：US20050221563A1
公开(公告)日：2005-10-06
申请号：US10814062
申请日：2004-03-31
申请人： Frank Baiocchi , Bailey Jones , Muhammed Shibib , Shuming Xu
发明人： Frank Baiocchi , Bailey Jones , Muhammed Shibib , Shuming Xu
IPC分类号： H01L21/20 , H01L21/336 , H01L29/417
CPC分类号： H01L29/66659 , H01L29/4175
摘要： A technique for forming a semiconductor structure in a semiconductor wafer includes the steps of forming an epitaxial layer on a least a portion of a semiconductor substrate of a first conductivity type and forming at least one trench in an upper surface of the semiconductor wafer and partially into the epitaxial layer. The method further includes the step of forming at least one diffusion region between a bottom wall of the trench and the substrate, the diffusion region providing an electrical path between the bottom wall of the trench and the substrate. One or more sidewalls of the trench are doped with a first impurity of a known concentration level so as to form an electrical path between an upper surface of the epitaxial layer and the at least one diffusion region. The trench is then filled with a filler material.
摘要翻译：在半导体晶片中形成半导体结构的技术包括以下步骤：在第一导电类型的半导体衬底的至少一部分上形成外延层，并在半导体晶片的上表面中形成至少一个沟槽，并部分地形成外延层。该方法还包括在沟槽的底壁和衬底之间形成至少一个扩散区域的步骤，扩散区域在沟槽的底壁和衬底之间提供电路径。掺杂具有已知浓度水平的第一杂质的沟槽的一个或多个侧壁，以便在外延层的上表面和至少一个扩散区之间形成电路径。然后用填充材料填充沟槽。

5. 发明申请

US20050093097A1 Enhanced substrate contact for a semiconductor device 有权
标题翻译：用于半导体器件的增强的衬底接触
公开(公告)号：US20050093097A1
公开(公告)日：2005-05-05
申请号：US10697757
申请日：2003-10-30
申请人： Frank Baiocchi , John Desko , Bailey Jones , Sean Lian
发明人： Frank Baiocchi , John Desko , Bailey Jones , Sean Lian
IPC分类号： H01L21/336 , H01L21/74 , H01L29/417 , H01L29/78 , H01L27/082
CPC分类号： H01L29/4175 , H01L21/743 , H01L29/66659 , H01L29/7835
摘要： A method of forming a semiconductor structure in a semiconductor wafer includes the steps of forming an epitaxial layer on at least a portion of a semiconductor substrate of a first conductivity type and forming at least one trench through the epitaxial layer to at least partially expose the substrate. The method further includes doping at least one or more sidewalls of the at least one trench with an impurity of a known concentration level. The at least one trench is then substantially filled with a filler material. In this manner, a low-resistance electrical path is formed between an upper surface of the epitaxial layer and the substrate.
摘要翻译：在半导体晶片中形成半导体结构的方法包括以下步骤：在第一导电类型的半导体衬底的至少一部分上形成外延层，并且通过外延层形成至少一个沟槽，以至少部分地暴露衬底。该方法还包括用已知浓度水平的杂质掺杂至少一个沟槽的至少一个或多个侧壁。然后至少一个沟槽基本上填充有填充材料。以这种方式，在外延层的上表面和基板之间形成低电阻电路径。

6. 发明授权

US06828649B2 Semiconductor device having an interconnect that electrically connects a conductive material and a doped layer, and a method of manufacture therefor 失效
标题翻译：具有电连接导电材料和掺杂层的互连的半导体器件及其制造方法
公开(公告)号：US06828649B2
公开(公告)日：2004-12-07
申请号：US10140616
申请日：2002-05-07
申请人： John C. Desko , Thomas J. Krutsick , Chung-Ming Hsieh , Brian E. Thompson , Bailey Jones , Steve Wallace
发明人： John C. Desko , Thomas J. Krutsick , Chung-Ming Hsieh , Brian E. Thompson , Bailey Jones , Steve Wallace
IPC分类号： H01L2900
CPC分类号： H01L21/763 , H01L21/743 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. In one advantageous embodiment, the semiconductor device includes a doped layer located over a semiconductor substrate, and an isolation trench located in the doped layer and having a dielectric layer located on a sidewall thereof. The semiconductor device may further include a conductive material located within the isolation trench and an interconnect that electrically connects the conductive material and the doped layer.
摘要翻译：本发明提供一种半导体器件及其制造方法以及包括该半导体器件的集成电路。在一个有利的实施例中，半导体器件包括位于半导体衬底上的掺杂层和位于掺杂层中并且位于其侧壁上的介电层的隔离沟槽。半导体器件还可以包括位于隔离沟槽内的导电材料和电连接导电材料和掺杂层的互连。

7. 发明授权

US06737311B2 Semiconductor device having a buried layer for reducing latchup and a method of manufacture therefor 有权
标题翻译：具有用于减少闭锁的掩埋层的半导体器件及其制造方法
公开(公告)号：US06737311B2
公开(公告)日：2004-05-18
申请号：US09964041
申请日：2001-09-26
申请人： John Desko , Chung-Ming Hsieh , Bailey Jones , Thomas J. Krutsick , Brian Thompson , Steve Wallace
发明人： John Desko , Chung-Ming Hsieh , Bailey Jones , Thomas J. Krutsick , Brian Thompson , Steve Wallace
IPC分类号： H01L2972
CPC分类号： H01L27/0921 , H01L21/823878 , H01L21/823892
摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device may include a well doped with a P-type dopant located over a semiconductor substrate. The semiconductor device may further include a buried layer including the P-type dopant located between the well and the semiconductor substrate, and a gate located over the well.
摘要翻译：本发明提供一种半导体器件及其制造方法以及包括半导体器件的集成电路。半导体器件可以包括掺杂有位于半导体衬底上的P型掺杂剂的阱。半导体器件还可以包括掩埋层，其包括位于阱和半导体衬底之间的P型掺杂剂，以及位于阱上方的栅极。

8. 发明申请

US20080054481A1 Semiconductor Structure Formed Using a Sacrificial Structure 失效
标题翻译：使用牺牲结构形成的半导体结构
公开(公告)号：US20080054481A1
公开(公告)日：2008-03-06
申请号：US11927978
申请日：2007-10-30
申请人： Bailey Jones , Sean Lian , Simon Molloy
发明人： Bailey Jones , Sean Lian , Simon Molloy
IPC分类号： H01L23/48
CPC分类号： H01L29/66681 , H01L21/76816 , H01L21/76838 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/42368 , H01L29/7816
摘要： A semiconductor structure is provided which eliminates the contact resistance traditionally associated with a junction between one or more contacts and a buried conductive structure formed in the semiconductor structure. The semiconductor structure includes a first insulating layer formed on a semiconductor layer and a conductive structure formed on at least a portion of the first insulating layer. A second insulating layer is formed on at least a portion of the conductive stricture. At least one contact is formed through the second insulating layer and electrically connected to the conductive structure. The contact and the conductive structure are formed as a substantially homogeneous structure in a same processing step.
摘要翻译：提供了一种半导体结构，其消除了传统上与一个或多个触点之间的接合和形成在半导体结构中的掩埋导电结构相关联的接触电阻。半导体结构包括形成在半导体层上的第一绝缘层和形成在第一绝缘层的至少一部分上的导电结构。在导电狭缝的至少一部分上形成第二绝缘层。通过第二绝缘层形成至少一个触点并与导电结构电连接。接触和导电结构在相同的处理步骤中形成为基本均匀的结构。

9. 发明申请

US20070007593A1 METAL-OXIDE-SEMICONDUCTOR DEVICE WITH ENHANCED SOURCE ELECTRODE 审中-公开
标题翻译：具有增强源电极的金属氧化物半导体器件
公开(公告)号：US20070007593A1
公开(公告)日：2007-01-11
申请号：US11532250
申请日：2006-09-15
申请人： Frank Baiocchi , Bailey Jones , Muhammed Shibib , Shuming Xu
发明人： Frank Baiocchi , Bailey Jones , Muhammed Shibib , Shuming Xu
IPC分类号： H01L29/76
CPC分类号： H01L29/7835 , H01L29/0847 , H01L29/402 , H01L29/4175 , H01L29/456
摘要： An MOS device is formed including a semiconductor layer of a first conductivity type, a first source/drain region of a second conductivity type formed in the semiconductor layer, and a second source/drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the first source/drain region. A gate is formed proximate an upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. The MOS device further includes at least one contact, the at least one contact including a silicide layer formed on and in electrical connection with at least a portion of the first source/drain region, the silicide layer extending laterally away from the gate. The contact further includes at least one insulating layer formed directly on the silicide layer.
摘要翻译：形成MOS器件，其包括形成在半导体层中的第一导电类型的半导体层，第二导电类型的第一源极/漏极区域和形成在半导体层中的第二导电类型的第二源极/漏极区域，以及与第一源极/漏极区间隔开。栅极形成在半导体层的上表面附近并且至少部分地形成在第一和第二源/漏区之间。所述MOS器件还包括至少一个触点，所述至少一个触点包括在所述第一源极/漏极区域的至少一部分上形成并且与所述第一源极/漏极区域的至少一部分电连接的硅化物层，所述硅化物层从所述栅极横向延伸。触点还包括直接形成在硅化物层上的至少一个绝缘层。

10. 发明申请

US20060038294A1 Metallization performance in electronic devices 有权
标题翻译：电子设备的金属化性能
公开(公告)号：US20060038294A1
公开(公告)日：2006-02-23
申请号：US10919591
申请日：2004-08-17
申请人： John Desko , Bailey Jones , Sean Lian , Simon Molloy , Vivian Ryan
发明人： John Desko , Bailey Jones , Sean Lian , Simon Molloy , Vivian Ryan
IPC分类号： H01L23/52
CPC分类号： H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： Phenomena such as electromigration and stress-induced migration occurring in metal interconnects of devices such as integrated circuits are inhibited by use of underlying non-planarities. Thus the material underlying the interconnect is formed to have non-planarities typically of at least 0.02 μm in height and advantageously within 100 μm of another such non-planarity. Such non-planarities, it is contemplated, reduce grain boundary movement in the overlying interconnect with a concomitant reduction in void aggregation.
摘要翻译：诸如集成电路的器件的金属互连中发生的诸如电迁移和应力诱发迁移的现象通过使用下面的非平面性被抑制。因此，互连下面的材料形成为具有通常在高度上通常为至少0.02μm的非平坦度，并且有利地在另一个这样的非平面性的100μm之内。可以预期的是，这种非平面性减少了上覆互连中的晶界运动，伴随着空隙聚集的降低。

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