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1. 发明申请

US20090285981A1 Method in the fabrication of a ferroelectric memory device 审中-公开
标题翻译：铁电存储器件的制造方法
公开(公告)号：US20090285981A1
公开(公告)日：2009-11-19
申请号：US11922052
申请日：2006-06-08
申请人： Peter Dyreklev , Geirr I. Leistad , Göran Gustafsson
发明人： Peter Dyreklev , Geirr I. Leistad , Göran Gustafsson
IPC分类号： B05D5/12
CPC分类号： H01L27/11507 , G11C11/22 , H01L27/11502 , H05K3/12
摘要： In a method in the fabrication of a ferroelectric memory device comprising a memory layer sandwiched between first and second electrode sets, the memory layer as well as both electrode sets are each realized in the memory device by a suitable printing process.
摘要翻译：在制造包含夹在第一和第二电极组之间的存储器层的铁电存储器件的方法中，存储器层以及两个电极组都通过合适的印刷工艺实现在存储器件中。

2. 发明授权

US07266008B2 Bimodal operation of ferroelectric and electret memory cells and devices 失效
标题翻译：铁电和驻极体存储器单元和器件的双峰操作
公开(公告)号：US07266008B2
公开(公告)日：2007-09-04
申请号：US11105350
申请日：2005-04-14
申请人： Hans Gude Gudesen , Geirr I Leistad , Isak Engquist , Göran Gustafsson
发明人： Hans Gude Gudesen , Geirr I Leistad , Isak Engquist , Göran Gustafsson
IPC分类号： G11C7/00
CPC分类号： G11C11/22
摘要： In a method for enhancing the data storage capability of ferroelectric or electret memory cell which has been applied to storage of data and attained an imprint condition, suitable voltage pulses are used for evoking a temporary relaxation of the imprint condition into a volatile polarization state that can be discriminated from the imprinted polarization state in a non-destructive readout operation. Sequences of one or more voltage pulses are used to evoke readout signals respectively indicative of a non-volatile and a volatile polarization state of the memory cell, but without altering said polarization states. Imprinted memory cells can be overwritten to effect a temporary and volatile storage of data in a memory device in a ferroelectric or electret memory device by assigning a first logical value to imprinted memory cells and a second logical value by transferring selected to memory cells transferred into a relaxed volatile state, whereby the stored logical values can be discriminated by the detecting the difference in dynamic response of respectively imprinted and relaxed memory cells.
摘要翻译：在用于增强已经应用于数据存储和达到印记条件的铁电或驻极体存储单元的数据存储能力的方法中，使用适当的电压脉冲来引起压印条件的暂时放宽到易挥发的极化状态，在非破坏性读出操作中与印刻偏振状态区分开来。使用一个或多个电压脉冲的序列来唤起分别指示存储器单元的非易失性和易失性极化状态但不改变所述极化状态的读出信号。印刷的存储器单元可以被覆盖，以通过将所选择的第一逻辑值分配给压印存储器单元并将所转移的存储器单元传送到第二逻辑值来实现在铁电或驻极体存储器件中的存储器件中的数据的临时和易失性存储轻松的挥发性状态，由此可以通过检测分别压印和放松的存储单元的动态响应的差异来区分所存储的逻辑值。

3. 发明授权

US08184467B2 Card-like memory unit with separate read/write unit 有权
标题翻译：带有单独读/写单元的卡状存储单元
公开(公告)号：US08184467B2
公开(公告)日：2012-05-22
申请号：US11917571
申请日：2006-06-08
申请人： Per Bröms , Christer Karlsson , Geirr I. Leistad , Per Hamberg , Staffan Björklid , Johan Carlsson , Göran Gustafsson , Hans Gude Gudesen
发明人： Per Bröms , Christer Karlsson , Geirr I. Leistad , Per Hamberg , Staffan Björklid , Johan Carlsson , Göran Gustafsson , Hans Gude Gudesen
IPC分类号： G11C11/22
CPC分类号： G06K7/0021 , B82Y10/00 , G11B9/02 , G11B9/1454 , G11C11/22 , G11C11/5664 , G11C13/0009 , G11C13/0014 , G11C13/0016
摘要： In a non-volatile electric memory system a memory unit and a read/write unit are provided as physically separate units. The memory unit is based on a memory material that can be set to at least two distinct physical states by applying an electric field across the memory material. Electrodes and/or contacts are either provided in the memory unit or in the read/write unit and contacts are at least always provided in the read/write unit. Electrodes and contacts are provided in a geometrical arrangement, which defines geometrically one or more memory cells in the memory layer. Establishing a physical contact between the memory unit and the read/write unit closes an electrical circuit over the addressed memory cell such that read, write or erase operations can be effected. The memory material of the memory unit can be polarized into two discernible polarization states.
摘要翻译：在非易失性电存储器系统中，存储单元和读/写单元被提供为物理上分离的单元。存储器单元基于可以通过在存储器材料上施加电场而被设置为至少两种不同物理状态的存储器材料。电极和/或触点被提供在存储器单元中或读/写单元中，并且触点至少总是设置在读/写单元中。电极和触点以几何布置提供，其几何地限定存储器层中的一个或多个存储器单元。在存储器单元和读/写单元之间建立物理接触关闭寻址的存储单元上的电路，从而可以实现读，写或擦除操作。存储器单元的存储材料可以被偏振成两个可识别的偏振状态。

4. 发明授权

US06787825B1 Data storage and processing apparatus, and method for fabricating the same 有权
标题翻译：数据存储和处理装置及其制造方法
公开(公告)号：US06787825B1
公开(公告)日：2004-09-07
申请号：US09463906
申请日：2001-01-02
申请人： Hans Gude Gudesen , Per-Erik Nordal , Geirr I. Leistad , Johan Carlsson , Göran Gustafsson , Michael O Thompson
发明人： Hans Gude Gudesen , Per-Erik Nordal , Geirr I. Leistad , Johan Carlsson , Göran Gustafsson , Michael O Thompson
IPC分类号： H01L2980
CPC分类号： H01L21/02686 , G11C5/02 , G11C17/06 , H01L21/02532 , H01L21/02689 , H01L21/2026 , H01L21/768 , H01L21/76888 , H01L21/76894 , H01L21/8221 , H01L27/0688 , H01L27/1021 , H01L27/105 , H01L27/1052 , H01L27/108 , H01L27/11 , H01L27/11502 , H01L51/0001 , H01L51/0024 , H01L2924/0002 , H01L2924/00
摘要： A data storage/processing apparatus includes ROM and/or WORM and/or REWRITEABLE memory modules and/or processing modules provided as a single main layer or multiple main layers on top of a substrate. Transistors and/or diodes operate the apparatus. In one set of embodiments, at least some of the transistors and/or diodes are provided on or in the substrate. In another set of embodiments, at least some of the layers on the top of the substrate include low-temperature compatible organic materials and/or low temperature compatible processes inorganic films, and the transistors and/or diodes need not be disposed on or in the substrate. In a related fabricating method, the memory and/or processing modules are provided on the substrate by depositing the layers in successive steps under thermal conditions that avoid subjecting an already-deposited, processed underlying layers to static or dynamic temperatures exceeding given stability limits, particularly with regard to organic materials.
摘要翻译：数据存储/处理装置包括在基板顶部上作为单个主层或多个主层提供的ROM和/或WORM和/或REWRITEABLE存储器模块和/或处理模块。晶体管和/或二极管操作该装置。在一组实施例中，晶体管和/或二极管中的至少一些设置在衬底上或衬底中。在另一组实施例中，衬底顶部上的至少一些层包括低温兼容的有机材料和/或低温兼容的无机膜，并且晶体管和/或二极管不需要被置于或基质。在相关制造方法中，存储器和/或处理模块通过在热条件下的连续步骤中沉积层而提供在衬底上，避免了已经沉积的经处理的下层在超过给定稳定极限的静态或动态温度下，特别是关于有机材料。

5. 发明申请

US20110011179A1 Moister sensor 有权
标题翻译： Moister传感器
公开(公告)号：US20110011179A1
公开(公告)日：2011-01-20
申请号：US12805039
申请日：2010-07-08
申请人： Göran Gustafsson , Xavier Crispin , Magnus Berggren , Oscar Larsson , Xiaodong Wang
发明人： Göran Gustafsson , Xavier Crispin , Magnus Berggren , Oscar Larsson , Xiaodong Wang
IPC分类号： G01N27/02 , H05K3/00
CPC分类号： G01N27/223 , Y10T29/49155
摘要： A moister sensor, for measuring moister in a building without leaving visible scars to the building surface, is provided. The moister sensor includes a flexible carrier carrying an antenna for receiving EM-radiation between 9 kHz and 11 MHz and a resonant circuit including a moister reactive element. The moister reactive element includes a hygroscopic electrolyte arranged between a first and a second electrode, wherein the electrolyte in the presence of moister forms mobile ions and provides a complex impedance at least in response to the alternating voltage, which complex impedance varies with the moister content of the electrolyte.
摘要翻译：提供了一种用于测量建筑物中的湿度的湿度传感器，而不会留下可见的疤痕到建筑物表面。湿度传感器包括承载用于接收9kHz和11MHz之间的EM辐射的天线的柔性载体以及包括一个不起作用的元件的谐振电路。吸湿反应元件包括布置在第一和第二电极之间的吸湿电解质，其中在存在气雾的情况下的电解质形成移动离子，并且至少响应于交变电压提供复阻抗，该复阻抗随着气味含量而变化的电解液。

6. 发明授权

US07215565B2 Method for operating a passive matrix-addressable ferroelectric or electret memory device 失效
标题翻译：用于操作无源矩阵寻址铁电或驻极体存储器件的方法
公开(公告)号：US07215565B2
公开(公告)日：2007-05-08
申请号：US11027977
申请日：2005-01-04
申请人： Christer Karlsson , Göran Gustafsson , Mats Johansson , Per Sandström , Per-Erik Nordal , Hans Gude Gudesen , Johan Carlsson
发明人： Christer Karlsson , Göran Gustafsson , Mats Johansson , Per Sandström , Per-Erik Nordal , Hans Gude Gudesen , Johan Carlsson
IPC分类号： G11C11/22
CPC分类号： G11C29/50 , G11C11/22
摘要： In a method for operating a passive matrix-addressable ferroelectric or electret memory device, a voltage pulse protocol based on a 1/3 voltage selection rule is used in order to keep disturb voltages at minimum, the voltage pulse protocol comprising cycles for read and write/erase bases on time sequence of voltage pulses with defined parameters. The method comprises a refresh procedure wherein cells for refresh are selected and refresh requests processed by a memory device controller, the refresh requests are monitored and processed in regard of ongoing or scheduled memory operations, and refresh voltage pulses with defined parameters are applied to the memory cells selected for refresh, while simultaneously ensuring that non-selected memory cells are subjected to zero voltage or voltages which do not affect the polarization state of these cells.
摘要翻译：在用于操作无源矩阵寻址铁电或驻极体存储器件的方法中，使用基于1/3电压选择规则的电压脉冲协议以便将干扰电压保持在最小值，所述电压脉冲协议包括用于读取和写入的周期根据具有定义参数的电压脉冲的时间顺序进行擦除。该方法包括刷新过程，其中选择用于刷新的单元和由存储器件控制器处理的刷新请求，关于正在进行或调度的存储器操作来监视和处理刷新请求，并且将具有所定义参数的刷新电压脉冲施加到存储器选择用于刷新的单元，同时确保未选择的存储单元经受不影响这些单元的极化状态的零电压或电压。

7. 发明授权

US06804138B2 Addressing of memory matrix 有权
标题翻译：存储矩阵的寻址
公开(公告)号：US06804138B2
公开(公告)日：2004-10-12
申请号：US09899093
申请日：2001-07-06
申请人： Michael O. Thompson , Per-Erik Nordal , Hans Gude Gudesen , Johan Carlsson , Göran Gustafsson
发明人： Michael O. Thompson , Per-Erik Nordal , Hans Gude Gudesen , Johan Carlsson , Göran Gustafsson
IPC分类号： G11C1122
CPC分类号： G11C11/22 , G09G3/20 , G09G3/3629 , G09G2300/06 , G09G2310/0251 , G09G2320/0209 , G11C7/06 , G11C7/1006 , G11C8/18
摘要： In a method of driving a passive matrix display or memory array of cells comprising an electrically polarizable material exhibiting hysteresis, in particular a ferroelectric material, wherein the polarization state of individual cells can be switched by application of electric potentials or voltages to word and bit lines in the matrix or array, a potential on selected word and bit lines is controlled to approach or coincide with one of n predefined potential levels and the potentials on all word and bit lines are controlled in time according to a protocol such that word lines are sequentially latched to potentials selected among nWORD potentials, while the bit lines are either latched sequentially to potentials selected among nBIT potentials, or during a certain period of a timing sequence given by the protocol connected to circuitry for detecting charges flowing between a bit line or bit lines and cells connecting thereto. This timing sequence is provided with a read cycle during which charges flowing between the selected bit line or bit lines connecting thereto are detected and a “refresh/write cycle” during which the polarization of the cells connecting with selected word and bit lines are brought to correspond with a set of predetermined values.
摘要翻译：在驱动无源矩阵显示器或存储阵列存储器阵列的方法中，该阵列包括具有磁滞的电可极化材料，特别是铁电材料，其中可以通过向字和位线施加电位或电压来切换各个单元的极化状态在矩阵或阵列中，选择的字和位线上的电位被控制为接近或与n个预定义的电位电平中的一个一致，并且根据协议在时间上控制所有字和位线上的电位，使得字线依次锁存到nWORD电位中选择的电位，而位线被顺序锁存到从nBIT电位中选择的电位，或者在连接到用于检测在位线或位线之间流动的电荷的电路的协议给定的定时序列的特定时段期间和与其连接的单元。该定时序列被提供有读取周期，在该循环期间检测在所选择的位线或连接到其之间的位线之间流动的电荷以及与所选择的字和位线连接的单元的极化被带到“刷新/写入周期” 对应于一组预定值。

8. 发明授权

US07646013B2 Transistor with large ion-complexes in electrolyte layer 失效
标题翻译：在电解质层中具有大离子络合物的晶体管
公开(公告)号：US07646013B2
公开(公告)日：2010-01-12
申请号：US11594995
申请日：2006-11-09
申请人： Lars Herlogsson , Göran Gustafsson , Olle-Johnny Hagel , Mats Sandberg , Magnus Berggren , Xavier Crispin , Nathaniel Robinson
发明人： Lars Herlogsson , Göran Gustafsson , Olle-Johnny Hagel , Mats Sandberg , Magnus Berggren , Xavier Crispin , Nathaniel Robinson
IPC分类号： H01L51/00
CPC分类号： H01L51/0516 , H01L51/002 , H01L51/0541
摘要： A fast organic field effect transistor (100), which operates at low voltages, is achieved by the introduction of an oligomeric or polymeric electrolyte (131) between the gate electrode (141) and the organic semiconductor layer (121), which electrolyte (131) has a dissociation constant of at least 10−8. Said organic semiconductor layer (121) is in contact with the source electrode (111) and the drain electrode (112) of the transistor. In operation a potential (152) applied to said gate electrode (141) controls the current A between said source electrode (111) and said drain electrode (112).
摘要翻译：通过在栅电极（141）和有机半导体层（121）之间引入低聚或高分子电解质（131）来实现在低电压下工作的快速有机场效应晶体管（100），该电解质）具有至少10-8的解离常数。所述有机半导体层（121）与晶体管的源电极（111）和漏电极（112）接触。在操作中，施加到所述栅极（141）的电位（152）控制所述源电极（111）和所述漏电极（112）之间的电流A.

9. 发明授权

US08236164B2 Moisture sensor 有权
标题翻译：水分传感器
公开(公告)号：US08236164B2
公开(公告)日：2012-08-07
申请号：US12805039
申请日：2010-07-08
申请人： Göran Gustafsson , Xavier Crispin , Magnus Berggren , Oscar Larsson , Xiaodong Wang
发明人： Göran Gustafsson , Xavier Crispin , Magnus Berggren , Oscar Larsson , Xiaodong Wang
IPC分类号： G01N7/04
CPC分类号： G01N27/223 , Y10T29/49155
摘要： A moisture sensor, for measuring moisture in a building without leaving visible scars to the building surface, is provided. The moisture sensor includes a flexible carrier carrying an antenna for receiving EM-radiation between 9 kHz and 11 MHz and a resonant circuit including a moisture reactive element. The moisture reactive element includes a hygroscopic electrolyte arranged between a first and a second electrode, wherein the electrolyte in the presence of moisture forms mobile ions and provides a complex impedance at least in response to the alternating voltage, which complex impedance varies with the moisture content of the electrolyte.
摘要翻译：一种湿度传感器，用于测量建筑物中的水分，而不会留下可见的疤痕到建筑物表面。水分传感器包括一个携带用于接收9kHz至11MHz之间的EM辐射的天线的柔性载体和包括一个湿度反应元件的谐振电路。湿气反应元件包括布置在第一和第二电极之间的吸湿电解质，其中在存在潮气的情况下电解质形成移动离子并且至少响应于交变电压提供复阻抗，该复阻抗随着水分含量而变化的电解液。

10. 发明授权

US07211885B2 Vertical electrical interconnections in a stack 失效
标题翻译：堆叠中的垂直电气互连
公开(公告)号：US07211885B2
公开(公告)日：2007-05-01
申请号：US10390178
申请日：2003-03-14
申请人： Per-Erik Nordal , Hans Gude Gudesen , Geirr Ivarsson Leidstad , Göran Gustafsson , Johan Carlsson
发明人： Per-Erik Nordal , Hans Gude Gudesen , Geirr Ivarsson Leidstad , Göran Gustafsson , Johan Carlsson
IPC分类号： H01L23/02
CPC分类号： H01L24/25 , H01L24/24 , H01L24/82 , H01L25/0657 , H01L2224/24051 , H01L2224/24145 , H01L2224/24146 , H01L2224/24225 , H01L2224/24226 , H01L2224/25175 , H01L2224/76155 , H01L2224/82102 , H01L2225/06524 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06562 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01033 , H01L2924/01055 , H01L2924/01057 , H01L2924/01074 , H01L2924/01082 , H01L2924/10253 , H01L2924/14 , H01L2924/30105 , H01L2924/00
摘要： In a memory and/or data processing device having at least two stacked layers which are supported by a substrate or forming a sandwiched self-supporting structure, wherein the layers include memory and/or processing circuitry with mutual connections between the layers and/or to circuitry in the substrate, the layers the are mutually arranged such that contiguous layers form a staggered structure on at least one edge of the device and at least one electrical edge conductor is provided passing over the edge on one layer and down one step at a time, enabling the connection to an electrical conductor in any of the following layers in the stack. A method for manufacturing a device of this kind includes the steps for adding the layers successively, one layer at a time, such that the layers form a staggered structure, and for providing one or more layers with at least one electrical contact pad for linking to one or more interlayer edge connectors.
摘要翻译：在具有由衬底支撑或形成夹层自支撑结构的至少两个层叠层的存储器和/或数据处理设备中，其中所述层包括存储器和/或处理电路，所述存储器和/或处理电路具有层之间的相互连接和/或电路在衬底中，这些层被相互布置，使得连续的层在器件的至少一个边缘上形成交错的结构，并且至少一个电气边缘导体被提供在一个层上沿着边缘通过并且一次一个下降，使得能够连接到堆叠中的以下任何层中的电导体。用于制造这种装置的方法包括以下步骤：一次一层地层叠这些层，使得这些层形成交错结构，并且用于提供一层或多层具有至少一个电接触垫，用于连接到一个或多个夹层边缘连接器。

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