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1. 发明授权

US06950330B2 Addressing of memory matrix 有权
公开(公告)号：US06950330B2
公开(公告)日：2005-09-27
申请号：US10934573
申请日：2004-09-07
申请人： Michael O. Thompson , Per-Erik Nordal , Hans Gude Gudesen , Johan Carlsson , Göran Gustafsson
发明人： Michael O. Thompson , Per-Erik Nordal , Hans Gude Gudesen , Johan Carlsson , Göran Gustafsson
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36 , G11C7/06 , G11C7/10 , G11C8/18 , G11C11/22
CPC分类号： G11C11/22 , G09G3/20 , G09G3/3629 , G09G2300/06 , G09G2310/0251 , G09G2320/0209 , G11C7/06 , G11C7/1006 , G11C8/18
摘要： A method of driving a passive matrix display or memory array of cells comprising an electrically polarizable material exhibiting hysteresis, in particular a ferroelectric material, wherein the polarization state of individual cells can be switched by application of electric potentials or voltages to word and bit lines in the matrix or array.

2. 发明授权

US06787825B1 Data storage and processing apparatus, and method for fabricating the same 有权
标题翻译：数据存储和处理装置及其制造方法
公开(公告)号：US06787825B1
公开(公告)日：2004-09-07
申请号：US09463906
申请日：2001-01-02
申请人： Hans Gude Gudesen , Per-Erik Nordal , Geirr I. Leistad , Johan Carlsson , Göran Gustafsson , Michael O Thompson
发明人： Hans Gude Gudesen , Per-Erik Nordal , Geirr I. Leistad , Johan Carlsson , Göran Gustafsson , Michael O Thompson
IPC分类号： H01L2980
CPC分类号： H01L21/02686 , G11C5/02 , G11C17/06 , H01L21/02532 , H01L21/02689 , H01L21/2026 , H01L21/768 , H01L21/76888 , H01L21/76894 , H01L21/8221 , H01L27/0688 , H01L27/1021 , H01L27/105 , H01L27/1052 , H01L27/108 , H01L27/11 , H01L27/11502 , H01L51/0001 , H01L51/0024 , H01L2924/0002 , H01L2924/00
摘要： A data storage/processing apparatus includes ROM and/or WORM and/or REWRITEABLE memory modules and/or processing modules provided as a single main layer or multiple main layers on top of a substrate. Transistors and/or diodes operate the apparatus. In one set of embodiments, at least some of the transistors and/or diodes are provided on or in the substrate. In another set of embodiments, at least some of the layers on the top of the substrate include low-temperature compatible organic materials and/or low temperature compatible processes inorganic films, and the transistors and/or diodes need not be disposed on or in the substrate. In a related fabricating method, the memory and/or processing modules are provided on the substrate by depositing the layers in successive steps under thermal conditions that avoid subjecting an already-deposited, processed underlying layers to static or dynamic temperatures exceeding given stability limits, particularly with regard to organic materials.
摘要翻译：数据存储/处理装置包括在基板顶部上作为单个主层或多个主层提供的ROM和/或WORM和/或REWRITEABLE存储器模块和/或处理模块。晶体管和/或二极管操作该装置。在一组实施例中，晶体管和/或二极管中的至少一些设置在衬底上或衬底中。在另一组实施例中，衬底顶部上的至少一些层包括低温兼容的有机材料和/或低温兼容的无机膜，并且晶体管和/或二极管不需要被置于或基质。在相关制造方法中，存储器和/或处理模块通过在热条件下的连续步骤中沉积层而提供在衬底上，避免了已经沉积的经处理的下层在超过给定稳定极限的静态或动态温度下，特别是关于有机材料。

3. 发明授权

US06804138B2 Addressing of memory matrix 有权
标题翻译：存储矩阵的寻址
公开(公告)号：US06804138B2
公开(公告)日：2004-10-12
申请号：US09899093
申请日：2001-07-06
申请人： Michael O. Thompson , Per-Erik Nordal , Hans Gude Gudesen , Johan Carlsson , Göran Gustafsson
发明人： Michael O. Thompson , Per-Erik Nordal , Hans Gude Gudesen , Johan Carlsson , Göran Gustafsson
IPC分类号： G11C1122
CPC分类号： G11C11/22 , G09G3/20 , G09G3/3629 , G09G2300/06 , G09G2310/0251 , G09G2320/0209 , G11C7/06 , G11C7/1006 , G11C8/18
摘要： In a method of driving a passive matrix display or memory array of cells comprising an electrically polarizable material exhibiting hysteresis, in particular a ferroelectric material, wherein the polarization state of individual cells can be switched by application of electric potentials or voltages to word and bit lines in the matrix or array, a potential on selected word and bit lines is controlled to approach or coincide with one of n predefined potential levels and the potentials on all word and bit lines are controlled in time according to a protocol such that word lines are sequentially latched to potentials selected among nWORD potentials, while the bit lines are either latched sequentially to potentials selected among nBIT potentials, or during a certain period of a timing sequence given by the protocol connected to circuitry for detecting charges flowing between a bit line or bit lines and cells connecting thereto. This timing sequence is provided with a read cycle during which charges flowing between the selected bit line or bit lines connecting thereto are detected and a “refresh/write cycle” during which the polarization of the cells connecting with selected word and bit lines are brought to correspond with a set of predetermined values.
摘要翻译：在驱动无源矩阵显示器或存储阵列存储器阵列的方法中，该阵列包括具有磁滞的电可极化材料，特别是铁电材料，其中可以通过向字和位线施加电位或电压来切换各个单元的极化状态在矩阵或阵列中，选择的字和位线上的电位被控制为接近或与n个预定义的电位电平中的一个一致，并且根据协议在时间上控制所有字和位线上的电位，使得字线依次锁存到nWORD电位中选择的电位，而位线被顺序锁存到从nBIT电位中选择的电位，或者在连接到用于检测在位线或位线之间流动的电荷的电路的协议给定的定时序列的特定时段期间和与其连接的单元。该定时序列被提供有读取周期，在该循环期间检测在所选择的位线或连接到其之间的位线之间流动的电荷以及与所选择的字和位线连接的单元的极化被带到“刷新/写入周期” 对应于一组预定值。

4. 发明授权

US07211885B2 Vertical electrical interconnections in a stack 失效
标题翻译：堆叠中的垂直电气互连
公开(公告)号：US07211885B2
公开(公告)日：2007-05-01
申请号：US10390178
申请日：2003-03-14
申请人： Per-Erik Nordal , Hans Gude Gudesen , Geirr Ivarsson Leidstad , Göran Gustafsson , Johan Carlsson
发明人： Per-Erik Nordal , Hans Gude Gudesen , Geirr Ivarsson Leidstad , Göran Gustafsson , Johan Carlsson
IPC分类号： H01L23/02
CPC分类号： H01L24/25 , H01L24/24 , H01L24/82 , H01L25/0657 , H01L2224/24051 , H01L2224/24145 , H01L2224/24146 , H01L2224/24225 , H01L2224/24226 , H01L2224/25175 , H01L2224/76155 , H01L2224/82102 , H01L2225/06524 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06562 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01033 , H01L2924/01055 , H01L2924/01057 , H01L2924/01074 , H01L2924/01082 , H01L2924/10253 , H01L2924/14 , H01L2924/30105 , H01L2924/00
摘要： In a memory and/or data processing device having at least two stacked layers which are supported by a substrate or forming a sandwiched self-supporting structure, wherein the layers include memory and/or processing circuitry with mutual connections between the layers and/or to circuitry in the substrate, the layers the are mutually arranged such that contiguous layers form a staggered structure on at least one edge of the device and at least one electrical edge conductor is provided passing over the edge on one layer and down one step at a time, enabling the connection to an electrical conductor in any of the following layers in the stack. A method for manufacturing a device of this kind includes the steps for adding the layers successively, one layer at a time, such that the layers form a staggered structure, and for providing one or more layers with at least one electrical contact pad for linking to one or more interlayer edge connectors.
摘要翻译：在具有由衬底支撑或形成夹层自支撑结构的至少两个层叠层的存储器和/或数据处理设备中，其中所述层包括存储器和/或处理电路，所述存储器和/或处理电路具有层之间的相互连接和/或电路在衬底中，这些层被相互布置，使得连续的层在器件的至少一个边缘上形成交错的结构，并且至少一个电气边缘导体被提供在一个层上沿着边缘通过并且一次一个下降，使得能够连接到堆叠中的以下任何层中的电导体。用于制造这种装置的方法包括以下步骤：一次一层地层叠这些层，使得这些层形成交错结构，并且用于提供一层或多层具有至少一个电接触垫，用于连接到一个或多个夹层边缘连接器。

5. 发明授权

US07215565B2 Method for operating a passive matrix-addressable ferroelectric or electret memory device 失效
标题翻译：用于操作无源矩阵寻址铁电或驻极体存储器件的方法
公开(公告)号：US07215565B2
公开(公告)日：2007-05-08
申请号：US11027977
申请日：2005-01-04
申请人： Christer Karlsson , Göran Gustafsson , Mats Johansson , Per Sandström , Per-Erik Nordal , Hans Gude Gudesen , Johan Carlsson
发明人： Christer Karlsson , Göran Gustafsson , Mats Johansson , Per Sandström , Per-Erik Nordal , Hans Gude Gudesen , Johan Carlsson
IPC分类号： G11C11/22
CPC分类号： G11C29/50 , G11C11/22
摘要： In a method for operating a passive matrix-addressable ferroelectric or electret memory device, a voltage pulse protocol based on a 1/3 voltage selection rule is used in order to keep disturb voltages at minimum, the voltage pulse protocol comprising cycles for read and write/erase bases on time sequence of voltage pulses with defined parameters. The method comprises a refresh procedure wherein cells for refresh are selected and refresh requests processed by a memory device controller, the refresh requests are monitored and processed in regard of ongoing or scheduled memory operations, and refresh voltage pulses with defined parameters are applied to the memory cells selected for refresh, while simultaneously ensuring that non-selected memory cells are subjected to zero voltage or voltages which do not affect the polarization state of these cells.
摘要翻译：在用于操作无源矩阵寻址铁电或驻极体存储器件的方法中，使用基于1/3电压选择规则的电压脉冲协议以便将干扰电压保持在最小值，所述电压脉冲协议包括用于读取和写入的周期根据具有定义参数的电压脉冲的时间顺序进行擦除。该方法包括刷新过程，其中选择用于刷新的单元和由存储器件控制器处理的刷新请求，关于正在进行或调度的存储器操作来监视和处理刷新请求，并且将具有所定义参数的刷新电压脉冲施加到存储器选择用于刷新的单元，同时确保未选择的存储单元经受不影响这些单元的极化状态的零电压或电压。

6. 发明授权

US07265379B2 Organic electronic device and methods for manufacturing a device of this kind 失效
标题翻译：有机电子装置及其制造方法
公开(公告)号：US07265379B2
公开(公告)日：2007-09-04
申请号：US11088194
申请日：2005-03-24
申请人： Mats Sandberg , Per-Erik Nordal , Grzegorz Greczynski , Mats Johansson , Per Carlsen , Hans Gude Gudesen , Göran Gustafsson , Linda Andersson
发明人： Mats Sandberg , Per-Erik Nordal , Grzegorz Greczynski , Mats Johansson , Per Carlsen , Hans Gude Gudesen , Göran Gustafsson , Linda Andersson
IPC分类号： H01L29/08 , H01L35/24 , H01L51/00
CPC分类号： G11C13/0014 , B82Y10/00 , G11C13/0016 , G11C2213/55 , H01L51/0025 , H01L51/0026 , H01L51/0034 , H01L51/0043 , H01L51/005
摘要： An organic electronic device consists of one or more electro-active organic or polymer materials sandwiched between electrodes. Critical in such devices is the interface between the electrode and the polymer, where degradation or chemical reaction products may develop that are deleterious to the proper functioning of the device. This is solved by introducing a functional interlayer composed of one or more materials consisting of a molecular backbone bearing phosphonate or phosphate functions, either directly attached or through side chains, said functional layer being disposed between at least one of the respective electrodes and said one or more electro-active materials in the device.
摘要翻译：有机电子器件由夹在电极之间的一种或多种电活性有机或聚合物材料组成。在这种装置中的关键是电极和聚合物之间的界面，其中可能产生对装置的正常功能有害的降解或化学反应产物。这通过引入由一种或多种由含有膦酸酯或磷酸酯官能团的分子骨架组成的材料构成的功能性夹层来解决，直接连接或通过侧链，所述功能层设置在至少一个相应的电极之间，更多的电活性材料在设备中。

7. 发明授权

US07352612B2 Method for operating a data storage apparatus employing passive matrix addressing 失效
标题翻译：用于操作采用无源矩阵寻址的数据存储装置的方法
公开(公告)号：US07352612B2
公开(公告)日：2008-04-01
申请号：US10579968
申请日：2004-11-24
申请人： Per Hamberg , Christer Karlsson , Per-Erik Nordal , Nicklas Ojakangas , Johan Carlsson , Hans Gude Gudesen
发明人： Per Hamberg , Christer Karlsson , Per-Erik Nordal , Nicklas Ojakangas , Johan Carlsson , Hans Gude Gudesen
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G06F12/0238 , G06F2212/1036 , G06F2212/7211 , G11C8/12 , G11C2013/0083
摘要： In a method for reducing detrimental phenomena related to disturb voltages in a data storage apparatus employing passive matrix addressing, particularly a memory device or a sensor device, an application of electric potentials conforming to an addressing operation is generally controlled in a time-coordinated manner according to a voltage pulse protocol. In an addressing operation a data storage cell is set to a first polarization state by means of a first active voltage pulse and then, dependent on the voltage pulse protocol, a second voltage pulse which may be a second active voltage pulse of opposite polarity to that of the first voltage pulse, is applied and used for switching the data storage cell to a second polarization state. The addressed cell is thus set to a predetermined polarization state as specified by the addressing operation. The data storage cells of the apparatus are provided in two or more electrically separated segments such that each segment comprises a separate physical address space for the apparatus. In an addressing operation the data are directed to a segment that is selected based on information on prior and/or scheduled applications of active voltage pulses to the segments.
摘要翻译：在采用无源矩阵寻址的数据存储装置，特别是存储装置或传感器装置中减少与干扰电压有关的有害现象的方法中，通常按时间协调方式控制符合寻址操作的电位的应用，到电压脉冲协议。在寻址操作中，通过第一有效电压脉冲将数据存储单元设置为第一偏振状态，然后根据电压脉冲协议设置第二电压脉冲，该第二电压脉冲可以是具有相反极性的第二有源电压脉冲的第一电压脉冲被施加并用于将数据存储单元切换到第二极化状态。因此，所寻址的单元被设置为由寻址操作指定的预定极化状态。设备的数据存储单元被提供在两个或更多个电分离的段中，使得每个段包括用于该设备的单独的物理地址空间。在寻址操作中，数据被引导到基于关于有效电压脉冲到段的先前和/或预定应用的信息而被选择的段。

8. 发明授权

US06541869B1 Scalable data processing apparatus 失效
标题翻译：可扩展数据处理设备
公开(公告)号：US06541869B1
公开(公告)日：2003-04-01
申请号：US09601457
申请日：2000-09-18
申请人： Hans Gude Gudesen , Per-Erik Nordal , Geirr I. Leistad , Rolf Magnue Berggren , Bengt Göran Gustafsson , Johan Roger Axel Karlsson
发明人： Hans Gude Gudesen , Per-Erik Nordal , Geirr I. Leistad , Rolf Magnue Berggren , Bengt Göran Gustafsson , Johan Roger Axel Karlsson
IPC分类号： H01L2348
CPC分类号： G11C11/22 , B82Y10/00 , G11C5/02 , H01L25/0657 , H01L2224/32145 , H01L2225/06527 , H01L2225/06541 , H01L2225/06551 , H01L2225/06555 , H01L2225/06572 , H01L2924/3011
摘要： In a scalable data processing apparatus, particularly a data storage apparatus, one or more thin-film devices which form a substantially planar layer comprise a plurality of sublayers of thin film. Two or more thin-film devices are provided as an integrated stack of the substantially planar layers which form the thin-film devices, such that the apparatus thereby forms a stacked configuration. Each thin-film device comprises one or more memory areas which form matrix addressable memories and additionally circuit areas which form electronic thin-film circuitry for controlling, driving and addressing memory cells in one or more memories. Each memory device has an interface to every other thin-film device in the apparatus, said interfaces being realized with communication and signal lines as well as supporting circuitry for processing extending vertically through dedicated interface areas in the thin-film device.
摘要翻译：在可伸缩的数据处理装置，特别是数据存储装置中，形成基本平坦的层的一个或多个薄膜装置包括多个薄膜子层。提供两个或更多个薄膜器件作为形成薄膜器件的基本上平面的层的集成堆叠，使得该器件由此形成堆叠结构。每个薄膜器件包括形成矩阵可寻址存储器的一个或多个存储区域，以及形成用于控制，驱动和寻址一个或多个存储器中的存储器单元的电子薄膜电路的附加电路区域。每个存储器件具有与装置中的每个其它薄膜器件的接口，所述接口通过通信和信号线实现，以及用于通过薄膜器件中的专用接口区垂直延伸的处理的支持电路。

9. 发明申请

US20080151609A1 Method for operating a data storage apparatus employing passive matrix addressing 失效
标题翻译：用于操作采用无源矩阵寻址的数据存储装置的方法
公开(公告)号：US20080151609A1
公开(公告)日：2008-06-26
申请号：US12010067
申请日：2008-01-18
申请人： Per Hamberg , Christer Karlsson , Per-Erik Nordal , Nicklas Ojakangas , Johan Carlsson , Hans Gude Gudesen
发明人： Per Hamberg , Christer Karlsson , Per-Erik Nordal , Nicklas Ojakangas , Johan Carlsson , Hans Gude Gudesen
IPC分类号： G11C11/00 , G11C8/00
CPC分类号： G11C11/22 , G06F12/0238 , G06F2212/1036 , G06F2212/7211 , G11C8/12 , G11C2013/0083
摘要： In a method for obviating the effect of disturb voltages in a data storage apparatus employing passive matrix addressing, an application of electric potentials for an addressing operation is according to a voltage pulse protocol. The data storage cells of the apparatus are provided in two or more electrically separated segments each constituting non-overlapping physical address subspaces of the data storage apparatus physical address space. A number of data storage cells in each segment are preset to the same polarization by an active voltage pulse with a specific polarization. In a first addressing operation one or more data storage cells are read by applying an active pulse with the same polarization to each data storage cell and recording the output charge response. On basis thereof the output data in subsequent second addressing operation are copied onto preset data storage cells in another segment of the data storage apparatus, this segment being selected on the basis of its previous addressing history.
摘要翻译：在采用无源矩阵寻址的数据存储装置中避免干扰电压的影响的方法中，用于寻址操作的电位的应用是根据电压脉冲协议。设备的数据存储单元被提供在两个或更多个电隔离的段中，每个段构成数据存储设备物理地址空间的非重叠物理地址子空间。每个段中的多个数据存储单元通过具有特定极化的有源电压脉冲预设为相同的极化。在第一寻址操作中，通过向每个数据存储单元施加具有相同极化的有源脉冲并记录输出电荷响应来读取一个或多个数据存储单元。基于此，随后的第二寻址操作中的输出数据被复制到数据存储装置的另一段中的预定数据存储单元上，该段根据其先前的寻址历史进行选择。

10. 发明授权

US06762950B2 Folded memory layers 失效
标题翻译：折叠内存层
公开(公告)号：US06762950B2
公开(公告)日：2004-07-13
申请号：US10306229
申请日：2002-11-29
申请人： Hans Gude Gudesen , Per-Erik Nordal
发明人： Hans Gude Gudesen , Per-Erik Nordal
IPC分类号： G11C1122
CPC分类号： G11C11/22 , H01L27/10
摘要： A ferroelectric or electret volumetric memory device with a memory material provided in sandwich between first and second electrode layers with stripe-like electrodes forming word lines and bit lines of a matrix-addressable memory array, memory cells are defined in volumes of memeory material in between two crossing word lines and bit lines and a plurality of memory arrays are provided in a stacked arrangement. A stack of memory arrays is formed by tow or more ribbon-like structures, which are folded and/or braided into each other. Each ribbon-like structure includes a flexible substrate of non-conducting material and the electrode layers respectively provided on each surface of the substrate and including the parallel strip-like electrodes extending along the ribbon-like structure. A layer of memory material covers one of the electrode layers whereby each memory array of the stack is formed by overlapping portions of a pair of adjacent ribbon-like structures and crossing in substantially orthogonal relationship.
摘要翻译：具有记忆材料的铁电体或驻极体体积存储装置，其具有在形成矩阵可寻址存储器阵列的字线和位线的带条形电极的第一和第二电极层之间夹层提供的存储器单元，以堆叠的方式设置两个交叉字线和位线以及多个存储器阵列。一叠存储器阵列由丝束状或更多的带状结构形成，这些结构被折叠和/或编织成彼此。每个带状结构包括非导电材料的柔性基板和分别设置在基板的每个表面上并包括沿着带状结构延伸的平行条状电极的电极层。存储器材料层覆盖电极层之一，由此堆叠的每个存储器阵列由一对相邻的带状结构的重叠部分形成，并以基本正交的关系交叉。

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