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1. 发明授权

US5712808A Digital signal processing 失效
公开(公告)号：US5712808A
公开(公告)日：1998-01-27
申请号：US510167
申请日：1995-08-02
申请人： Peter Charles Eastty , Tetsuya Konishi , Conrad Charles Cooke
发明人： Peter Charles Eastty , Tetsuya Konishi , Conrad Charles Cooke
IPC分类号： G10L19/00 , G10H1/12 , H03H17/02 , H03H17/04 , G06F17/10
CPC分类号： G10H1/125 , H03H17/0294 , H03H17/04 , G10H2250/101 , G10H2250/121 , G10H2250/545
摘要： Digital signal processing (e.g. filtering) apparatus comprises pipelined digital signal processing means for generating each output sample of an output digital signal from input samples of an input digital signal by combining the input samples with a plurality of subsets of a set of filter coefficients associated with that output sample during a respective plurality of sample periods of the input digital signal; and coefficient generating means for supplying sets of filter coefficients to the signal processing means in response to the current state of a filter control signal. The coefficient generating means is operable to supply the plurality of subsets of each set of filter coefficients to the signal processing means during the respective plurality of sample periods of the input digital signal.

2. 发明授权

US5877971A Digital signal processing 失效
标题翻译：数字信号处理
公开(公告)号：US5877971A
公开(公告)日：1999-03-02
申请号：US947289
申请日：1997-10-07
申请人： Peter Charles Eastty , Tetsuya Konishi , Conrad Charles Cooke
发明人： Peter Charles Eastty , Tetsuya Konishi , Conrad Charles Cooke
IPC分类号： G10L19/00 , G10H1/12 , H03H17/02 , H03H17/04 , G06F17/10
CPC分类号： G10H1/125 , H03H17/0294 , H03H17/04 , G10H2250/101 , G10H2250/121 , G10H2250/545
摘要： Digital signal processing (e.g. filtering) apparatus comprises pipelined digital signal processing means for generating each output sample of an output digital signal from input samples of an input digital signal by combining the input samples with a plurality of subsets of a set of filter coefficients associated with that output sample during a respective plurality of sample periods of the input digital signal; and coefficient generating means for supplying sets of filter coefficients to the signal processing means in response to the current state of a filter control signal. The coefficient generating means is operable to supply the plurality of subsets of each set of filter coefficients to the signal processing means during the respective plurality of sample periods of the input digital signal.
摘要翻译：数字信号处理（例如滤波）装置包括流水线数字信号处理装置，用于通过将输入样本与一组与滤波系数相关联的多个子集组合而从输入数字信号的输入样本产生输出数字信号的每个输出样本在输入数字信号的相应多个采样周期期间该输出采样; 以及系数产生装置，用于响应于滤波器控制信号的当前状态向信号处理装置提供滤波器系数集合。系数产生装置可操作以在输入数字信号的相应多个采样周期期间将每组滤波器系数的多个子集提供给信号处理装置。

3. 发明授权

US5898878A Data processing system having capability to interpolate processing coefficients 失效
标题翻译：数据处理系统具有内插处理系数的能力
公开(公告)号：US5898878A
公开(公告)日：1999-04-27
申请号：US48133
申请日：1998-03-25
申请人： Rodney Hugh Densham , William Kentish , Peter Charles Eastty , Conrad Charles Cooke
发明人： Rodney Hugh Densham , William Kentish , Peter Charles Eastty , Conrad Charles Cooke
IPC分类号： G06F15/16 , G06F9/48 , G06F11/10 , G06F11/30 , G06F11/32 , G06F15/177 , G06F17/17 , G06F7/00 , G06F9/46
CPC分类号： G06F11/3072 , G06F11/10 , G06F17/17 , G06F11/327 , G06F2201/86 , G06F2201/88
摘要： A method and apparatus is provided for generating an interrupt signal in a data processing system, the interrupt signal being supplied to a control processor of the system to indicate the occurrence of any of a plurality of predetermined events in the system. The method and apparatus operate by: writing data to at least one memory location of a plurality of pairs of memory locations A,B of the system in dependence upon the event to be indicated, the pairs of memory locations A,B being predefined in the system for respective ones of the events; reading data from the pairs of memory locations A,B; processing the data read from each pair of memory locations A,B to generate interrupt data indicative of whether the associated event has occurred, and if so transmitting an interrupt signal to the control processor; and writing the interrupt data corresponding to the events to respective third memory locations C, the third memory locations C being predefined in the control processor for the events. On receipt of an interrupt signal, the control processor reads the interrupt data in the third memory locations C to determine the event indicated by the interrupt signal.
摘要翻译：提供了一种用于在数据处理系统中产生中断信号的方法和装置，所述中断信号被提供给系统的控制处理器，以指示系统中多个预定事件中的任何一个发生。该方法和装置通过以下方式操作：根据要指示的事件将数据写入系统的多对存储器位置A，B的至少一个存储器位置，存储器位置A，B在系统为各自的事件; 从存储单元对A，B中读取数据; 处理从每对存储器位置A，B读取的数据，以产生指示相关联的事件是否已经发生的中断数据，并且如果发送中断信号到控制处理器; 并将与事件相对应的中断数据写入相应的第三存储器位置C，在控制处理器中为事件预定义第三存储单元C. 在接收到中断信号时，控制处理器读取第三存储器位置C中的中断数据，以确定由中断信号指示的事件。

4. 发明授权

US5740449A Method and apparatus for managing interrupts in a data processing system 失效
标题翻译：用于管理数据处理系统中的中断的方法和装置
公开(公告)号：US5740449A
公开(公告)日：1998-04-14
申请号：US598537
申请日：1996-02-08
申请人： Rodney Hugh Densham , William Kentish , Peter Charles Eastty , Conrad Charles Cooke
发明人： Rodney Hugh Densham , William Kentish , Peter Charles Eastty , Conrad Charles Cooke
IPC分类号： G06F15/16 , G06F9/48 , G06F11/10 , G06F11/30 , G06F11/32 , G06F15/177 , G06F17/17 , G06F9/46 , G06F11/00
CPC分类号： G06F11/3072 , G06F11/10 , G06F17/17 , G06F11/327 , G06F2201/86 , G06F2201/88
摘要： A method and apparatus is provided for generating an interrupt signal in a data processing system, the interrupt signal being supplied to a control processor of the system to indicate the occurrence of any of a plurality of predetermined events in the system. The method and apparatus operate by: writing data to at least one memory location of a plurality of pairs of memory locations A, B of the system in dependence upon the event to be indicated, the pairs of memory locations A, B being predefined in the system for respective ones of the events; reading data from the pairs of memory locations A, B; processing the data read from each pair of memory locations A, B to generate interrupt data indicative of whether the associated event has occurred, and if so transmitting an interrupt signal to the control processor; and writing the interrupt data corresponding to the events to respective third memory locations C, the third memory locations C being predefined in the control processor. On receipt of an interrupt signal, the control processor reads the interrupt data in the third memory locations C to determine the event indicated by the interrupt signal.
摘要翻译：提供了一种用于在数据处理系统中产生中断信号的方法和装置，所述中断信号被提供给系统的控制处理器，以指示系统中多个预定事件中的任何一个发生。该方法和装置通过以下方式操作：根据要指示的事件将数据写入系统的多对存储器位置A，B的至少一个存储器位置，存储器位置A，B在系统为各自的事件; 从存储单元对A，B中读取数据; 处理从每对存储器位置A，B读取的数据，以产生指示相关联的事件是否已经发生的中断数据，并且如果发送中断信号到控制处理器; 并将对应于事件的中断数据写入相应的第三存储器位置C，在控制处理器中预定义第三存储单元C. 在接收到中断信号时，控制处理器读取第三存储器位置C中的中断数据，以确定由中断信号指示的事件。

5. 发明授权

US5881077A Data processing system 失效
标题翻译：数据处理系统
公开(公告)号：US5881077A
公开(公告)日：1999-03-09
申请号：US845559
申请日：1997-04-24
申请人： Rodney Hugh Densham , William Kentish , Peter Charles Eastty , Conrad Charles Cooke
发明人： Rodney Hugh Densham , William Kentish , Peter Charles Eastty , Conrad Charles Cooke
IPC分类号： G06F15/16 , G06F9/48 , G06F11/10 , G06F11/30 , G06F11/32 , G06F15/177 , G06F17/17 , G06F11/00
CPC分类号： G06F11/3072 , G06F11/10 , G06F17/17 , G06F11/327 , G06F2201/86 , G06F2201/88
摘要： A method and apparatus is provided for generating an interrupt signal in a data processing system, the interrupt signal being supplied to a control processor of the system to indicate the occurrence of any of a plurality of predetermined events in the system. The method and apparatus operate by: writing data to at least one memory location of a plurality of pairs of memory locations A,B of the system in dependence upon the event to be indicated, the pairs of memory locations A,B being predefined in the system for respective ones of the events; reading data from the pairs of memory locations A,B; processing the data read from each pair of memory locations A,B to generate interrupt data indicative of whether the associated event has occurred, and if so transmitting an interrupt signal to the control processor; and writing the interrupt data corresponding to the events to respective third memory locations C, the third memory locations C being predefined in the control processor for the said events. On receipt of an interrupt signal, the control processor reads the interrupt data in the third memory locations C to determine the event indicated by the interrupt signal.
摘要翻译：提供了一种用于在数据处理系统中产生中断信号的方法和装置，所述中断信号被提供给系统的控制处理器，以指示系统中多个预定事件中的任何一个发生。该方法和装置通过以下方式操作：根据要指示的事件将数据写入系统的多对存储器位置A，B的至少一个存储器位置，存储器位置A，B在系统为各自的事件; 从存储单元对A，B中读取数据; 处理从每对存储器位置A，B读取的数据，以产生指示相关联的事件是否已经发生的中断数据，并且如果发送中断信号到控制处理器; 并将对应于事件的中断数据写入相应的第三存储器位置C，在控制处理器中为所述事件预定义第三存储单元C. 在接收到中断信号时，控制处理器读取第三存储器位置C中的中断数据，以确定由中断信号指示的事件。

6. 发明授权

US5802385A Array processing system with each processor including router and which selectively delays input/output of individual processors in response delay instructions 失效
标题翻译：阵列处理系统，每个处理器包括路由器，并且在响应延迟指令中选择性地延迟单个处理器的输入/输出
公开(公告)号：US5802385A
公开(公告)日：1998-09-01
申请号：US515837
申请日：1995-08-16
申请人： Rodney Hugh Densham , Peter Charles Eastty , Conrad Charles Cooke
发明人： Rodney Hugh Densham , Peter Charles Eastty , Conrad Charles Cooke
IPC分类号： G06F15/16 , G06F15/177 , G06F15/80 , H04H60/04 , G06F15/82
CPC分类号： H04H60/04
摘要： In one aspect, the invention provides parallel processing apparatus comprising an array of data processors 4. arranged to operate synchronously, and a plurality of data buses. Each data processor 4 has first and second I/O means 16H, 16V for transfer of data between the processor 4 and respective data buses H,V a plurality of processors 4 being connected to each of the data buses H,V and each processor 4 being connected, via said I/O means 16H, 16V, to a different pair of data buses H,V. Each processor 4 includes selectively operable routing means 32H, 32V for interconnecting the first and second I/O means 16H, 16V to transfer data between the buses H,V connected thereto.
摘要翻译：一方面，本发明提供并行处理装置，其包括布置成同步操作的数据处理器阵列4和多个数据总线。每个数据处理器4具有用于在处理器4和相应的数据总线H，V之间传送数据的第一和第二I / O装置16H，16V，多个处理器4连接到每个数据总线H，V和每个处理器4 通过所述I / O装置16H，16V连接到不同的一对数据总线H，V。每个处理器4包括用于互连第一和第二I / O装置16H，16V的选择性可操作的路由装置32H，32V，以在连接到其之间的总线H，V之间传送数据。

7. 发明授权

US06327631B1 Signal processing apparatus 失效
标题翻译：信号处理装置
公开(公告)号：US06327631B1
公开(公告)日：2001-12-04
申请号：US08654217
申请日：1996-05-28
申请人： Peter Charles Eastty , William Edmund Cranstoun Kentish , Christopher Michael McCulloch
发明人： Peter Charles Eastty , William Edmund Cranstoun Kentish , Christopher Michael McCulloch
IPC分类号： G06F104
CPC分类号： H04H60/04
摘要： A processing apparatus includes a network of interconnected processors comprising a plurality of signal processors for digitally processing input signals in real time to generate output signals and one or more control processors, each control processor controlling the operation of a plurality of signal processors. The processing apparatus automatically schedules control tasks in a plurality of time slices, where more than one control processor is provided for coordination between control processors, a wired-OR configuration connection can be provided to synchronise the beginning and/or end of the time slices. A control processor can change an address field of microcode instructions of a signal processor for implementing a multiplexer function. A control delay list can be provided for scheduling control task delays. Control tasks can be allocated to more than one control processor, each control processor then communicating to the other control processors if it completes the task so that the other control processors may abandon further processing of the task. The invention finds particular application to an audio mixing console.
摘要翻译：处理装置包括互连处理器的网络，其包括多个用于实时数字处理输入信号的信号处理器以产生输出信号和一个或多个控制处理器，每个控制处理器控制多个信号处理器的操作。处理装置在多个时间片段中自动调度控制任务，其中提供多于一个控制处理器用于控制处理器之间的协调，可以提供有线配置连接以同步时间片段的开始和/或结束。控制处理器可以改变用于实现复用器功能的信号处理器的微码指令的地址字段。可以提供控制延迟列表用于调度控制任务延迟。控制任务可以被分配给多个控制处理器，然后每个控制处理器如果完成任务则与其他控制处理器进行通信，以便其他控制处理器可以放弃任务的进一步处理。本发明特别适用于音频混合控制台。

8. 发明授权

US6021204A Analysis of audio signals 失效
标题翻译：音频信号分析
公开(公告)号：US6021204A
公开(公告)日：2000-02-01
申请号：US947260
申请日：1997-10-08
申请人： Peter Charles Eastty
发明人： Peter Charles Eastty
IPC分类号： G10L11/00 , G01R13/40 , G01R23/16 , H04S7/00 , H04H5/00
CPC分类号： H04S7/40 , G01R13/408 , G01R23/16
摘要： Apparatus for analyzing audio signals from a stereo pair of audio channels, comprises: means for detecting the magnitudes of the audio signals of the two audio channels; first detector for detecting a degree of phase correlation between the audio signals of the two audio channels; and second detector for generating an indicator color for display in respect of the audio channels at a time of test, the indicator color having a hue, intensity and/or saturation dependent on at least the relative magnitudes of and the degree of phase correlation between the audio signals of the two audio channels at the time of test.
摘要翻译：用于从立体声音频通道对分析音频信号的装置包括：用于检测两个音频通道的音频信号的大小的装置; 第一检测器，用于检测两个音频通道的音频信号之间的相位相关程度; 以及第二检测器，用于在测试时产生关于音频通道的显示的指示器颜色，所述指示符颜色具有至少取决于所述音频通道的相对幅度和相位相关程度之间的色相，强度和/或饱和度在测试时两个音频通道的音频信号。

9. 发明授权

US6002353A One-bit digital signal processing 失效
标题翻译：一位数字信号处理
公开(公告)号：US6002353A
公开(公告)日：1999-12-14
申请号：US978724
申请日：1997-11-26
申请人： Peter Charles Eastty , Christopher Sleight , Peter Damien Thorpe
发明人： Peter Charles Eastty , Christopher Sleight , Peter Damien Thorpe
IPC分类号： H03M3/02 , H03K5/08 , H04B1/18 , H04L25/02 , H04L25/06
CPC分类号： H04L25/0292 , H03K5/08 , H04L25/06 , H04L25/0278
摘要： An input stage for receiving an input signal having a signal level varying to represent successive states of a one-bit digital signal, comprises: a thresholder for detecting whether the input signal level is above or below a threshold signal level; in which: the input of the thresholder is biased with a bias signal varying between a signal level above the threshold signal level and a signal level below the threshold signal level; and the amplitude of the alternating component of the bias signal is lower than the amplitude of the alternating component of the input signal.
摘要翻译：一种用于接收信号电平变化以表示一比特数字信号的连续状态的输入信号的输入级，包括：用于检测输入信号电平是高于还是低于阈值信号电平的阈值器; 其中：阈值器的输入被偏置在偏置信号之间，该偏置信号在高于阈值信号电平的信号电平和低于阈值信号电平的信号电平之间变化; 并且偏置信号的交变分量的幅度低于输入信号的交变分量的振幅。

10. 发明授权

US5923767A Digital audio processing 失效
标题翻译：数字音频处理
公开(公告)号：US5923767A
公开(公告)日：1999-07-13
申请号：US801355
申请日：1997-02-19
申请人： Paul Anthony Frindle , Peter Charles Eastty
发明人： Paul Anthony Frindle , Peter Charles Eastty
IPC分类号： G10L21/02 , H03G7/00 , H03M7/50
CPC分类号： H03G7/007
摘要： Digital audio processing apparatus comprises: device for detecting the magnitude of an input digital audio signal; and a variable gain element for applying a gain to the input digital audio signal dependent on the detected magnitude of the input digital audio signal, in which:(i) the applied gain is linearly related to the envelope signal with a first predetermined slope, for detected magnitudes below a first threshold magnitude;(ii) the applied gain is linearly related to the envelope signal with a second predetermined slope, for detected magnitudes above a second threshold magnitude higher than the first threshold magnitude; and(iii) for detected magnitudes from the first threshold magnitude to the second threshold magnitude, the slope of the applied gain with respect to detected magnitude varies monotonically from the first predetermined slope to the second predetermined slope.
摘要翻译：数字音频处理装置包括：用于检测输入数字音频信号的大小的装置; 以及可变增益元件，用于根据检测到的输入数字音频信号的幅度将增益应用于输入数字音频信号，其中：（i）所施加的增益与具有第一预定斜率的包络信号线性相关，用于检测到的幅度低于第一阈值幅度; （ii）所施加的增益与具有第二预定斜率的包络信号线性相关，用于高于高于第一阈值幅度的第二阈值幅度的检测幅度; 和（iii）对于从第一阈值幅度到第二阈值幅度的检测幅度，施加的增益相对于检测到的幅度的斜率从第一预定斜率到第二预定斜率单调变化。

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