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1. 发明授权

US07480882B1 Measuring and predicting VLSI chip reliability and failure 失效
标题翻译：测量和预测VLSI芯片的可靠性和故障
公开(公告)号：US07480882B1
公开(公告)日：2009-01-20
申请号：US12049344
申请日：2008-03-16
申请人： Peilin Song , David Heidel , Franco Motika , Franco Stellari
发明人： Peilin Song , David Heidel , Franco Motika , Franco Stellari
IPC分类号： G06F17/50 , G06F19/00 , G06F11/27 , G01R31/3187 , G01R31/28
CPC分类号： G01R31/318536
摘要： This embodiment replaces the use of LBIST to get a pass or no-pass result. A selective signature feature is used to collect the top failing paths, by shmooing the chip over a cycle time. These paths can be stored on-chip or off-chip, for later use. Once the chip is running in the field for a certain time, the same procedure is performed to collect the top failing paths, and this is compared with the stored old paths. If the order of the top paths changes, it indicates that (for example) there is a path (not the slowest path before) that slows more than others, which could be potential reliability concern. Therefore, a potential reliability failure is identified in the field.
摘要翻译：该实施例取代了LBIST的使用以获得通过或不通过结果。选择性签名功能用于通过在一个周期时间内抖动芯片来收集顶部故障路径。这些路径可以片上或片外存储，供以后使用。一旦芯片在现场运行一段时间，执行相同的过程来收集最上面的故障路径，并将其与存储的旧路径进行比较。如果顶部路径的顺序发生变化，则表示（例如）有一个路径（不是最慢的路径）比其他路径慢，这可能是潜在的可靠性问题。因此，在现场确定潜在的可靠性故障。

2. 发明授权

US08193009B2 Apparatus and methods for packaging electronic devices for optical testing 失效
标题翻译：用于包装电子设备进行光学测试的装置和方法
公开(公告)号：US08193009B2
公开(公告)日：2012-06-05
申请号：US12534592
申请日：2009-08-03
申请人： Alberto Tosi , Franco Stellari , Peilin Song
发明人： Alberto Tosi , Franco Stellari , Peilin Song
IPC分类号： H01L21/66
CPC分类号： G01R31/311 , G01R1/0408 , H01L25/16 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2924/00011 , H01L2924/00014 , H01L2924/3011 , H01L2224/0401
摘要： Apparatus and methods are provided for packaging IC (integrated circuit) chips to enable both optical access to the back side of an IC chip and electrical access to the front side of the IC chip.
摘要翻译：提供了用于封装IC（集成电路）芯片的装置和方法，以使得能够对IC芯片的背侧进行光学接入和对IC芯片的前侧的电接入。

3. 发明申请

US20090286353A1 Apparatus and Methods for Packaging Electronic Devices for Optical Testing 失效
标题翻译：用于包装用于光学测试的电子设备的装置和方法
公开(公告)号：US20090286353A1
公开(公告)日：2009-11-19
申请号：US12534592
申请日：2009-08-03
申请人： Alberto Tosi , Franco Stellari , Peilin Song
发明人： Alberto Tosi , Franco Stellari , Peilin Song
IPC分类号： H01L21/52
CPC分类号： G01R31/311 , G01R1/0408 , H01L25/16 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2924/00011 , H01L2924/00014 , H01L2924/3011 , H01L2224/0401
摘要： Apparatus and methods are provided for packaging IC (integrated circuit) chips to enable both optical access to the back side of an IC chip and electrical access to the front side of the IC chip.
摘要翻译：提供了用于封装IC（集成电路）芯片的装置和方法，以使得能够对IC芯片的背侧进行光学接入和对IC芯片的前侧的电接入。

4. 发明申请

US20060220664A1 Optical trigger for PICA technique 失效
标题翻译： PICA技术的光触发器
公开(公告)号：US20060220664A1
公开(公告)日：2006-10-05
申请号：US11098850
申请日：2005-04-05
申请人： Franco Stellari , Peilin Song
发明人： Franco Stellari , Peilin Song
IPC分类号： G01R31/302
CPC分类号： G01R31/31709 , G01R31/311
摘要： Optical triggering system and method for synchronizing a test of an integrated circuit chip with its operation. An optical triggering system includes a testing mechanism, such as a PICA testing mechanism, for testing an integrated circuit chip. An optical trigger mechanism generates an optical trigger signal for synchronizing a test of the integrated circuit chip with its operation. The optical trigger mechanism provides an optical trigger signal having reduced jitter and a higher frequency rate than an electrical trigger signal resulting in a more accurate test of the integrated circuit chip.
摘要翻译：用于使集成电路芯片的测试与其操作同步的光触发系统和方法。光触发系统包括用于测试集成电路芯片的诸如PICA测试机构的测试机构。光学触发机构产生用于使集成电路芯片的测试与其操作同步的光学触发信号。光学触发机构提供具有比电触发信号更少的抖动和更高频率的光学触发信号，导致集成电路芯片的更准确的测试。

5. 发明授权

US09581642B2 Method and system for quickly identifying circuit components in an emission image 有权
标题翻译：用于快速识别发射图像中电路元件的方法和系统
公开(公告)号：US09581642B2
公开(公告)日：2017-02-28
申请号：US12778544
申请日：2010-05-12
申请人： Peilin Song , Franco Stellari
发明人： Peilin Song , Franco Stellari
IPC分类号： G06T7/00 , G01R31/311
CPC分类号： G01R31/311 , G01R31/2853 , G06T7/001 , G06T7/11 , G06T2207/10056 , G06T2207/30148
摘要： A system and method for localization and resolvability of an integrated circuit includes selecting one or more electrical stimuli to be applied to a device under test such that the electrical stimuli are chosen to provide a baseline image and a distinguishing image effect as a result of the chosen stimuli when applied to the device under test. The one or more electrical stimuli are applied to the device under test. Emissions from the device under test are measured to provide a measurement data set from the one or more electrical stimuli using one or more measurement tools for collecting the baseline image and the distinguishing image effect. The measurement data set is analyzed to localize and evaluate circuit structures by comparing the baseline image and the distinguishing image effect.
摘要翻译：用于集成电路的定位和可解析性的系统和方法包括选择要施加到被测器件的一个或多个电刺激，使得选择电刺激以提供基线图像和作为所选择的结果的结果的区别图像效果当被施加到被测设备时刺激。一个或多个电刺激被施加到被测设备。测量来自被测器件的发射，以使用一个或多个测量工具从一个或多个电刺激提供测量数据集，用于收集基线图像和区分图像效果。分析测量数据集，通过比较基线图像和区分图像效果来定位和评估电路结构。

6. 发明授权

US09557369B2 Integrated time dependent dielectric breakdown reliability testing 有权
标题翻译：集成时间依赖介质击穿可靠性测试
公开(公告)号：US09557369B2
公开(公告)日：2017-01-31
申请号：US13530782
申请日：2012-06-22
申请人： Jifeng Chen , Dirk Pfeiffer , Thomas M. Shaw , Peilin Song , Franco Stellari
发明人： Jifeng Chen , Dirk Pfeiffer , Thomas M. Shaw , Peilin Song , Franco Stellari
IPC分类号： G01R31/28 , G01R31/311
CPC分类号： G01R31/2855 , G01R31/281 , G01R31/2817 , G01R31/2858 , G01R31/2879 , G01R31/311
摘要： Methods for reliability testing include applying a stress voltage to a device under test (DUT); measuring a leakage current across the DUT; triggering measurement of optical emissions from the DUT based on the timing of the measurement of the leakage current; and correlating measurements of the leakage current with measurements of the optical emissions to determine a time and location of a defect occurrence within the DUT by locating instances of increased noise in the leakage current that correspond in time with instances of increased optical emissions.
摘要翻译：可靠性测试方法包括对被测设备（DUT）施加应力电压; 测量穿过DUT的漏电流; 基于泄漏电流测量的定时，触发DUT测量光发射; 并且将泄漏电流的测量与光发射的测量值相关联，以通过将泄漏电流中增加的噪声的实例定位在与增加的光发射的情况相对应的时间内来确定DUT内的缺陷发生的时间和位置。

7. 发明授权

US09448277B2 Integrated time dependent dielectric breakdown reliability testing 有权
标题翻译：集成时间依赖介质击穿可靠性测试
公开(公告)号：US09448277B2
公开(公告)日：2016-09-20
申请号：US13544080
申请日：2012-07-09
申请人： Jifeng Chen , Dirk Pfeiffer , Thomas M. Shaw , Peilin Song , Franco Stellari
发明人： Jifeng Chen , Dirk Pfeiffer , Thomas M. Shaw , Peilin Song , Franco Stellari
IPC分类号： G01R31/28 , G01R31/311
CPC分类号： G01R31/2855 , G01R31/281 , G01R31/2817 , G01R31/2858 , G01R31/2879 , G01R31/311
摘要： Systems for reliability testing include a picometer configured to measure a leakage current across a device under test (DUT); a camera configured to measure optical emissions from the DUT based on a timing of the measurement of the leakage current; and a test system configured to apply a stress voltage to the DUT and to correlate the leakage current with the optical emissions using a processor to determine a time and location of a defect occurrence within the DUT by locating instances of increased noise in the leakage current that correspond in time with instances of increased optical emissions.
摘要翻译：用于可靠性测试的系统包括配置成测量被测器件（DUT）上的漏电流的波长计; 配置为基于所述泄漏电流的测量的定时来测量来自所述DUT的光发射的照相机; 以及被配置为向DUT施加应力电压并且使用处理器将泄漏电流与光发射相关联的测试系统，以通过定位泄漏电流中增加的噪声的实例来确定DUT内的缺陷发生的时间和位置，在时间上对应于增加的光发射的情况。

8. 发明授权

US08635582B2 Navigating analytical tools using layout software 有权
标题翻译：使用布局软件浏览分析工具
公开(公告)号：US08635582B2
公开(公告)日：2014-01-21
申请号：US13611776
申请日：2012-09-12
申请人： Franco Stellari , Peilin Song
发明人： Franco Stellari , Peilin Song
IPC分类号： G06F17/50 , G06F9/44 , G09G5/00
CPC分类号： G06F17/5081 , G06F17/5022 , G06F17/5036
摘要： A background process installs a system hook for message interception of integrated circuit chip layout display software. A call message is intercepted through the system hook, and current layout coordinates are read from the integrated circuit chip layout display software. A representation of the current layout coordinates is entered into tool control software configured to control a physical tool for analyzing integrated circuits, and the physical tool is controlled with the tool control software. In an “inverse” approach, a background process is used to install at least one system hook for message interception of tool control software configured to control a physical tool for analyzing integrated circuits, and a call message is intercepted through the system hook. Current coordinates are read from the tool control software. A representation of the current coordinates is entered into integrated circuit chip layout display software, and at least a portion of an integrated circuit layout is displayed.
摘要翻译：背景过程安装了用于消息拦截集成电路芯片布局显示软件的系统挂钩。通过系统挂钩截取通话消息，从集成电路芯片布局显示软件中读取当前布局坐标。将当前布局坐标的表示输入到被配置为控制用于分析集成电路的物理工具的工具控制软件中，并且物理工具由工具控制软件控制。在“反向”方法中，使用后台进程来安装至少一个用于消息拦截的系统钩子，用于控制用于分析集成电路的物理工具的工具控制软件，并且通过系统钩子拦截呼叫消息。从刀具控制软件读取当前坐标。将当前坐标的表示输入到集成电路芯片布局显示软件中，并且显示集成电路布局的至少一部分。

9. 发明申请

US20130345997A1 INTEGRATED TIME DEPENDENT DIELECTRIC BREAKDOWN RELIABILITY TESTING 有权
标题翻译：集成时间依赖电介质断开可靠性测试
公开(公告)号：US20130345997A1
公开(公告)日：2013-12-26
申请号：US13530782
申请日：2012-06-22
申请人： JIFENG CHEN , Dirk Pfeiffer , Thomas M. Shaw , Peilin Song , Franco Stellari
发明人： JIFENG CHEN , Dirk Pfeiffer , Thomas M. Shaw , Peilin Song , Franco Stellari
IPC分类号： G01R31/12 , G06F19/00
CPC分类号： G01R31/2855 , G01R31/281 , G01R31/2817 , G01R31/2858 , G01R31/2879 , G01R31/311
摘要： Methods for reliability testing include applying a stress voltage to a device under test (DUT); measuring a leakage current across the DUT; triggering measurement of optical emissions from the DUT based on the timing of the measurement of the leakage current; and correlating measurements of the leakage current with measurements of the optical emissions to determine a time and location of a defect occurrence within the DUT by locating instances of increased noise in the leakage current that correspond in time with instances of increased optical emissions.
摘要翻译：可靠性测试方法包括对被测设备（DUT）施加应力电压; 测量穿过DUT的漏电流; 基于泄漏电流测量的定时，触发DUT测量光发射; 并且将泄漏电流的测量与光发射的测量值相关联，以通过将泄漏电流中增加的噪声的实例定位在与增加的光发射的情况相对应的时间内来确定DUT内的缺陷发生的时间和位置。

10. 发明授权

US08412993B2 Self-adjusting critical path timing of multi-core VLSI chip 有权
标题翻译：多核VLSI芯片的自调节关键路径时序
公开(公告)号：US08412993B2
公开(公告)日：2013-04-02
申请号：US12788987
申请日：2010-05-27
申请人： Peilin Song , Franco Stellari
发明人： Peilin Song , Franco Stellari
IPC分类号： G01R31/28
CPC分类号： G01R31/31726 , G01R31/3187 , G06F1/10 , G06F11/2242
摘要： A method for adjusting timing of multiple cores within an integrated circuit includes selecting a reference core and a target core from among a plurality of cores of an integrated circuit. Self-test circuitry of the integrated circuit is used to generate a response signature for each of the reference core and the target core. The response signature of the reference core is compared with the response signature of the target core. A local clock buffer of the target core is adjusted until the response signature of the target core matches the response signature of the reference core.
摘要翻译：一种用于调整集成电路内的多个核心的定时的方法包括从集成电路的多个核心中选择参考核心和目标核心。集成电路的自检电路用于为每个参考核心和目标核心产生响应特征。将参考核心的响应签名与目标核心的响应签名进行比较。调整目标核心的本地时钟缓冲器，直到目标核心的响应签名与参考核心的响应签名相匹配。

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