专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090145877A1 METHOD FOR CONTROLLING ADI-AEI CD DIFFERENCE RATIO OF OPENINGS HAVING DIFFERENT SIZES 有权
标题翻译：用于控制具有不同尺寸的开口的ADI-AEI CD差异比例的方法
公开(公告)号：US20090145877A1
公开(公告)日：2009-06-11
申请号：US12371809
申请日：2009-02-16
申请人： Feng-Yih Chang , Pei-Yu Chou , Jiunn-Hsiung Liao , Chih-Wen Feng , Ying-Chih Lin
发明人： Feng-Yih Chang , Pei-Yu Chou , Jiunn-Hsiung Liao , Chih-Wen Feng , Ying-Chih Lin
IPC分类号： B44C1/22
CPC分类号： H01L21/76804 , H01L21/31144 , H01L21/76895
摘要： A method for controlling an ADI-AEI CD difference ratio of openings having different sizes is described. The openings are formed through a silicon-containing material layer, an etching resistive layer and a target material layer in turn. Before the opening etching steps, at least one of the opening patterns in the photoresist mask is altered in size through photoresist trimming or deposition of a substantially conformal polymer layer. A first etching step forming thicker polymer on the sidewall of the wider opening pattern is performed to form a patterned Si-containing material layer. A second etching step is performed to remove exposed portions of the etching resistive layer and the target material layer. At least one parameter among the parameters of the photoresist trimming or polymer layer deposition step and the etching parameters of the first etching step is controlled to obtain a predetermined ADI-AEI CD difference ratio.
摘要翻译：描述了用于控制具有不同尺寸的开口的ADI-AEI CD差异比率的方法。开口依次形成为含硅材料层，蚀刻电阻层和靶材料层。在开口蚀刻步骤之前，光致抗蚀剂掩模中的至少一个开口图案的尺寸通过基本上保形的聚合物层的光致抗蚀剂修饰或沉积而改变。执行在更宽的开口图案的侧壁上形成较厚聚合物的第一蚀刻步骤以形成图案化的含Si材料层。执行第二蚀刻步骤以去除蚀刻电阻层和目标材料层的暴露部分。控制光致抗蚀剂修整或聚合物层沉积步骤的参数中的至少一个参数和第一蚀刻步骤的蚀刻参数以获得预定的ADI-AEI CD差异比。

2. 发明授权

US08293639B2 Method for controlling ADI-AEI CD difference ratio of openings having different sizes 有权
标题翻译：用于控制具有不同尺寸的开口的ADI-AEI CD差异比率的方法
公开(公告)号：US08293639B2
公开(公告)日：2012-10-23
申请号：US12371809
申请日：2009-02-16
申请人： Feng-Yih Chang , Pei-Yu Chou , Jiunn-Hsiung Liao , Chih-Wen Feng , Ying-Chih Lin
发明人： Feng-Yih Chang , Pei-Yu Chou , Jiunn-Hsiung Liao , Chih-Wen Feng , Ying-Chih Lin
IPC分类号： H01L21/4763
CPC分类号： H01L21/76804 , H01L21/31144 , H01L21/76895
摘要： A method for controlling an ADI-AEI CD difference ratio of openings having different sizes is described. The openings are formed through a silicon-containing material layer, an etching resistive layer and a target material layer in turn. Before the opening etching steps, at least one of the opening patterns in the photoresist mask is altered in size through photoresist trimming or deposition of a substantially conformal polymer layer. A first etching step forming thicker polymer on the sidewall of the wider opening pattern is performed to form a patterned Si-containing material layer. A second etching step is performed to remove exposed portions of the etching resistive layer and the target material layer. At least one parameter among the parameters of the photoresist trimming or polymer layer deposition step and the etching parameters of the first etching step is controlled to obtain a predetermined ADI-AEI CD difference ratio.
摘要翻译：描述了用于控制具有不同尺寸的开口的ADI-AEI CD差异比率的方法。开口依次形成为含硅材料层，蚀刻电阻层和靶材料层。在开口蚀刻步骤之前，光致抗蚀剂掩模中的至少一个开口图案的尺寸通过基本上保形的聚合物层的光致抗蚀剂修饰或沉积而改变。执行在更宽的开口图案的侧壁上形成较厚聚合物的第一蚀刻步骤以形成图案化的含Si材料层。执行第二蚀刻步骤以去除蚀刻电阻层和目标材料层的暴露部分。控制光致抗蚀剂修整或聚合物层沉积步骤的参数中的至少一个参数和第一蚀刻步骤的蚀刻参数以获得预定的ADI-AEI CD差异比。

3. 发明授权

US08236702B2 Method of fabricating openings and contact holes 有权
标题翻译：制造开口和接触孔的方法
公开(公告)号：US08236702B2
公开(公告)日：2012-08-07
申请号：US12042340
申请日：2008-03-05
申请人： Feng-Yi Chang , Pei-Yu Chou , Jiunn-Hsiung Liao , Chih-Wen Feng , Ying-Chih Lin , Po-Chao Tsao
发明人： Feng-Yi Chang , Pei-Yu Chou , Jiunn-Hsiung Liao , Chih-Wen Feng , Ying-Chih Lin , Po-Chao Tsao
IPC分类号： H01L21/302
CPC分类号： H01L21/76802 , H01L21/76831 , H01L21/76897
摘要： A semiconductor substrate having an etch stop layer and at least a dielectric layer disposed from bottom to top is provided. The dielectric layer and the etching stop layer is then patterned to form a plurality of openings exposing the semiconductor substrate. A dielectric thin film is subsequently formed to cover the dielectric layer, the sidewalls of the openings, and the semiconductor substrate. The dielectric thin film disposed on the dielectric layer and the semiconductor substrate is then removed while the dielectric thin film disposed on the sidewalls remains.
摘要翻译：提供具有蚀刻停止层和至少从底部到顶部设置的电介质层的半导体衬底。然后对电介质层和蚀刻停止层进行图案化以形成暴露半导体衬底的多个开口。随后形成介电薄膜以覆盖电介质层，开口的侧壁和半导体衬底。然后去除设置在电介质层和半导体衬底上的电介质薄膜，同时保留设置在侧壁上的电介质薄膜。

4. 发明申请

US20110223768A1 Method for Forming Contact Opening 审中-公开
标题翻译：形成接触开口的方法
公开(公告)号：US20110223768A1
公开(公告)日：2011-09-15
申请号：US12720671
申请日：2010-03-10
申请人： Ying-Chih LIN , Pei-Yu Chou , Jiunn-Hsiung Liao , Feng-Yi Chang , Chih-Wen Feng , Shang-Yuan Tsai
发明人： Ying-Chih LIN , Pei-Yu Chou , Jiunn-Hsiung Liao , Feng-Yi Chang , Chih-Wen Feng , Shang-Yuan Tsai
IPC分类号： H01L21/311
CPC分类号： H01L21/31116 , H01L21/02063 , H01L21/76802 , H01L21/76814
摘要： A method for forming contact openings is provided. First, a semiconductor device is formed on a substrate. Next, an etching stop layer, a first dielectric layer and a patterned photoresist layer are sequentially formed on the substrate. Next a portion of the first dielectric layer and a portion of the etching stop layer are removed to form an opening, wherein the portion of the first dielectric layer and the portion of the etching stop layer are not covered by the patterned photoresist layer. Next, the patterned photoresist layer is removed. Next, an over etching process is performed to remove the etching stop layer at a bottom of the opening and expose the semiconductor device in a nitrogen-free environment. The reactant gas of the over etching process includes fluorine-containing hydrocarbons, hydrogen gas and argon gas.
摘要翻译：提供了形成接触开口的方法。首先，在基板上形成半导体装置。接下来，在衬底上依次形成蚀刻停止层，第一电介质层和图案化光致抗蚀剂层。接下来，去除第一电介质层的一部分和蚀刻停止层的一部分以形成开口，其中第一介电层的一部分和蚀刻停止层的部分不被图案化的光致抗蚀剂层覆盖。接下来，去除图案化的光致抗蚀剂层。接下来，进行过蚀刻处理以去除开口底部的蚀刻停止层，并在无氮环境中暴露半导体器件。过蚀刻工艺的反应气体包括含氟烃，氢气和氩气。

5. 发明授权

US08592322B2 Method of fabricating openings 有权
标题翻译：开口方法
公开(公告)号：US08592322B2
公开(公告)日：2013-11-26
申请号：US13535370
申请日：2012-06-28
申请人： Feng-Yi Chang , Pei-Yu Chou , Jiunn-Hsiung Liao , Chih-Wen Feng , Ying-Chih Lin , Po-Chao Tsao
发明人： Feng-Yi Chang , Pei-Yu Chou , Jiunn-Hsiung Liao , Chih-Wen Feng , Ying-Chih Lin , Po-Chao Tsao
IPC分类号： H01L21/302
CPC分类号： H01L21/76802 , H01L21/76831 , H01L21/76897
摘要： A method of fabricating openings is disclosed. First, a semiconductor substrate having a salicide region thereon is provided. An etch stop layer and at least a dielectric layer are disposed on the semiconductor substrate from bottom to top. Second, the dielectric layer and the etching stop layer are patterned to form a plurality of openings in the dielectric layer and in the etching stop layer so that the openings expose the salicide region. Then, a dielectric thin film covering the dielectric layer, sidewalls of the openings and the salicide region is formed. Later, the dielectric thin film disposed on the dielectric layer and on the salicide region is removed.
摘要翻译：公开了一种制造开口的方法。首先，提供其上具有自对准硅化物区域的半导体衬底。蚀刻停止层和至少介电层从底部到顶部设置在半导体衬底上。其次，对电介质层和蚀刻停止层进行图案化以在电介质层和蚀刻停止层中形成多个开口，使得开口露出自对准区域。然后，形成覆盖电介质层的电介质薄膜，开口侧壁和自对准硅化物区域。然后，去除设置在电介质层和自对准硅化物区域上的电介质薄膜。

6. 发明授权

US08461649B2 Opening structure for semiconductor device 有权
标题翻译：半导体器件的开口结构
公开(公告)号：US08461649B2
公开(公告)日：2013-06-11
申请号：US13234159
申请日：2011-09-16
申请人： Po-Chao Tsao , Chang-Chi Huang , Ming-Tsung Chen , Feng-Yi Chang , Pei-Yu Chou , Jiunn-Hsiung Liao , Chih-Wen Feng , Ying-Chih Lin
发明人： Po-Chao Tsao , Chang-Chi Huang , Ming-Tsung Chen , Feng-Yi Chang , Pei-Yu Chou , Jiunn-Hsiung Liao , Chih-Wen Feng , Ying-Chih Lin
IPC分类号： H01L29/78
CPC分类号： H01L21/31144 , H01L21/76802 , H01L21/76831 , H01L23/485
摘要： An opening structure is disclosed. The opening structure includes: a semiconductor substrate; at least one dielectric layer disposed on the semiconductor substrate, wherein the dielectric layer has a plurality of openings exposing the semiconductor substrate, and each of the openings has a sidewall; a dielectric thin film covering at least a portion of the sidewall of each of the openings; an etch stop layer disposed between the semiconductor substrate and the dielectric layer and extending partially into the openings to isolate the dielectric thin film from the semiconductor substrate; and a metal layer filled in the openings.
摘要翻译：公开了一种开口结构。开口结构包括：半导体衬底; 设置在所述半导体衬底上的至少一个电介质层，其中所述电介质层具有暴露所述半导体衬底的多个开口，并且每个所述开口具有侧壁; 覆盖每个开口的侧壁的至少一部分的电介质薄膜; 蚀刻停止层，设置在所述半导体衬底和所述电介质层之间并且部分地延伸到所述开口中以将所述电介质薄膜与所述半导体衬底隔离; 以及填充在开口中的金属层。

7. 发明申请

US20120270403A1 METHOD OF FABRICATING OPENINGS 有权
标题翻译：制作开口的方法
公开(公告)号：US20120270403A1
公开(公告)日：2012-10-25
申请号：US13535370
申请日：2012-06-28
申请人： Feng-Yi Chang , Pei-Yu Chou , Jiunn-Hsiung Liao , Chih-Wen Feng , Ying-Chih Lin , Po-Chao Tsao
发明人： Feng-Yi Chang , Pei-Yu Chou , Jiunn-Hsiung Liao , Chih-Wen Feng , Ying-Chih Lin , Po-Chao Tsao
IPC分类号： H01L21/306
CPC分类号： H01L21/76802 , H01L21/76831 , H01L21/76897
摘要： A method of fabricating openings is disclosed. First, a semiconductor substrate having a salicide region thereon is provided. An etch stop layer and at least a dielectric layer are disposed on the semiconductor substrate from bottom to top. Second, the dielectric layer and the etching stop layer are patterned to form a plurality of openings in the dielectric layer and in the etching stop layer so that the openings expose the salicide region. Then, a dielectric thin film covering the dielectric layer, sidewalls of the openings and the salicide region is formed. Later, the dielectric thin film disposed on the dielectric layer and on the salicide region is removed.
摘要翻译：公开了一种制造开口的方法。首先，提供其上具有自对准硅化物区域的半导体衬底。蚀刻停止层和至少介电层从底部到顶部设置在半导体衬底上。其次，对电介质层和蚀刻停止层进行图案化以在电介质层和蚀刻停止层中形成多个开口，使得开口露出自对准区域。然后，形成覆盖电介质层的电介质薄膜，开口侧壁和自对准硅化物区域。然后，去除设置在电介质层和自对准硅化物区域上的电介质薄膜。

8. 发明授权

US08164141B2 Opening structure with sidewall of an opening covered with a dielectric thin film 有权
标题翻译：具有覆盖有介电薄膜的开口的侧壁的开口结构
公开(公告)号：US08164141B2
公开(公告)日：2012-04-24
申请号：US12884198
申请日：2010-09-17
申请人： Po-Chao Tsao , Chang-Chi Huang , Ming-Tsung Chen , Feng-Yi Chang , Pei-Yu Chou , Jiunn-Hsiung Liao , Chih-Wen Feng , Ying-Chih Lin
发明人： Po-Chao Tsao , Chang-Chi Huang , Ming-Tsung Chen , Feng-Yi Chang , Pei-Yu Chou , Jiunn-Hsiung Liao , Chih-Wen Feng , Ying-Chih Lin
IPC分类号： H01L29/78
CPC分类号： H01L21/31144 , H01L21/76802 , H01L21/76831 , H01L23/485
摘要： An opening structure includes a semiconductor substrate, at least one dielectric layer disposed on the semiconductor substrate, wherein the dielectric layer has a plurality of openings exposing the semiconductor substrate, and each of the openings has a sidewall, a dielectric thin film covering at least a portion of the sidewall of each of the openings, and a metal layer filled in the openings.
摘要翻译：开口结构包括半导体衬底，设置在半导体衬底上的至少一个电介质层，其中所述电介质层具有暴露所述半导体衬底的多个开口，并且每个所述开口具有侧壁，至少覆盖至少一个的电介质薄膜每个开口的侧壁的一部分，以及填充在开口中的金属层。

9. 发明授权

US08101092B2 Method for controlling ADI-AEI CD difference ratio of openings having different sizes 有权
标题翻译：用于控制具有不同尺寸的开口的ADI-AEI CD差异比率的方法
公开(公告)号：US08101092B2
公开(公告)日：2012-01-24
申请号：US11877918
申请日：2007-10-24
申请人： Chih-Wen Feng , Pei-Yu Chou , Chun-Ting Yeh , Jyh-Cherng Yau , Jiunn-Hsiung Liao , Feng-Yi Chang , Ying-Chih Lin
发明人： Chih-Wen Feng , Pei-Yu Chou , Chun-Ting Yeh , Jyh-Cherng Yau , Jiunn-Hsiung Liao , Feng-Yi Chang , Ying-Chih Lin
IPC分类号： C03C15/00 , H01L21/4763
CPC分类号： H01L21/31144 , H01L21/0276 , H01L21/31116 , H01L21/31138 , H01L21/76816 , H01L21/76897
摘要： A method for controlling ADI-AEI CD difference ratios of openings having different sizes is provided. First, a first etching step using a patterned photoresist layer as a mask is performed to form a patterned Si-containing material layer and a polymer layer on sidewalls thereof. Next, a second etching step is performed with the patterned photoresist layer, the patterned Si-containing material layer and the polymer layer as masks to at least remove an exposed portion of a etching resistive layer to form a patterned etching resistive layer. A portion of a target material layer is removed by using the patterned etching resistive layer as an etching mask to form a first and a second openings in the target material layer. The method is characterized by controlling etching parameters of the first and second etching steps to obtain predetermined ADI-AEI CD difference ratios.
摘要翻译：提供了一种用于控制具有不同尺寸的开口的ADI-AEI CD差异比率的方法。首先，使用图案化的光致抗蚀剂层作为掩模进行第一蚀刻步骤，以在其侧壁上形成图案化的含Si材料层和聚合物层。接下来，利用图案化的光致抗蚀剂层，图案化的含Si材料层和聚合物层作为掩模来执行第二蚀刻步骤，以至少去除蚀刻电阻层的暴露部分以形成图案化的蚀刻电阻层。通过使用图案化的蚀刻电阻层作为蚀刻掩模来去除目标材料层的一部分，以在靶材料层中形成第一和第二开口。该方法的特征在于控制第一和第二蚀刻步骤的蚀刻参数以获得预定的ADI-AEI CD差异比。

10. 发明申请

US20120001338A1 OPENING STRUCTURE 有权
标题翻译：开放式结构
公开(公告)号：US20120001338A1
公开(公告)日：2012-01-05
申请号：US13234159
申请日：2011-09-16
申请人： Po-Chao Tsao , Chang-Chi Huang , Ming-Tsung Chen , Feng-Yi Chang , Pei-Yu Chou , Jiunn-Hsiung Liao , Chih-Wen Feng , Ying-Chih Lin
发明人： Po-Chao Tsao , Chang-Chi Huang , Ming-Tsung Chen , Feng-Yi Chang , Pei-Yu Chou , Jiunn-Hsiung Liao , Chih-Wen Feng , Ying-Chih Lin
IPC分类号： H01L23/48
CPC分类号： H01L21/31144 , H01L21/76802 , H01L21/76831 , H01L23/485
摘要： An opening structure is disclosed. The opening structure includes: a semiconductor substrate; at least one dielectric layer disposed on the semiconductor substrate, wherein the dielectric layer has a plurality of openings exposing the semiconductor substrate, and each of the openings has a sidewall; a dielectric thin film covering at least a portion of the sidewall of each of the openings; an etch stop layer disposed between the semiconductor substrate and the dielectric layer and extending partially into the openings to isolate the dielectric thin film from the semiconductor substrate; and a metal layer filled in the openings.
摘要翻译：公开了一种开口结构。开口结构包括：半导体衬底; 设置在所述半导体衬底上的至少一个电介质层，其中所述电介质层具有暴露所述半导体衬底的多个开口，并且每个所述开口具有侧壁; 覆盖每个开口的侧壁的至少一部分的电介质薄膜; 蚀刻停止层，设置在所述半导体衬底和所述电介质层之间并且部分地延伸到所述开口中以将所述电介质薄膜与所述半导体衬底隔离; 以及填充在开口中的金属层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式