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1. 发明申请

US20100299576A1 System to Improve Miscorrection Rates in Error Control Code Through Buffering and Associated Methods 失效
标题翻译：系统通过缓冲和相关方法提高错误控制代码的误码率
公开(公告)号：US20100299576A1
公开(公告)日：2010-11-25
申请号：US12023516
申请日：2008-01-31
申请人： Irving G. Baysah , Timothy J. Dell , Luis A. Lastras-Montano , Warren E. Maule , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
发明人： Irving G. Baysah , Timothy J. Dell , Luis A. Lastras-Montano , Warren E. Maule , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1044
摘要： A system to improve miscorrection rates in error control code may include an error control decoder with a safe decoding mode that processes at least two data packets. The system may also include a buffer to receive the processed at least two data packets from the error control decoder. The error control decoder may apply a logic OR operation to the uncorrectable error signal related to the processing of the at least two data packets to produce a global uncorrectable error signal. The system may further include a recipient to receive the at least two data packets and the global uncorrectable error signal.
摘要翻译：用于改善错误控制代码中的错误率的系统可以包括处理至少两个数据分组的具有安全解码模式的错误控制解码器。系统还可以包括缓冲器，以从误差控制解码器接收经处理的至少两个数据分组。误差控制解码器可以对与至少两个数据分组的处理相关的不可校正误差信号应用逻辑或运算，以产生全局不可校正的误差信号。系统还可以包括接收器以接收至少两个数据分组和全局不可校正的误差信号。

2. 发明授权

US08176391B2 System to improve miscorrection rates in error control code through buffering and associated methods 失效
标题翻译：系统通过缓冲和相关方法提高错误控制代码中的错误率
公开(公告)号：US08176391B2
公开(公告)日：2012-05-08
申请号：US12023516
申请日：2008-01-31
申请人： Irving G. Baysah , Timothy J. Dell , Luis A. Lastras-Montano , Warren E. Maule , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
发明人： Irving G. Baysah , Timothy J. Dell , Luis A. Lastras-Montano , Warren E. Maule , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
IPC分类号： H03M13/00
CPC分类号： G06F11/1044
摘要： A system to improve miscorrection rates in error control code may include an error control decoder with a safe decoding mode that processes at least two data packets. The system may also include a buffer to receive the processed at least two data packets from the error control decoder. The error control decoder may apply a logic OR operation to the uncorrectable error signal related to the processing of the at least two data packets to produce a global uncorrectable error signal. The system may further include a recipient to receive the at least two data packets and the global uncorrectable error signal.
摘要翻译：用于改善错误控制代码中的错误率的系统可以包括处理至少两个数据分组的具有安全解码模式的错误控制解码器。系统还可以包括缓冲器，以从误差控制解码器接收经处理的至少两个数据分组。误差控制解码器可以对与至少两个数据分组的处理相关的不可校正误差信号应用逻辑或运算，以产生全局不可校正的误差信号。系统还可以包括接收器以接收至少两个数据分组和全局不可校正的误差信号。

3. 发明授权

US08185801B2 System to improve error code decoding using historical information and associated methods 有权
标题翻译：系统使用历史信息和相关方法改进错误码解码
公开(公告)号：US08185801B2
公开(公告)日：2012-05-22
申请号：US12023445
申请日：2008-01-31
申请人： Timothy J. Dell , Luis A. Lastras-Montano , Barry M. Trager , Shmuel Winograd
发明人： Timothy J. Dell , Luis A. Lastras-Montano , Barry M. Trager , Shmuel Winograd
IPC分类号： H03M13/00
CPC分类号： G06F11/1044
摘要： A system to improve error code decoding using historical information. An example system includes storage partitioned into memory ranks, and a table to record symbols having failures for each memory rank. The system generates a memory rank score for each memory rank. The system also includes an error control decoder that uses the memory rank score when each memory rank is accessed in order to determine whether an error should be corrected or not.
摘要翻译：一种使用历史信息改进错误代码解码的系统。示例性系统包括分割成存储器排名的存储器，以及用于记录具有每个存储器级别的故障的符号的表。系统为每个存储器级别生成内存等级分数。该系统还包括错误控制解码器，当访问每个存储器等级时，使用存储器等级分数，以便确定是否应该纠正错误。

4. 发明申请

US20100287445A1 System to Improve Memory Reliability and Associated Methods 有权
标题翻译：提高内存可靠性和相关方法的系统
公开(公告)号：US20100287445A1
公开(公告)日：2010-11-11
申请号：US12023374
申请日：2008-01-31
申请人： Timothy J. Dell , Luis A. Lastras-Montano , Barry M. Trager , Shmuel Winograd
发明人： Timothy J. Dell , Luis A. Lastras-Montano , Barry M. Trager , Shmuel Winograd
IPC分类号： H03M13/05 , G06F11/10 , H03M13/07
CPC分类号： H03M13/1545 , G06F11/1044 , H03M13/1515
摘要： A system to improve memory reliability in computer systems that may include memory chips, and may rely on a error control encoder to send codeword symbols for storage in each of the memory chips. At least two symbols from a codeword are assigned to each memory chip and therefore failure of any of the memory chips could affect two symbols or more. The system may also include a table to record failures and partial failures of the codeword symbols for each of the memory chips so the error control encoder can correct subsequent partial failures based upon the previous partial failures. The error control coder is capable of correcting and/or detecting more errors if only a fraction of a chip is noted in the table as having a failure as opposed to a full chip noted as having a failure.
摘要翻译：一种用于提高可能包括存储器芯片的计算机系统中的存储器可靠性的系统，并且可以依赖于错误控制编码器来发送用于存储在每个存储器芯片中的码字符号。来自码字的至少两个符号被分配给每个存储器芯片，因此任何存储器芯片的故障可能影响两个或更多个符号。该系统还可以包括用于记录每个存储器芯片的码字符号的故障和部分故障的表，因此错误控制编码器可以基于先前的部分故障来校正随后的部分故障。误差控制编码器能够校正和/或检测更多的误差，如果在表中只有一部分芯片被注意为具有故障，而不是被称为具有故障的全芯片。

5. 发明申请

US20100287454A1 System to Improve Error Code Decoding Using Historical Information and Associated Methods 有权
标题翻译：使用历史信息和相关方法改进错误代码解码的系统
公开(公告)号：US20100287454A1
公开(公告)日：2010-11-11
申请号：US12023445
申请日：2008-01-31
申请人： Timothy J. Dell , Luis A. Lastras-Montano , Barry M. Trager , Shmuel Winograd
发明人： Timothy J. Dell , Luis A. Lastras-Montano , Barry M. Trager , Shmuel Winograd
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： G06F11/1044
摘要： A system to improve error code decoding using historical information may include storage partitioned into memory ranks, and a table to record symbols having failures for each memory rank. The system may also generate a memory rank score for each memory rank. The system may also include an error control decoder that may use the memory rank score when each memory rank is accessed in order to determine whether an error should be corrected or not.
摘要翻译：使用历史信息改进错误代码解码的系统可以包括分割成存储器排名的存储器，以及记录具有每个存储器级别故障的符号的表。系统还可以为每个存储器等级产生存储器等级分数。系统还可以包括错误控制解码器，其可以在访问每个存储器级时使用存储器等级分数，以便确定是否应该纠正错误。

6. 发明授权

US08171377B2 System to improve memory reliability and associated methods 有权
标题翻译：系统提高内存可靠性和相关方法
公开(公告)号：US08171377B2
公开(公告)日：2012-05-01
申请号：US12023374
申请日：2008-01-31
申请人： Timothy J. Dell , Luis A. Lastras-Montano , Barry M. Trager , Shmuel Winograd
发明人： Timothy J. Dell , Luis A. Lastras-Montano , Barry M. Trager , Shmuel Winograd
IPC分类号： G11C29/00
CPC分类号： H03M13/1545 , G06F11/1044 , H03M13/1515
摘要： A system to improve memory reliability in computer systems that may include memory chips, and may rely on a error control encoder to send codeword symbols for storage in each of the memory chips. At least two symbols from a codeword are assigned to each memory chip and therefore failure of any of the memory chips could affect two symbols or more. The system may also include a table to record failures and partial failures of the codeword symbols for each of the memory chips so the error control encoder can correct subsequent partial failures based upon the previous partial failures. The error control coder is capable of correcting and/or detecting more errors if only a fraction of a chip is noted in the table as having a failure as opposed to a full chip noted as having a failure.
摘要翻译：一种用于提高可能包括存储器芯片的计算机系统中的存储器可靠性的系统，并且可以依赖于错误控制编码器来发送用于存储在每个存储器芯片中的码字符号。来自码字的至少两个符号被分配给每个存储器芯片，因此任何存储器芯片的故障可能影响两个或更多个符号。该系统还可以包括用于记录每个存储器芯片的码字符号的故障和部分故障的表，因此错误控制编码器可以基于先前的部分故障来校正随后的部分故障。误差控制编码器能够校正和/或检测更多的误差，如果在表中只有一部分芯片被注意为具有故障，而不是被称为具有故障的全芯片。

7. 发明授权

US08245105B2 Cascade interconnect memory system with enhanced reliability 有权
标题翻译：级联互连存储器系统具有增强的可靠性
公开(公告)号：US08245105B2
公开(公告)日：2012-08-14
申请号：US12166235
申请日：2008-07-01
申请人： Timothy J. Dell , Kevin C. Gower , Warren E. Maule , Michael R. Trombley
发明人： Timothy J. Dell , Kevin C. Gower , Warren E. Maule , Michael R. Trombley
IPC分类号： H03M13/00
CPC分类号： G06F11/0772 , G06F11/073 , G06F11/0781 , G06F11/1004 , G11C5/04 , G11C29/70 , G11C2029/0409 , G11C2029/0411
摘要： A hub device, memory system, and method for providing a cascade interconnect memory system with enhanced reliability. The hub device includes an interface to a high-speed bus for communicating with a memory controller. The memory controller and the hub device are included in a cascade interconnect memory system and the high-speed bus includes bit lanes and one or more clock lanes. The hub device also includes a bi-directional fault signal line in communication with the memory controller and readable by a service interface. The hub device also includes a fault isolation register (FIR) for storing information about failures detected at the hub device, the information including severity levels of the detected failures. In addition, the hub device includes error recovery logic for responding to a failure detected at the hub device.
摘要翻译：一种用于提供具有增强的可靠性的级联互连存储器系统的集线器设备，存储器系统和方法。集线器设备包括与高速总线的接口，用于与存储器控制器进行通信。存储器控制器和集线器设备包括在级联互连存储器系统中，并且高速总线包括位通道和一个或多个时钟通道。集线器设备还包括与存储器控制器通信并可由服务接口读取的双向故障信号线。集线器设备还包括用于存储关于在集线器设备处检测到的故障的信息的故障隔离寄存器（FIR），该信息包括检测到的故障的严重性级别。此外，集线器设备包括用于响应在集线器设备处检测到的故障的错误恢复逻辑。

8. 发明申请

US20100005366A1 CASCADE INTERCONNECT MEMORY SYSTEM WITH ENHANCED RELIABILITY 有权
标题翻译：具有增强可靠性的CASCADE互连存储器系统
公开(公告)号：US20100005366A1
公开(公告)日：2010-01-07
申请号：US12166235
申请日：2008-07-01
申请人： Timothy J. Dell , Kevin C. Gower , Warren E. Maule , Michael R. Trombley
发明人： Timothy J. Dell , Kevin C. Gower , Warren E. Maule , Michael R. Trombley
IPC分类号： G06F11/10 , H03M13/00 , G11C29/00 , G06F11/14
CPC分类号： G06F11/0772 , G06F11/073 , G06F11/0781 , G06F11/1004 , G11C5/04 , G11C29/70 , G11C2029/0409 , G11C2029/0411
摘要： A hub device, memory system, and method for providing a cascade interconnect memory system with enhanced reliability. The hub device includes an interface to a high-speed bus for communicating with a memory controller. The memory controller and the hub device are included in a cascade interconnect memory system and the high-speed bus includes bit lanes and one or more clock lanes. The hub device also includes a bi-directional fault signal line in communication with the memory controller and readable by a service interface. The hub device also includes a fault isolation register (FIR) for storing information about failures detected at the hub device, the information including severity levels of the detected failures. In addition, the hub device includes error recovery logic for responding to a failure detected at the hub device. Responding to the error includes recording a severity level of the failure in the FIR and taking an action at the hub device that is responsive to the severity level of the failure. The action includes one or more of fast clock stop, setting the bi-directional fault indicator, setting cyclical redundancy code (CRC) bits and transmitting them to the memory controller, re-try, sparing out a bit lane and sparing out a clock lane.
摘要翻译：一种用于提供具有增强的可靠性的级联互连存储器系统的集线器设备，存储器系统和方法。集线器设备包括与高速总线的接口，用于与存储器控制器进行通信。存储器控制器和集线器设备包括在级联互连存储器系统中，并且高速总线包括位通道和一个或多个时钟通道。集线器设备还包括与存储器控制器通信并可由服务接口读取的双向故障信号线。集线器设备还包括用于存储关于在集线器设备处检测到的故障的信息的故障隔离寄存器（FIR），该信息包括检测到的故障的严重性级别。此外，集线器设备包括用于响应在集线器设备处检测到的故障的错误恢复逻辑。响应该错误包括在FIR中记录故障的严重性级别，并在响应于故障严重性级别的集线器设备上执行操作。该动作包括一个或多个快速时钟停止，设置双向故障指示器，设置循环冗余码（CRC）位并将其发送到存储器控制器，重新尝试，省略一个位线并省出一个时钟通道。

9. 发明申请

US20090006886A1 SYSTEM AND METHOD FOR ERROR CORRECTION AND DETECTION IN A MEMORY SYSTEM 有权
标题翻译：用于记忆系统中错误校正和检测的系统和方法
公开(公告)号：US20090006886A1
公开(公告)日：2009-01-01
申请号：US11769929
申请日：2007-06-28
申请人： James A. O'Connor , Luis A. Lastras-Montano , Luis C. Alves , William J. Clarke , Timothy J. Dell , Thomas J. Dewkett , Kevin C. Gower
发明人： James A. O'Connor , Luis A. Lastras-Montano , Luis C. Alves , William J. Clarke , Timothy J. Dell , Thomas J. Dewkett , Kevin C. Gower
IPC分类号： G06F11/20
CPC分类号： G06F11/108 , G06F2211/1045 , G06F2211/1057 , G06F2211/1064
摘要： A system and method for error correction and detection in a memory system. The system includes a memory controller, a plurality of memory modules and a mechanism. The memory modules are in communication with the memory controller and with a plurality of memory devices. The mechanism detects that one of the memory modules has failed possibly coincident with a memory device failure on an other of the memory modules. The mechanism allows the memory system to continue to run unimpaired in the presence of the memory module failure and the memory device failure.
摘要翻译：一种用于存储系统中的纠错和检测的系统和方法。该系统包括存储器控制器，多个存储器模块和机构。存储器模块与存储器控制器和多个存储器件通信。该机制检测到其中一个内存模块出现故障，可能与其他内存模块上的内存设备故障一致。该机制允许内存系统在内存模块故障和内存设备故障的情况下继续运行不受损坏。

10. 发明授权

US07721140B2 Systems and methods for improving serviceability of a memory system 失效
标题翻译：用于提高存储系统可维护性的系统和方法
公开(公告)号：US07721140B2
公开(公告)日：2010-05-18
申请号：US11619038
申请日：2007-01-02
申请人： Timothy J. Dell , Luis A. Lastras-Montano
发明人： Timothy J. Dell , Luis A. Lastras-Montano
IPC分类号： G06F11/00
CPC分类号： G11C29/56008 , G06F11/1012 , G11C5/04 , G11C2029/0409
摘要： Systems and methods for improving serviceability of a memory system including a method for identifying a failing memory element in a memory system when two or more modules operate in unison in response to a read request. The method includes receiving syndrome bits and an address associated with an uncorrectable error (UE). In response to a previous correctable error (CE) having occurred, the location of the previous CE is retrieved. The location of the CE specifies a memory device position of the CE. A location of the UE is determined using the location of the previous CE and the syndrome bits of the UE as input. The location of the UE specified a memory device position. A failing memory element associated with the location of the UE is identified.
摘要翻译：一种用于提高存储系统的可维护性的系统和方法，包括当两个或多个模块响应于读取请求而一致地操作时，用于识别存储器系统中的故障存储器元件的方法。该方法包括接收校正子位和与不可校正误差（UE）相关联的地址。响应于已经发生的先前可校正错误（CE），检索先前CE的位置。 CE的位置指定CE的存储设备位置。使用先前CE的位置和UE的校正子位作为输入来确定UE的位置。 UE的位置指定了存储设备位置。识别与UE的位置相关联的故障存储器元件。

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