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1. 发明授权

US06340882B1 Accurate current source with an adjustable temperature dependence circuit 失效
标题翻译：具有可调温度相关电路的精确电流源
公开(公告)号：US06340882B1
公开(公告)日：2002-01-22
申请号：US09678563
申请日：2000-10-03
申请人： Paul W. Chung , John T. Contreras
发明人： Paul W. Chung , John T. Contreras
IPC分类号： G05F316
CPC分类号： G05F3/225
摘要： An accurate current source with an adjustable temperature dependence. This type of current source is used in silicon Integrated Circuit (IC) designs requiring supporting reference-voltage sources and/or reference-current sources which may be designed with or without temperature dependence. The circuit generates an accurate current with temperature independence along with another accurate current source with temperature dependence using only one precision external resistors. For the temperature-dependent current source, the temperature dependence can be controlled by setting a temperature dependence factor (TDF).
摘要翻译：具有可调温度依赖性的精确电流源。这种电流源用于需要支持参考电压源和/或参考电流源的硅集成电路（IC）设计，可以设计有或没有温度依赖性。该电路产生与温度无关的精确电流以及仅使用一个精密外部电阻的温度依赖性的另一个精确电流源。对于依赖于温度的电流源，可以通过设置温度依赖因子（TDF）来控制温度依赖性。

2. 发明授权

US4496852A Low power clock generator 失效
标题翻译：低功率时钟发生器
公开(公告)号：US4496852A
公开(公告)日：1985-01-29
申请号：US441707
申请日：1982-11-15
申请人： Eugene M. Blaser , Paul W. Chung , Ramesh C. Varshney
发明人： Eugene M. Blaser , Paul W. Chung , Ramesh C. Varshney
IPC分类号： H03K5/02 , H03K17/06 , H03K19/017 , H03K19/094 , H03K5/135 , H03K17/10 , H03K19/096
CPC分类号： H03K19/01735 , H03K5/023
摘要： A clock generator circuit for producing with very little power dissipation an output clock signal having levels determined by positive and negative power supply levels from an input clock signal having levels determined by the positive power supply level and ground. In a low state of the input clock signal, an upper or first transistor of an output transistor pair connected in series between positive and negative power supply levels is turned off by applying a ground level to the base thereof, while the lower or second transistor of the output transistor pair is turned off by applying a positive potential to its base. When the input clock signal makes a transition from the low state to the high state, a bootstrap capacitor is charged between the positive and negative power supply levels to provide a boosted positive voltage to turn on the upper transistor. While the bootstrap capacitor is charging, the base of the lower transistor is lightly grounded to partially turn it on. When the charge on the bootstrap capacitor has reached a predetermined level, the base of the first transistor is taken to the negative power supply level through an inverting transistor, the base of which also receives the boosted voltage developed across the bootstrap capacitor. By using a fully dynamic circuit arrangement, only a very small amount of power is required for operating the circuit.
摘要翻译：一种时钟发生器电路，其具有非常小的功耗，其输出时钟信号具有由正电源电平和地电平确定的电平的输入时钟信号由正和负电源电平确定的电平。在输入时钟信号的低状态下，串联连接在正电源电平和负电源电平之间的输出晶体管对的上或第一晶体管通过对其基极施加接地电平而被关断，而下或第二晶体管通过向其基极施加正电位来关断输出晶体管对。当输入时钟信号从低状态转变到高电平状态时，在正电源电压和负电源电平之间充电自举电容器，以提供升压的正电压来接通上部晶体管。当自举电容器充电时，下晶体管的基极轻微接地以部分地将其接通。当自举电容器上的电荷达到预定电平时，第一晶体管的基极通过反相晶体管被带到负电源电平，反相晶体管的基极也接收跨越自举电容器产生的升压电压。通过使用完全动态的电路布置，操作电路只需要极少的功率。

3. 发明授权

US4929918A Setting and dynamically adjusting VCO free-running frequency at system level 失效
标题翻译：在系统级设置和动态调整VCO自由运行频率
公开(公告)号：US4929918A
公开(公告)日：1990-05-29
申请号：US363566
申请日：1989-06-07
申请人： Paul W. Chung , Ralph L. Gee , Luke C. K. Lang , Paik Saber
发明人： Paul W. Chung , Ralph L. Gee , Luke C. K. Lang , Paik Saber
IPC分类号： G11B20/14 , G11B20/12 , H03L7/113 , H03L7/14
CPC分类号： H03L7/113 , G11B20/1258
摘要： A method and means for setting the free-running frequency of a voltage controlled oscillator (VCO) without requiring laser trimming or the like is described. The VCO forms part of an interconnected phase-locked loop (PLL) and frequency-locked loop (FLL). At system power on, the PLL is automatically disabled and a digital-to-analog (DAC) in the PLL is set to a value corresponding substantially to the center of a preselected lock range. The FLL, which includes a second DAC, then operates to generate a bias voltage for incrementing or decrementing the VCO output frequency until the VCO pulse count stored in a register equals an expected count; whereupon the VCO will be set at its free-running frequency. When the PLL is enabled, a phase error generator generates a digital phase error signal from the input data. A digital integrator converts the phase error signal to a digital frequency error signal. These error signals are added and the result is supplied to the DAC in the PLL for providing an analog output indicative of PLL frequency error. The outputs from both DACs are summed and the resultant current is converted to a bias voltage to adjust the VCO frequency as necessary for normally maintaining it within said lock range. If the VCO frequency deviates from said range, the frequency error signal to the PLL DAC is zeroed, and the frequency error signal is supplied to the FLL DAC. The phase error signal from the PLL DAC and the signal from the FLL DAC as modified by the frequency error signal are summed, and the resultant current in converted to a bias voltage to adjust the VCO frequency to within said lock range.

4. 发明授权

US5012246A BiCMOS analog-to-digital converter with minimized metastability 失效
标题翻译： BiCMOS模数转换器，具有最小的亚稳态
公开(公告)号：US5012246A
公开(公告)日：1991-04-30
申请号：US472974
申请日：1990-01-31
申请人： Paul W. Chung , Karl R. Hense , Kim Y. Nguyen
发明人： Paul W. Chung , Karl R. Hense , Kim Y. Nguyen
IPC分类号： H03M1/36 , H03M1/08
CPC分类号： H03M1/0872 , H03M1/361
摘要： A high performance, low power analog to digital converter is designed in BIFET technology utilizing the high gain, high performance of a bipolar comparator and the low power of a CMOS latch and CMOS encoding logic circuits. Using a FET dynamic latch, metastability is avoided, significantly reducing soft error rate.

5. 发明授权

US4808840A Dynamic edge-triggered latch 失效
标题翻译：动态边沿触发锁存
公开(公告)号：US4808840A
公开(公告)日：1989-02-28
申请号：US123498
申请日：1987-11-20
申请人： Paul W. Chung , Niantsu N. Wang
发明人： Paul W. Chung , Niantsu N. Wang
IPC分类号： H03K3/356 , H03K3/013 , H03K3/15 , H03K3/295 , H03K3/86
CPC分类号： H03K3/356026
摘要： An edge-triggered latch is disclosed which has a low setup time and almost no metastability problem. It comprises a dynamic sensing means for detecting the voltage level of the data signal and at least one dynamic buffer for amplifying said detected voltage level into one of two logic levels recognizable by a static latch wherein the sampled result is stored.

6. 发明授权

US5422642A DC centering analog receiver for flash A/D converter 失效
标题翻译：用于闪存A / D转换器的直流定心模拟接收器
公开(公告)号：US5422642A
公开(公告)日：1995-06-06
申请号：US81760
申请日：1993-06-22
申请人： Paul W. Chung , John E. Gersbach , Bac Pham , Karl Hense , Pete Granata
发明人： Paul W. Chung , John E. Gersbach , Bac Pham , Karl Hense , Pete Granata
IPC分类号： G11B20/10 , H03M1/06 , H03M1/08 , H03M1/10 , H03M1/12 , H03M1/36
CPC分类号： H03M1/0607
摘要： An analog receiver circuit suitable for use with a flash analog-to-digital converter is described. A first stage of the receiver acts essentially as a voltage follower, receiving the centertap voltage of a flash A/D converter resistor ladder, and maintaining an internal reference voltage substantially equal to the centertap voltage over time. A second stage of the analog receiver acts as centering means, receiving an analog signal and centering it with respect to the internal reference voltage provided by the first stage. The receiver is thus able to provide an analog signal to the flash A/D converter which is dynamically centered with respect to the converter's operating voltage, thereby reducing DC offset. Moreover, introducing the analog signal at the second stage minimizes the bandwidth-limiting elements between this input signal and the DC-centered output signal. Thus DC offset is further reduced and operating frequencies of 500 MTz or greater are possible.
摘要翻译：描述适用于闪存模数转换器的模拟接收机电路。接收器的第一级基本上作为电压跟随器，接收闪存A / D转换器电阻梯的centertap电压，并且保持内部参考电压基本上等于Centertap电压随时间变化。模拟接收机的第二级用作对中装置，接收模拟信号并使其相对于由第一级提供的内部参考电压居中。因此，接收器能够向闪存A / D转换器提供模拟信号，闪存A / D转换器相对于转换器的工作电压动态地居中，从而减少DC偏移。此外，在第二级引入模拟信号使得该输入信号和以DC为中心的输出信号之间的带宽限制元件最小化。因此，DC偏移进一步降低，并且500MTz或更大的工作频率是可能的。

7. 发明授权

US5057785A Method and circuitry to suppress additive disturbances in data channels 失效
标题翻译：在数据通道中抑制加性干扰的方法和电路
公开(公告)号：US5057785A
公开(公告)日：1991-10-15
申请号：US468526
申请日：1990-01-23
申请人： Paul W. Chung , Michael O. Jenkins , Stephen A. Jove , Klaas B. Klaassen , Paik Saber , Jacobus C. L. van Peppen
发明人： Paul W. Chung , Michael O. Jenkins , Stephen A. Jove , Klaas B. Klaassen , Paik Saber , Jacobus C. L. van Peppen
IPC分类号： G11B5/09 , G11B5/00 , G11B5/012 , G11B5/02 , G11B20/02 , G11B20/24
CPC分类号： G11B20/02 , G11B20/24 , G11B5/012 , G11B2005/0016 , G11B5/02
摘要： A method and circuitry for suppressing additive transient disturbances in an analog differential input signal, such disturbances being due, for example, to thermal asperity transients caused by an MR transducer contacting a moving storage surface. The input data signal is algebraically summed with a corrective feedback signal for providing as output signal. The output signal is fed back to a circuit including an envelope detector and differentiator and converted into another signal that is the derivative of an amplitude envelope corresponding to the output signal. Nonlinear signal-adaptive filter means converts said other signal into the corrective feedback signal, which substantially replicates the additive transient disturbance and is subtracted from the data input signal to render the output signal substantially free of the transient disturbance.The input, output and corrective signals are preferably differential signals.

8. 发明授权

US4649516A Dynamic row buffer circuit for DRAM 失效
标题翻译： DRAM的动态行缓冲电路
公开(公告)号：US4649516A
公开(公告)日：1987-03-10
申请号：US616045
申请日：1984-06-01
申请人： Paul W. Chung , Richard E. Matick , Daniel T. Ling
发明人： Paul W. Chung , Richard E. Matick , Daniel T. Ling
IPC分类号： G11C11/401 , G06F12/00 , G11C7/10 , G11C11/4093 , G06F13/38
CPC分类号： G11C7/106 , G11C11/4093 , G11C7/1051 , G11C7/1075
摘要： A dynamic row buffer circuit is disclosed for a dynamic random access memory (DRAM) chip which enables the DRAM chip to be used for special function applications. The dynamic row buffer comprises a row buffer master register and a row buffer slave register. The row buffer master register comprises a plurality of master circuits (M1) and a plurality of slave circuits (S1). Likewise, the row buffer slave register comprises a plurality of master circuits (M2) and a plurality of slave circuits (S2). The row buffer master register is parallel load and parallel read-out with the outputs of the master register slave circuits being connected to the master circuits of the slave register. The row buffer slave register is a parallel load, serial read-out register with the output being shifted out of a secondary output port. The entire row buffer can be isolated from the memory array, and when so isolated, the memory array can be accessed through the primary input/output port in the same way as in an ordinary DRAM chip. This arrangement permits the conversion of a DRAM chip to a dual port display, of which a specific example is disclosed, or some other special function RAM thereby adding a large value to the DRAM chip with little additional cost.
摘要翻译：公开了用于动态随机存取存储器（DRAM）芯片的动态行缓冲器电路，其使DRAM芯片能够用于特殊功能应用。动态行缓冲器包括行缓冲器主寄存器和行缓冲器从寄存器。行缓冲器主寄存器包括多个主电路（M1）和多个从电路（S1）。类似地，行缓冲器从机寄存器包括多个主电路（M2）和多个从电路（S2）。行缓冲器主寄存器是并行负载并行读出，主寄存器从电路的输出端连接到从机寄存器的主电路。行缓冲器从寄存器是一个并行负载，串行读出寄存器，输出端从辅助输出端口移出。整个行缓冲器可以与存储器阵列隔离，并且当这样隔离时，存储器阵列可以以与普通DRAM芯片相同的方式通过主输入/输出端口访问。这种布置允许将DRAM芯片转换为双端口显示器，其中公开了一个具体示例，或者一些其他特殊功能RAM，从而以少量额外成本为DRAM芯片增加了大的价值。

9. 发明授权

US5391935A Assertive latching flip-flop 失效
标题翻译：自信锁定触发器
公开(公告)号：US5391935A
公开(公告)日：1995-02-21
申请号：US96102
申请日：1993-07-22
申请人： John E. Gersbach , Paul W. Chung
发明人： John E. Gersbach , Paul W. Chung
IPC分类号： H03K3/02 , H03K3/037 , H03K3/286 , H03K3/2885 , H03K3/356 , H03K3/29
CPC分类号： H03K3/2885 , H03K3/0375
摘要： An assertive latching flip-flop circuit is provided which prevents the occurrence of metastable outputs. The circuit comprises a single flip-flop which is comprised of standard switching transistors which are switched by a clocking mechanism having no additionally introduced delay. The circuit includes an imbalancing element which is coupled to a latching portion of the circuit. The latching portion of the circuit comprises a pair of cross-coupled transistors, in current mode embodiments of the invention, or a pair of cross-coupled inverters, in voltage mode embodiments of the invention. The imbalancing element introduces an electrical disturbance on the input line to one of the latching transistors or inverters. The imbalancing element is a capacitor in voltage mode embodiments of the invention and an additional transistor in current mode embodiments.
摘要翻译：提供了一种断言闩锁触发器电路，其防止亚稳输出的发生。该电路包括单个触发器，该触发器由标准开关晶体管组成，该标准开关晶体管由没有额外引入的延迟的时钟机构切换。电路包括耦合到电路的锁存部分的不平衡元件。在本发明的电压模式实施例中，电路的锁存部分包括在本发明的电流模式实施例中的一对交叉耦合晶体管或一对交叉耦合的反相器。不平衡元件将输入线上的电气干扰引入到一个锁存晶体管或反相器。不平衡元件是本发明的电压模式实施例中的电容器和当前模式实施例中的附加晶体管。

10. 发明授权

US4859880A High speed CMOS differential driver 失效
标题翻译：高速CMOS差分驱动器
公开(公告)号：US4859880A
公开(公告)日：1989-08-22
申请号：US207481
申请日：1988-06-16
申请人： Paul W. Chung , Niantsu N. Wang
发明人： Paul W. Chung , Niantsu N. Wang
IPC分类号： H03K5/02 , H03K5/151 , H03K17/687
CPC分类号： H03K5/151
摘要： A CMOS differential driver includes a differential amplifier with two input terminals. Complementary transfer gates selectively connect high and low voltage input terminals to the amplifier input terminals. The complementary transfer gates are controlled by identical logic input signals to provide exactly complementary voltage inputs to the differential amplifier circuit, so true complementary output signals are provided at the amplifier output terminals.

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