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1. 发明授权

US5360881A Method of cross-linking ethylene monomers using diallyloxyacetic acid and its basic addition salts as cross-linking agents 失效
标题翻译：使用二烯丙氧基乙酸及其碱式加成盐作为交联剂交联乙烯单体的方法
公开(公告)号：US5360881A
公开(公告)日：1994-11-01
申请号：US65446
申请日：1993-05-24
申请人： Paul Mallo , Christian Sidot , Alain Blanc , Yani Christidis
发明人： Paul Mallo , Christian Sidot , Alain Blanc , Yani Christidis
IPC分类号： C07C59/60 , C08F2/16 , C08F16/32 , C08F220/04
CPC分类号： C08F16/32 , C07C59/60
摘要： Diallyloxyacetic acid and its basic addition salts, their preparation process and their application as cross-linking agents.Diallyloxyacetic acid and its basic addition salts, preparation process and application as cross-linking agents.
摘要翻译：二烯丙氧基乙酸及其碱式加成盐，其制备方法及其作为交联剂的应用。二烯丙氧基乙酸及其碱式加成盐，制备方法和应用为交联剂。

2. 发明授权

US08085789B2 Algorithm and system for selecting acknowledgments from an array of collapsed VOQ's 失效
标题翻译：用于从收缩的VOQ数组中选择确认的算法和系统
公开(公告)号：US08085789B2
公开(公告)日：2011-12-27
申请号：US12365091
申请日：2009-02-03
申请人： Alain Blanc , Rene Glaise , Francois Le Maut , Michel Poret
发明人： Alain Blanc , Rene Glaise , Francois Le Maut , Michel Poret
IPC分类号： H04L12/28
CPC分类号： H04L49/3027 , H04L49/103 , H04L49/201 , H04L49/3045
摘要： A method for selecting packets to be switched in a collapsed virtual output queuing array (cVOQ) switch core, using a request/acknowledge mechanism is disclosed. An egress location for an ingress port is selected based on degrees of freedom for the selection mechanism. The degree of freedom can be derived from the collapsed virtual output queuing array by determining a number of egress locations to which an ingress port may send packets and determining a number of ingress ports from which an egress location can receive packets. Analyzing all the queued packets for assignment to an egress location, starting with a lesser degree of freedom and ending with a greater degree of freedom provides efficient switching allocations and acknowledgements.
摘要翻译：公开了一种使用请求/确认机制来选择在折叠的虚拟输出排队阵列（cVOQ）切换核心中切换的分组的方法。基于选择机制的自由度选择入口端口的出口位置。可以通过确定进入端口可以发送分组的出口位置的数量并确定出口位置可以从哪个入口端口接收分组的数目的入口端口，从折叠的虚拟输出排队阵列导出自由度。分析所有排队的分组以分配到出口位置，以较小的自由度开始，并以更大的自由度结束，从而提供有效的切换分配和确认。

3. 发明授权

US07430167B2 Method and system to enable an adaptive load balancing in a parallel packet switch 失效
标题翻译：在并行分组交换机中实现自适应负载均衡的方法和系统
公开(公告)号：US07430167B2
公开(公告)日：2008-09-30
申请号：US10711320
申请日：2004-09-10
申请人： Rene Glaise , Alain Blanc , Francois Le Maut , Michel Poret
发明人： Rene Glaise , Alain Blanc , Francois Le Maut , Michel Poret
IPC分类号： G06F11/00
CPC分类号： H04L47/125 , H04L49/1523 , H04L49/25 , H04L49/30 , H04L49/3045
摘要： A method and a system to adapt the load balancing of the incoming traffic over the planes of a parallel packet switch (PPS) on the basis of the monitoring of requests and acknowledgments exchanged between ingress port adapters and arrays of collapsed virtual output queues (cVOQ) situated within the plane switch cores is disclosed. According to the invention, at least one counter is associated, in each ingress port-adapter, to each individual switching plane or device to be monitored. Each of these counters is incremented when a request is sent to the corresponding individual switching plane or device and decremented when an acknowledgment is received from this individual switching plane or device. When the range of values taken by the counters of a same ingress port-adapter reaches a predetermined threshold, less (or none) incoming traffic is further transmitted to the individual switching plane or device associated to the higher value counter. An alarm signal is possibly raised too e.g., for replacing the defective individual switching plane or device.
摘要翻译：基于在入口端口适配器和折叠虚拟输出队列（cVOQ）阵列之间交换的请求和确认的监视来适应并行分组交换机（PPS）的平面上的入局业务的负载平衡的方法和系统，位于平面开关芯内。根据本发明，至少一个计数器在每个入口端口适配器中被关联到要监视的每个单独的切换平面或设备。当将请求发送到相应的单独的交换平面或设备时，这些计数器中的每一个递增，并且当从该单独的交换平面或设备接收到确认时递减。当相同入口端口适配器的计数器所取值的范围达到预定阈值时，较少（或无））进入流量进一步传输到与较高值计数器相关联的单独交换平面或设备。也可能引起报警信号，例如用于更换有缺陷的单独开关平面或装置。

4. 发明申请

US20060025945A1 Method and systems for optimizing high-speed signal transmission 失效
标题翻译：用于优化高速信号传输的方法和系统
公开(公告)号：US20060025945A1
公开(公告)日：2006-02-02
申请号：US11235856
申请日：2005-09-27
申请人： Alain Blanc , Patrick Jeanniot
发明人： Alain Blanc , Patrick Jeanniot
IPC分类号： G06F19/00
CPC分类号： H04L25/03343 , H04L1/0001 , H04L1/20 , H04L7/0337 , H04L2025/03375
摘要： A method and systems for automatically adjusting the parameters of signal emitter in a synchronous high-speed transmission system, is disclosed. According to the method of the invention, the quality of a high-speed received signal is analyzed for a plurality of sets of parameter values and the one producing the best signal quality is selected. In a first embodiment, the quality of the high-speed received signal is determined by analyzing a digital eye characterizing the signal behavior, obtained by over-sampling the high-speed received signal. In a second embodiment, the quality of the high-speed received signal is determined by analyzing the behavior of the phase rotator used for data sampling. Finally, in a third embodiment, the quality of the high-speed received signal is determined by analyzing a digital eye, obtained by moving the position of a phase rotator from one end to the other and sampling data at each position.
摘要翻译：公开了一种在同步高速传输系统中自动调整信号发射器参数的方法和系统。根据本发明的方法，对多组参数值分析高速接收信号的质量，并选择产生最佳信号质量的参数值。在第一实施例中，通过分析表征由高速接收信号过采样得到的信号行为的数字眼来确定高速接收信号的质量。在第二实施例中，通过分析用于数据采样的相位旋转器的行为来确定高速接收信号的质量。最后，在第三实施例中，通过分析通过将相位旋转器的位置从一端移动到另一端而获得的数字眼，并且在每个位置处采样数据来确定高速接收信号的质量。

5. 发明授权

US06990418B2 Method and systems for optimizing high-speed signal transmission 失效
公开(公告)号：US06990418B2
公开(公告)日：2006-01-24
申请号：US10697832
申请日：2003-10-30
申请人： Alain Blanc , Patrick Jeanniot
发明人： Alain Blanc , Patrick Jeanniot
IPC分类号： G01R13/00 , H04B17/00
CPC分类号： H04L25/03343 , H04L1/0001 , H04L1/20 , H04L7/0337 , H04L2025/03375
摘要： A method and systems for automatically adjusting the parameters of signal emitter in a synchronous high-speed transmission system, is disclosed. According to the method of the invention, the quality of a high-speed received signal is analyzed for a plurality of sets of parameter values and the one producing the best signal quality is selected. In a first embodiment, the quality of the high-speed received signal is determined by analyzing a digital eye characterizing the signal behavior, obtained by over-sampling the high-speed received signal. In a second embodiment, the quality of the high-speed received signal is determined by analyzing the behavior of the phase rotator used for data sampling. Finally, in a third embodiment, the quality of the high-speed received signal is determined by analyzing a digital eye, obtained by moving the position of a phase rotator from one end to the other and sampling data at each position.

6. 发明授权

US06606300B1 Flow control process for a switching system and system for performing the same 失效
公开(公告)号：US06606300B1
公开(公告)日：2003-08-12
申请号：US09219081
申请日：1998-12-22
申请人： Alain Blanc , Pierre Debord , Alain Saurel , Bernard Brezzo
发明人： Alain Blanc , Pierre Debord , Alain Saurel , Bernard Brezzo
IPC分类号： H04L1256
CPC分类号： H04L49/3081 , H04L49/1507 , H04L49/201 , H04L49/25 , H04L49/50 , H04L49/506 , H04L2012/563 , H04L2012/5672 , H04Q11/0478
摘要： A flow control process for a switching system having at least one switch core connected through serial communication links to remote and distributed Protocol Adapters or Protocol Engines through Switch Core Access Layer (SCAL) elements. For each input port i, the SCAL element contains a receive Protocol Interface corresponding to the adapter assigned to the input port i and a first serializer for providing attachment to the switch core by means of a first serial communication link. When the cells are received in the switch core, they are deserialized by means of a first deserializer. At each output port, the cells are serialized again by means of a second serializer and then transmitted via a second serial communication link, to the appropriate SCAL. The SCAL contains a second deserializer and a transmit Protocol Interface circuit for permitting attachment of the Protocol Adapter. The flow control process permits two flow control signals, a flow control receive (FCR) from the core to the SCAL, and a flow control transmit (FCX) from the SCAL back to the core. For transmission of the FCR signal in response to the detection of local saturation in the switch core, the process causes transfer of an internal FCR signal to the serializer located within the saturated core. The FCR is introduced in the normal data flow to be conveyed through the second serial link to the remote SCAL corresponding to the saturated input port of the core. An internal control signal can be transmitted to the Protocol Interface that is originating too many cells which results in the overloaded input port of the core. For the transmission of the FCX signal in response to the detection of a saturated Protocol Interface element at one output port, the process generates an internal control signal to the serializer located in the SCAL element. The serializer can introduce a FCX signal in the normal data flow which is conveyed to the core and then decoded by the deserializer in the core. Thus, the core can be informed of the saturation condition that has occurred in the considered output port. Particular adaptations are provided in which the switching system is arranged in a set of individual switching structures mounted in a port expansion mode.

7. 发明授权

US5359709A Apparatus and method for providing multiple operating configurations in data circuit terminating equipment 失效
标题翻译：在数据电路终端设备中提供多种操作配置的装置和方法
公开(公告)号：US5359709A
公开(公告)日：1994-10-25
申请号：US826504
申请日：1992-01-27
申请人： Alain Blanc , Sylvie Gohl-Roux , Gottfried Ungerboeck
发明人： Alain Blanc , Sylvie Gohl-Roux , Gottfried Ungerboeck
IPC分类号： H04L5/00 , H04L27/00 , H04L29/06 , H04L29/10 , G06F13/42
CPC分类号： H04L29/06 , H04L27/00
摘要： Multiple operating configurations in data circuit terminating equipment (DCE) are enabled through multiple queues stored in a random access memory and which are loaded with bits and characters coming either from data terminating equipment (DTE) or the telecommunications line. The DSP processor stores bits provided by a transmit circuit in a first queue, determines characters from the bits stored in the first queue based on a first transmission protocol and stores the characters in a second queue. A third queue is used by a control processor to store characters to be transmitted to a remote DCE. The DSP processor determines bits to be transmitted from the characters stored in a third queue based on a second transmission protocol, and stores those bits in a fourth queue. When the DCE is operating in a synchronous mode, the DSP processor determines PCM words for transmission based on the contents of the second queue and stores them in a fifth queue for transmission. Similarly, when the DCE switches to an asynchronous mode, the DSP processor determines PCM words based on the contents of the fourth queue and stores them in the fifth queue for transmission. A similar queue arrangement is provided for the receive circuitry of the DCE.
摘要翻译：数据电路终端设备（DCE）中的多种操作配置通过存储在随机存取存储器中的多个队列启用，并且装载有来自数据终端设备（DTE）或电信线路的位和字符。 DSP处理器将由发送电路提供的位在第一队列中存储，基于第一传输协议从存储在第一队列中的比特确定字符，并将该字符存储在第二队列中。控制处理器使用第三个队列来存储要发送到远程DCE的字符。 DSP处理器基于第二传输协议确定从存储在第三队列中的字符发送的比特，并将这些比特存储在第四队列中。当DCE工作在同步模式时，DSP处理器根据第二个队列的内容来确定用于传输的PCM字，并将其存储在第五个队列中进行传输。类似地，当DCE切换到异步模式时，DSP处理器基于第四队列的内容来确定PCM字，并将它们存储在第五队列中以进行传输。为DCE的接收电路提供了类似的队列布置。

8. 发明授权

US4918139A Aqueous dispersions of thermally cross-linkable polymers based on alkyl (meth)acrylate, the process for their preparation and their use in particular as binders and/or impregnation agents 失效
标题翻译：基于（甲基）丙烯酸烷基酯的可热交联聚合物的水分散体，其制备方法及其特别用作粘合剂和/或浸渍剂
公开(公告)号：US4918139A
公开(公告)日：1990-04-17
申请号：US332136
申请日：1989-04-03
申请人： Fernand Cuirassier , Didier Wilheim , Alain Blanc
发明人： Fernand Cuirassier , Didier Wilheim , Alain Blanc
IPC分类号： C08L33/06 , C08F2/22 , C08F8/28 , C08F20/52 , C08F220/06 , C08F220/10 , C08F220/12 , C08F220/18 , C08F220/58 , C08L33/04 , D06M15/263 , D06M15/285 , D21H19/44
CPC分类号： C08F220/12 , C08F8/28 , C08F2800/20 , C08F2810/20
摘要： These aqueous dispersions contain a copolymerizate containing 90 to 99% by weight of repeating units resulting from the polymerization of a mixture of monomers (a) based on 0.1 to 10% by weight of alpha,beta-ethylenic mono- and/or di-carboxylic C.sub.3 -C.sub.5 acid and/or their amides, 0 to 10% by weight of styrene and/or acrylonitrile, the remainder of the esters of (meth)acrylic acid with C.sub.1 -C.sub.12 alkanols; and 10 to 1% by weight of repeating units of general formula (I) ##STR1## where R=H or --CH.sub.3, R.sub.1 =H or C.sub.1 -C.sub.4 alkyl and R.sub.2 and R.sub.3 =C.sub.1 -C.sub.8 alkyl or a --CH.sub.2 --CR.sub.4 R.sub.5 --(CH.sub.2).sub.n --group in which n=0 or 1 and R.sub.4 and R.sub.5 =H or --CH.sub.3.
摘要翻译：这些水性分散体含有共聚合物，其含有90至99重量％的由单体混合物（a）聚合得到的重复单元，基于0.1至10重量％的α，β-烯属单 - 和/或二 - 羧酸 C3-C5酸和/或它们的酰胺，0至10重量％的苯乙烯和/或丙烯腈，其余的（甲基）丙烯酸与C 1 -C 12链烷醇的酯; 和10至1重量％的通式（I）的重复单元其中R = H或-CH 3，R 1 = H或C 1 -C 4烷基，R 2和R 3 = C 1 -C 8烷基或 - CH2-CR4R5-（CH2）n-基，其中n = 0或1，R4和R5 = H或-CH3。

9. 发明授权

US07769003B2 Data packet switch and method of operating same 失效
标题翻译：数据包交换机和操作方法相同
公开(公告)号：US07769003B2
公开(公告)日：2010-08-03
申请号：US11852661
申请日：2007-09-10
申请人： Rene Glaise , Alain Blanc , Francois Le Maut , Michel Poret
发明人： Rene Glaise , Alain Blanc , Francois Le Maut , Michel Poret
IPC分类号： H04L12/50 , H04Q11/00 , H04L12/28 , H04L12/56
CPC分类号： H04L49/15 , H04L49/103 , H04L49/1523 , H04L49/201 , H04L49/253 , H04L49/90
摘要： A high speed data packet switch comprising input and output ports and a switch fabric to link each input port to each output port wherein each connection between input and output ports comprises a dynamic buffer memory for storing at least one data packet for a minimum specified storing time is disclosed. When a data packet is received through an input port, it is written in all individual dynamic memory buffers connected to this input port so as to have a copy of the incoming data packet ready to go through any output port to support unicast, multicast and broadcast traffic. Given the architecture of the data packet switch and its control algorithm, dynamic memory buffers neither need to be refreshed nor their contents have to be restored after reading.
摘要翻译：包括输入和输出端口的高速数据分组交换机以及将每个输入端口链接到每个输出端口的交换结构，其中输入和输出端口之间的每个连接包括动态缓冲存储器，用于存储至少一个数据分组用于最小指定的存储时间被披露。当通过输入端口接收到数据包时，它被写入连接到该输入端口的所有单独的动态存储器缓冲器中，以便具有输入数据包的副本准备通过任何输出端口来支持单播，多播和广播交通。给定数据包交换机的架构及其控制算法，动态内存缓冲区既不需要刷新，也不需要在读取后恢复其内容。

10. 发明授权

US07706394B2 System and method for collapsing VOQ's of a packet switch fabric 有权
标题翻译：用于折叠分组交换结构的VOQ的系统和方法
公开(公告)号：US07706394B2
公开(公告)日：2010-04-27
申请号：US10894582
申请日：2004-07-20
申请人： Alain Blanc , Rene Glaise , Francois Le Maut , Michel Poret
发明人： Alain Blanc , Rene Glaise , Francois Le Maut , Michel Poret
IPC分类号： H04L12/28 , H04L12/54
CPC分类号： H04L47/10 , H04L47/263 , H04L47/30 , H04L49/103 , H04L49/3027 , H04L49/3045
摘要： A system and a method to avoid packet traffic congestion in a shared-memory switch core, while dramatically reducing the amount of shared memory in the switch core and the associated egress buffers, is disclosed. According to the invention, the virtual output queuing (VOQ) of all ingress adapters of a packet switch fabric are collapsed into its central switch core to allow an efficient flow control. The transmission of packets from an ingress buffer to the switch core is subject to a mechanism of request/acknowledgment. Therefore, a packet is transmitted from a virtual output queue to the shared-memory switch core only if the switch core can actually forward it to the corresponding egress buffer. A token based mechanism allows the switch core to determine the egress buffer's level of occupation. Therefore, since the switch core knows the states of the input and output adapters, it is able to optimize packet switching and to avoid packet congestion. Furthermore, since a packet is admitted in the switch core only if it can be transmitted to the corresponding egress buffer, the shared memory is reduced.
摘要翻译：公开了一种在共享存储器交换机核心中避免分组业务拥塞的系统和方法，同时显着地减少了交换机核心和相关联的出口缓冲器中的共享存储器的数量。根据本发明，分组交换结构的所有入口适配器的虚拟输出排队（VOQ）被折叠到其中央交换机核心中以允许有效的流控制。数据包从入口缓冲区传输到交换机核心受到请求/确认的机制。因此，只有当交换机核心才能将其转发到相应的出口缓冲区时，才将数据包从虚拟输出队列传输到共享存储交换机内核。基于令牌的机制允许交换机核心确定出口缓冲区的占用水平。因此，由于交换机核心知道输入和输出适配器的状态，因此能够优化分组交换并避免分组拥塞。此外，由于分组只有在可以发送到对应的出口缓冲器的情况下才允许在交换机核心中，所以共享存储器被减少。

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