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1. 发明授权

US06548413B1 Method to reduce microloading in metal etching 失效
标题翻译：在金属蚀刻中减少微载荷的方法
公开(公告)号：US06548413B1
公开(公告)日：2003-04-15
申请号：US09048208
申请日：1998-03-26
申请人： Paul Kwok Keung Ho , Thomas Schulue , Raymond Joy , Wai Lok Lee , Ramasamy Chockalingam , Ba Tuan Pham , Premachandran Vayalakkara
发明人： Paul Kwok Keung Ho , Thomas Schulue , Raymond Joy , Wai Lok Lee , Ramasamy Chockalingam , Ba Tuan Pham , Premachandran Vayalakkara
IPC分类号： H01L21302
CPC分类号： H01L21/32136
摘要： A new method of etching metal lines with reduced microloading effect is described. Semiconductor device structures are provided in and on a semiconductor substrate and covered with an insulating layer. A barrier metal layer is deposited overlying the insulating layer and a metal layer is deposited overlying the barrier metal layer. The metal layer is covered with a photoresist mask wherein there are both wide spaces and narrow spaces between portions of the photoresist mask. The metal layer is etched away where it is not covered by the photoresist mask wherein the barrier metal layer is reached within the wide spaces while some of the metal layer remains within the narrow spaces. The metal layer remaining within the narrow spaces is selectively etched away. Thereafter, the barrier metal layer not covered by the photoresist mask is etched away wherein the insulating layer is reached within the wide spaces while some of the barrier metal layer remains within the narrow spaces. The barrier metal layer remaining within the narrow spaces is selectively etched away. Thereafter, the insulating layer not covered by the photoresist mask is overetched to complete the metal lines without microloading in the fabrication of an integrated circuit.
摘要翻译：描述了一种蚀刻具有减少的微加载效应的金属线的新方法。半导体器件结构设置在半导体衬底中并在半导体衬底上并被绝缘层覆盖。沉积覆盖在绝缘层上的阻挡金属层，并且沉积覆盖阻挡金属层的金属层。金属层被光致抗蚀剂掩模覆盖，其中在光致抗蚀剂掩模的部分之间存在宽的空间和狭窄的空间。金属层被蚀刻掉，其中它不被光致抗蚀剂掩模覆盖，其中阻挡金属层在宽空间内到达，而一些金属层保留在狭窄的空间内。残留在狭窄空间内的金属层被有选择地蚀刻掉。此后，蚀刻掉未被光致抗蚀剂掩模覆盖的阻挡金属层，其中绝缘层在宽空间内到达，而一些阻挡金属层保留在狭窄的空间内。残留在狭窄空间内的阻挡金属层被有选择地蚀刻掉。此后，在制造集成电路的过程中，将未被光致抗蚀剂掩模覆盖的绝缘层进行过蚀刻以完成金属线而无需微加载。

2. 发明申请

US20080105653A1 Apparatus and methods for Cleaning and Drying of wafers 有权
标题翻译：用于清洁和干燥晶片的装置和方法
公开(公告)号：US20080105653A1
公开(公告)日：2008-05-08
申请号：US11556696
申请日：2006-11-05
申请人： Boon Meng Seah , Bei Chao Zhang , Raymond Joy , Shao Beng Law , John Sudijono , Liang Choo Hsia
发明人： Boon Meng Seah , Bei Chao Zhang , Raymond Joy , Shao Beng Law , John Sudijono , Liang Choo Hsia
IPC分类号： B05B13/04 , B05B1/14 , B08B3/08 , B44C1/22
CPC分类号： H01L21/67028 , H01L21/67051 , H01L21/6708
摘要： An first example method and apparatus for etching and cleaning a substrate comprises device with a first manifold and a second manifold. The first manifold has a plurality of nozzles for dispensing chemicals onto the substrate. The second manifold is attached to a vacuum source and/or a dry air/gas source. A second example embodiment is a wafer cleaning device and method that uses a manifold with capillary jet nozzles and a liquid capillary jet stream to clean substrates.
摘要翻译：用于蚀刻和清洁衬底的第一示例性方法和装置包括具有第一歧管和第二歧管的装置。第一歧管具有用于将化学品分配到基底上的多个喷嘴。第二歧管连接到真空源和/或干燥空气/气体源。第二示例性实施例是晶片清洁装置和方法，其使用具有毛细管喷嘴和液体毛细管喷流的歧管来清洁基底。

3. 发明授权

US08177993B2 Apparatus and methods for cleaning and drying of wafers 有权
标题翻译：用于清洗和干燥晶片的装置和方法
公开(公告)号：US08177993B2
公开(公告)日：2012-05-15
申请号：US11556696
申请日：2006-11-05
申请人： Boon Meng Seah , Bei Chao Zhang , Raymond Joy , Shao Beng Law , John Sudijono , Liang Choo Hsia
发明人： Boon Meng Seah , Bei Chao Zhang , Raymond Joy , Shao Beng Law , John Sudijono , Liang Choo Hsia
IPC分类号： B44C1/22
CPC分类号： H01L21/67028 , H01L21/67051 , H01L21/6708
摘要： An first example method and apparatus for etching and cleaning a substrate comprises device with a first manifold and a second manifold. The first manifold has a plurality of nozzles for dispensing chemicals onto the substrate. The second manifold is attached to a vacuum source and/or a dry air/gas source. A second example embodiment is a wafer cleaning device and method that uses a manifold with capillary jet nozzles and a liquid capillary jet stream to clean substrates.
摘要翻译：用于蚀刻和清洁衬底的第一示例性方法和装置包括具有第一歧管和第二歧管的装置。第一歧管具有用于将化学品分配到基底上的多个喷嘴。第二歧管连接到真空源和/或干燥空气/气体源。第二示例性实施例是晶片清洁装置和方法，其使用具有毛细管喷嘴和液体毛细管喷流的歧管来清洁基底。

4. 发明申请

US20070264820A1 Protruded contact and insertion of inter-layer-dielectric material to match damascene hardmask to improve undercut for low-k interconnects 有权
标题翻译：突出接触和插入层间介电材料以匹配镶嵌硬掩模，以改善低k互连的底切
公开(公告)号：US20070264820A1
公开(公告)日：2007-11-15
申请号：US11434318
申请日：2006-05-15
申请人： Wuping Liu , Raymond Joy , Beichao Zhang , Liang Hsia , Boon Seah , Shyam Pal
发明人： Wuping Liu , Raymond Joy , Beichao Zhang , Liang Hsia , Boon Seah , Shyam Pal
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/02063 , H01L21/31111 , H01L21/31116 , H01L21/31133 , H01L21/31138 , H01L21/31144 , H01L21/76814
摘要： An embodiment of the invention shows a process to form a damascene opening preferably without hardmask overhang or dielectric layer undercut/void. The low-k dielectric material can be sandwiched in two hardmask films to form the dielectric film through which an interconnect opening is etched. A first example embodiment comprises the following. We form a lower interconnect and an insulating layer over a semiconductor structure. We form a first hardmask a dielectric layer, and a second hardmask layer, over the lower interconnect and insulating layer. We etch a first interconnect opening in the first hardmask, the dielectric layer and the second hardmask layer. Lastly, we form an interconnect in the first interconnect opening.
摘要翻译：本发明的一个实施例示出了一种形成镶嵌开口的方法，优选地不具有硬掩模悬垂或电介质层底切/空隙。低k电介质材料可以被夹在两个硬掩模膜中以形成蚀刻互连开口的电介质膜。第一示例性实施例包括以下。我们在半导体结构上形成下互连和绝缘层。我们在下互连和绝缘层上形成第一硬掩模介电层和第二硬掩模层。我们蚀刻第一硬掩模，电介质层和第二硬掩模层中的第一互连开口。最后，我们在第一个互连开口中形成互连。

5. 发明申请

US20060094230A1 Multiple Layer Resist Scheme Implementing Etch Recipe Particular to Each Layer 有权
标题翻译：多层抗扰性方案实现每层专用的蚀刻配方
公开(公告)号：US20060094230A1
公开(公告)日：2006-05-04
申请号：US10904323
申请日：2004-11-04
申请人： Nicholas Fuller , Timothy Dalton , Raymond Joy , Yi-hsiung Lin , Chun Low
发明人： Nicholas Fuller , Timothy Dalton , Raymond Joy , Yi-hsiung Lin , Chun Low
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/0332 , H01L21/31138 , H01L21/31144
摘要： Methods of forming a metal line and/or via critical dimension (CD) in a single or dual damascene process on a semiconductor substrate, and the resist scheme implemented, are disclosed. The method includes forming a multiple layer resist scheme including a first planarizing layer of a first type material over the substrate, a second dielectric layer of a second type material over the planarizing layer, and a third photoresist layer of a third type material over the dielectric layer. The types of material alternate between organic and inorganic material. The third layer is patterned for the metal line and/or via CD. Sequential etching to form the metal line and/or via critical dimension using a tailored etch recipe particular to each of the first photoresist layer, the second dielectric layer and the third planarizing layer as each layer is exposed is then used. Accurate CD formation and adequate resist budget are provided.
摘要翻译：公开了在半导体衬底上的单镶嵌或双镶嵌工艺中形成金属线和/或通过临界尺寸（CD）的方法和实现的抗蚀剂方案。该方法包括形成多层抗蚀剂方案，该多层抗蚀剂方案包括在该衬底上的第一类型材料的第一平坦化层，平坦化层上的第二类型材料的第二电介质层，以及在电介质上的第三类型材料的第三光致抗蚀剂层层。有机材料和无机材料之间的材料类型是交替的。第三层被图案化为金属线和/或经由CD。然后使用对每一个被暴露的第一光致抗蚀剂层，第二介电层和第三平坦化层中的每一个特定的定制蚀刻配方进行顺序蚀刻以形成金属线和/或通过临界尺寸。提供准确的CD形成和足够的抗蚀剂预算。

6. 发明申请

US20140004677A1 High-k Seal for Protection of Replacement Gates 审中-公开
标题翻译：用于保护更换闸门的高k密封
公开(公告)号：US20140004677A1
公开(公告)日：2014-01-02
申请号：US13537140
申请日：2012-06-29
申请人： Ying Li , Raymond Joy , Yong Meng Lee
发明人： Ying Li , Raymond Joy , Yong Meng Lee
IPC分类号： H01L21/336 , H01L21/20
CPC分类号： H01L29/66636 , H01L21/823814 , H01L29/66545 , H01L29/66606 , H01L29/78
摘要： Embodiments of the invention include methods of protecting sacrificial gates during raised/source drain and replacement metal gate processes. Embodiments include steps of forming sacrificial gates on a semiconductor substrate, protecting the sacrificial gates with gate seals, forming source/drains near the sacrificial gates without substantially growing semiconductor material on the sacrificial gates, removing the gate seals, and replacing the sacrificial gates with metal gates. In some embodiments, the gate seals are made of a high-k material.
摘要翻译：本发明的实施例包括在升高/源极漏极和替换金属栅极工艺期间保护牺牲栅极的方法。实施例包括在半导体衬底上形成牺牲栅极的步骤，用栅极密封保护牺牲栅极，在牺牲栅极附近形成源极/漏极，而不在牺牲栅极上基本上生长半导体材料，移除栅极密封件，并用金属替换牺牲栅极大门在一些实施例中，门密封由高k材料制成。

7. 发明授权

US07601607B2 Protruded contact and insertion of inter-layer-dielectric material to match damascene hardmask to improve undercut for low-k interconnects 有权
标题翻译：突出接触和插入层间介电材料以匹配镶嵌硬掩模，以改善低k互连的底切
公开(公告)号：US07601607B2
公开(公告)日：2009-10-13
申请号：US11434318
申请日：2006-05-15
申请人： Wuping Liu , Raymond Joy , Beichao Zhang , Liang Choo Hsia , Boon Meng Seah , Shyam Pal
发明人： Wuping Liu , Raymond Joy , Beichao Zhang , Liang Choo Hsia , Boon Meng Seah , Shyam Pal
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/02063 , H01L21/31111 , H01L21/31116 , H01L21/31133 , H01L21/31138 , H01L21/31144 , H01L21/76814
摘要： An embodiment of the invention shows a process to form a damascene opening preferably without hardmask overhang or dielectric layer undercut/void. The low-k dielectric material can be sandwiched in two hardmask films to form the dielectric film through which an interconnect opening is etched. A first example embodiment comprises the following. We form a lower interconnect and an insulating layer over a semiconductor structure. We form a first hardmask a dielectric layer, and a second hardmask layer, over the lower interconnect and insulating layer. We etch a first interconnect opening in the first hardmask, the dielectric layer and the second hardmask layer. Lastly, we form an interconnect in the first interconnect opening.
摘要翻译：本发明的一个实施例示出了一种形成镶嵌开口的方法，优选地不具有硬掩模悬垂或电介质层底切/空隙。低k电介质材料可以被夹在两个硬掩模膜中以形成蚀刻互连开口的电介质膜。第一示例性实施例包括以下。我们在半导体结构上形成下互连和绝缘层。我们在下互连和绝缘层上形成第一硬掩模介电层和第二硬掩模层。我们蚀刻第一硬掩模，电介质层和第二硬掩模层中的第一互连开口。最后，我们在第一个互连开口中形成互连。

8. 发明授权

US07352064B2 Multiple layer resist scheme implementing etch recipe particular to each layer 有权
标题翻译：多层抗蚀剂方案实现每层特有的蚀刻配方
公开(公告)号：US07352064B2
公开(公告)日：2008-04-01
申请号：US10904323
申请日：2004-11-04
申请人： Nicholas C. M. Fuller , Timothy J. Dalton , Raymond Joy , Yi-hsiung Lin , Chun Hui Low
发明人： Nicholas C. M. Fuller , Timothy J. Dalton , Raymond Joy , Yi-hsiung Lin , Chun Hui Low
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L21/4763
CPC分类号： H01L21/76802 , H01L21/0332 , H01L21/31138 , H01L21/31144
摘要： Methods of forming a metal line and/or via critical dimension (CD) in a single or dual damascene process on a semiconductor substrate, and the resist scheme implemented, are disclosed. The method includes forming a multiple layer resist scheme including a first planarizing layer of a first type material over the substrate, a second dielectric layer of a second type material over the planarizing layer, and a third photoresist layer of a third type material over the dielectric layer. The types of material alternate between organic and inorganic material. The third layer is patterned for the metal line and/or via CD. Sequential etching to form the metal line and/or via critical dimension using a tailored etch recipe particular to each of the first photoresist layer, the second dielectric layer and the third planarizing layer as each layer is exposed is then used. Accurate CD formation and adequate resist budget are provided.
摘要翻译：公开了在半导体衬底上的单镶嵌或双镶嵌工艺中形成金属线和/或通过临界尺寸（CD）的方法和实现的抗蚀剂方案。该方法包括形成多层抗蚀剂方案，该多层抗蚀剂方案包括在该衬底上的第一类型材料的第一平坦化层，平坦化层上的第二类型材料的第二电介质层，以及在电介质上的第三类型材料的第三光致抗蚀剂层层。有机材料和无机材料之间的材料类型是交替的。第三层被图案化为金属线和/或经由CD。然后使用对每一个被暴露的第一光致抗蚀剂层，第二介电层和第三平坦化层中的每一个特定的定制蚀刻配方进行顺序蚀刻以形成金属线和/或通过临界尺寸。提供准确的CD形成和足够的抗蚀剂预算。

9. 发明授权

US06271115B1 Post metal etch photoresist strip method 失效
标题翻译：后金属蚀刻光刻胶剥离法
公开(公告)号：US06271115B1
公开(公告)日：2001-08-07
申请号：US09604065
申请日：2000-06-26
申请人： Wen Jun Liu , Simon Chooi , Mei Sheng Zhou , Raymond Joy
发明人： Wen Jun Liu , Simon Chooi , Mei Sheng Zhou , Raymond Joy
IPC分类号： H01L214763
CPC分类号： H01L21/02071
摘要： An improved method for removing a photoresist mask from an etched aluminum pattern after etching the pattern in a chlorine containing plasma has been developed. The method is a five step process, in which the first step is in a microwave generated plasma containing O2 and H2O; the second step is in a microwave generated plasma containing O2 and N2; the third step is in a microwave generated plasma containing H2O; the fourth step is in a microwave generated plasma containing O2 and N2; and the fifth step is in a microwave generated plasma containing H2O. The first step which initiates removal of photoresist while simultaneously beginning the passivation process causes residue-free removal of photoresist following etching of aluminum or aluminum-copper layers in chlorine bearing etchants.
摘要翻译：已经开发了一种用于在含氯等离子体中蚀刻图案之后从蚀刻铝图案去除光致抗蚀剂掩模的改进方法。该方法是五步法，其中第一步是在微波产生的含有O 2和H 2 O的等离子体中; 第二步是在微波产生的含有O2和N2的等离子体中; 第三步是在微波产生的含有H 2 O的等离子体中; 第四步是在微波产生的含有O2和N2的等离子体中; 并且第五步是在含有H 2 O的微波产生的等离子体中。在同时开始钝化过程的同时开始除去光致抗蚀剂的第一步骤在蚀刻含氯蚀刻剂中的铝或铝 - 铜层之后会导致残留物去除光致抗蚀剂。

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