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1. 发明授权

US6011619A Semiconductor wafer optical scanning system and method using swath-area defect limitation 失效
标题翻译：半导体晶圆光学扫描系统和方法使用区域缺陷限制
公开(公告)号：US6011619A
公开(公告)日：2000-01-04
申请号：US987736
申请日：1997-12-09
申请人： Paul J. Steffan , Bryan Tracy , Ming Chun Chen
发明人： Paul J. Steffan , Bryan Tracy , Ming Chun Chen
IPC分类号： G01N21/956 , G01N21/88
CPC分类号： G01N21/95607
摘要： A semiconductor wafer optical scanning system and method for determining defects on a semiconductor wafer is disclosed. The method for determining wafer defects is based on maximum allowable defects on a swath basis, rather than maximum allowable defects on a wafer basis. The method step include determining the scanned area of an individual swath that is based on a recipe set-up, consistent with the capability of the optical scanning equipment being used and the particular semiconductor wafer being tested for defects. The predetermined swath area is supplied and stored in the optical scanning system along with the maximum allowable defect density determined by the user. By using the predetermined maximum allowable defects for a swath as a limit, defect analysis may be performed on the entire wafer. The optical scanning system would stop acquiring defects for the current swath being analyzed whenever the defect limit is reached, or until the swath defect analysis has been completed. The optical scanning would proceed to the next swath determining its defect and continuing in such a manner until the wafer is completely scanned.
摘要翻译：公开了一种用于确定半导体晶片上的缺陷的半导体晶片光学扫描系统和方法。用于确定晶片缺陷的方法基于条带上的最大允许缺陷，而不是基于晶片的最大允许缺陷。方法步骤包括根据正在使用的光学扫描设备的能力和正在测试缺陷的特定半导体晶片的能力，确定基于配方设置的单个条带的扫描区域。预定的条带区域与由用户确定的最大允许缺陷密度一起提供并存储在光学扫描系统中。通过将条纹的预定最大允许缺陷用作极限，可以在整个晶片上进行缺陷分析。光学扫描系统将停止获取当达到缺陷限制时所分析的当前条带的缺陷，或直到条带缺陷分析完成。光学扫描将进行到下一个条纹以确定其缺陷并以这种方式继续，直到晶片被完全扫描。

2. 发明申请

US20110117655A1 METHODS AND COMPOSITIONS FOR GENETICALLY MANIPULATING CLOSTRIDIA AND RELATED BACTERIA WITH HOMOLOGOUS RECOMBINATION ASSOCIATED PROTEINS 审中-公开
标题翻译：用于遗传重组相关蛋白质的遗传操作性和相关细菌的方法和组合物
公开(公告)号：US20110117655A1
公开(公告)日：2011-05-19
申请号：US12948887
申请日：2010-11-18
申请人： Bryan Tracy , Eleftherios Papoutsakis
发明人： Bryan Tracy , Eleftherios Papoutsakis
IPC分类号： C12N15/74 , C12N15/00 , C12N1/21
CPC分类号： C12N15/74 , C07K14/33 , C12N15/1082
摘要： Methods for effecting homologous recombination in a bacterium of the Clostridia family are described. These methods provide enhanced capability to genetically modify clostridia.
摘要翻译：描述了在梭菌家族细菌中进行同源重组的方法。这些方法提供增强的遗传修饰梭菌的能力。

3. 发明授权

US5639691A Copper pellet for reducing electromigration effects associated with a conductive via in a semiconductor device 失效
公开(公告)号：US5639691A
公开(公告)日：1997-06-17
申请号：US590781
申请日：1996-01-24
申请人： Richard K. Klein , Darrell M. Erb , Steven Avanzino , Robin Cheung , Scott Luning , Bryan Tracy , Subhash Gupta , Ming-Ren Lin
发明人： Richard K. Klein , Darrell M. Erb , Steven Avanzino , Robin Cheung , Scott Luning , Bryan Tracy , Subhash Gupta , Ming-Ren Lin
IPC分类号： H01L21/768 , H01L21/283
CPC分类号： H01L21/76805 , H01L21/76877 , Y10S257/915 , Y10S438/927
摘要： A multilayer semiconductor structure includes a conductive via. The conductive via includes a pellet of metal having a high resistance to electromigration. The pellet is made from a conformal layer of copper or gold deposited over the via to form a copper or gold reservoir or contact located in the via. A barrier layer is provided between the reservoir and an insulating layer to prevent the pellet from diffusing into the insulating layer. The pellet can be formed by selective deposition or by etching a conformal layer. The conformal layer can be deposited by sputtering, collimated sputtering, chemical vapor deposition (CVD), dipping, evaporating, or by other means. The barrier layer and pellet may be etched by anisotropic dry etching, plasma-assisted etching, or other layer removal techniques.

4. 发明授权

US5882738A Apparatus and method to improve electromigration performance by use of amorphous barrier layer 失效
标题翻译：通过使用无定形阻挡层改善电迁移性能的装置和方法
公开(公告)号：US5882738A
公开(公告)日：1999-03-16
申请号：US994356
申请日：1997-12-19
申请人： Richard C. Blish, II , Bryan Tracy
发明人： Richard C. Blish, II , Bryan Tracy
IPC分类号： C23C14/48 , H01L21/768 , C23C14/04
CPC分类号： H01L21/76859 , C23C14/48 , H01L21/76841 , Y10T428/12486 , Y10T428/12528 , Y10T428/12639 , Y10T428/12674 , Y10T428/12681
摘要： An ion implant process is disclosed for forming an amorphous structure in a semiconductor metallization barrier layer, which barrier may be a pure metal barrier, such as titanium, tantalum, tungsten, or metal compound barrier, such as titanium nitride, or titanium-tungsten. The implant is preferably an ion of the barrier metal being used, which is implanted such that an amorphous (texture-less non-crystalline) layer is produced. Other implant species, such as nitrogen or noble gases, such as neon or argon may also be used. Subsequent deposition of the interconnect metallization (typically Al or Cu) results in an interconnect metal structure having a high degree of texture which is characterized by a very narrow distribution of crystallographic orientations in the Al or Cu film. The highly textured Al or Cu metallization results in optimizing the interconnect metal for maximum electromigration performance. The implant energy is chosen such that the tail of the Gaussian distribution of ion's stopping distances extends above the top of the barrier metal film. The ion implantation forms a non-crystalline metal structure in the metal barrier film such that there is no crystalline metal to act as a "seed" for nucleation during the metallization deposition and subsequent processing. Thus, the final interconnect metallization texture (Al or Cu) will not be governed by the texture of the underlying metal barrier layer which results in an optimized interconnect metal structure with maximum electromigration performance characteristics.
摘要翻译：公开了用于在半导体金属化阻挡层中形成非晶结构的离子注入工艺，该阻挡层可以是纯金属屏障，例如钛，钽，钨或金属化合物屏障，例如氮化钛或钛 - 钨。植入物优选是所使用的阻挡金属的离子，其被注入使得产生无定形（无纹理的非结晶）层。也可以使用其它植入物种，例如氮气或惰性气体，例如氖或氩。互连金属化（通常为Al或Cu）的后续沉积导致具有高度纹理的互连金属结构，其特征在于Al或Cu膜中晶体取向的非常窄的分布。高度纹理的Al或Cu金属化导致优化互连金属以获得最大的电迁移性能。选择植入能量使得离子的停止距离的高斯分布的尾部延伸到阻挡金属膜的顶部之上。离子注入在金属阻挡膜中形成非结晶金属结构，使得在金属化沉积和后续加工期间不存在用于成核的“晶种”的结晶金属。因此，最终的互连金属化织构（Al或Cu）将不受底层金属阻挡层的结构的约束，这导致具有最大电迁移性能特性的优化的互连金属结构。

5. 发明授权

US5864199A Electron beam emitting tungsten filament 失效
标题翻译：电子束发射钨丝
公开(公告)号：US5864199A
公开(公告)日：1999-01-26
申请号：US912199
申请日：1997-08-18
申请人： Roger L. Alvis , Janice Gray , Bryan Tracy
发明人： Roger L. Alvis , Janice Gray , Bryan Tracy
IPC分类号： H01J1/304 , H01J9/02 , H01J27/00
CPC分类号： H01J9/025 , H01J1/304
摘要： Electron beam emitting filaments having a tip with a radius of curvature less than about 50 .ANG. are produced using focused ion beam milling. In one embodiment, platinum is deposited on a tungsten loop electron beam filament and sharpened using focused ion beam milling to a radius of curvature less than about 50 .ANG..
摘要翻译：使用聚焦离子束研磨产生具有小于约50的曲率半径的尖端的电子束发射细丝。在一个实施例中，将铂沉积在钨环电子束灯丝上，并使用聚焦离子束研磨将其锐化至小于约50安培的曲率半径。

6. 发明授权

US06534869B2 Method for reducing stress-induced voids for 0.25 &mgr;m micron and smaller semiconductor chip technology by annealing interconnect lines prior to ILD deposition and semiconductor chip made thereby 失效
标题翻译：用于通过在ILD沉积之前退火互连线并由此制造的半导体芯片来减少0.25微米和更小的半导体芯片技术的应力诱导空隙的方法
公开(公告)号：US06534869B2
公开(公告)日：2003-03-18
申请号：US09128057
申请日：1998-07-29
申请人： Bryan Tracy , Paul R. Besser , Minh Van Ngo
发明人： Bryan Tracy , Paul R. Besser , Minh Van Ngo
IPC分类号： H01L2352
CPC分类号： H01L21/76858 , H01L21/76841 , H01L21/7685 , H01L21/76885 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A method for making 0.25-micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms first, which subsequently volumetrically contracts, thereby forming a titanium aluminide compound, with the contraction being absorbed by the aluminum. Because the alloy is reacted to form the metal compound prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation in the interconnect lines is reduced.
摘要翻译：制造0.25微米半导体芯片的方法包括在线之间沉积层间电介质（ILD）之前退火金属互连线。在退火过程中，首先形成铝和钛的合金，其随后体积收缩，由此形成铝化铝化合物，其中收缩被铝吸收。因为在ILD沉积之前合金反应形成金属化合物，所以当它尝试吸收合金的收缩时，铝不受ILD的约束。因此，互连线中不希望的空隙形成的可能性降低。

7. 发明授权

US5770519A Copper reservoir for reducing electromigration effects associated with a conductive via in a semiconductor device 失效
标题翻译：用于减少与半导体器件中的导电通孔相关的电迁移效应的铜储存器
公开(公告)号：US5770519A
公开(公告)日：1998-06-23
申请号：US464305
申请日：1995-06-05
申请人： Richard K. Klein , Darrell Erb , Steven Avanzino , Robin Cheung , Scott Luning , Bryan Tracy , Subhash Gupta , Ming-Ren Lin
发明人： Richard K. Klein , Darrell Erb , Steven Avanzino , Robin Cheung , Scott Luning , Bryan Tracy , Subhash Gupta , Ming-Ren Lin
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/4763 , H01L21/44
CPC分类号： H01L21/76831 , H01L21/76805 , H01L21/76843 , H01L21/76844 , H01L21/76877 , H01L23/5226 , H01L23/53223 , H01L2924/0002
摘要： A multilayer semiconductor structure includes a conductive via. The conductive via includes a reservoir of metal having a high resistance to electromigration. The reservoir is made from a conformal layer of copper, or gold deposited over the via to form a copper, or gold plug located in the via. A barrier layer is provided between the reservoir and an insulating layer to prevent the reservoir from diffusing into the insulating layer. The barrier layer and reservoir may be deposited by sputtering, collimated sputtering, chemical vapor deposition (CVD), dipping, evaporating, or by other means. The barrier layer and reservoir may be etched by anisotropic dry etching, plasma-assisted etching, or other layer removal techniques.
摘要翻译：多层半导体结构包括导电通孔。导电通孔包括具有高抗电迁移性的金属储存器。储存器由铜的共形层或沉积在通孔上的金形成，以形成位于通孔中的铜或金塞。在储存器和绝缘层之间设置阻挡层，以防止储存器扩散到绝缘层中。可以通过溅射，准直溅射，化学气相沉积（CVD），浸渍，蒸发或其它方式沉积阻挡层和储层。可以通过各向异性干蚀刻，等离子体辅助蚀刻或其它层去除技术来蚀刻阻挡层和储存器。

8. 发明授权

US5727978A Method of forming electron beam emitting tungsten filament 失效
标题翻译：形成电子束发射钨丝的方法
公开(公告)号：US5727978A
公开(公告)日：1998-03-17
申请号：US574480
申请日：1995-12-19
申请人： Roger L. Alvis , Janice Gray , Bryan Tracy
发明人： Roger L. Alvis , Janice Gray , Bryan Tracy
IPC分类号： H01J1/304 , H01J9/02
CPC分类号： H01J9/025 , H01J1/304
摘要： Electron beam emitting filaments having a tip with a radius of curvature less than about 50 .ANG. are produced using focused ion beam milling. In one embodiment, platinum is deposited on a tungsten loop electron beam filament and sharpened using focused ion beam milling to a radius of curvature less than about 50 .ANG..
摘要翻译：使用聚焦离子束研磨产生具有小于约50的曲率半径的尖端的电子束发射细丝。在一个实施例中，将铂沉积在钨环电子束灯丝上，并使用聚焦离子束研磨将其锐化至小于约50安培的曲率半径。

9. 发明申请

US20130203170A1 METHODS AND COMPOSITIONS FOR GENETICALLY MANIPULATING CLOSTRIDIA AND RELATED BACTERIA WITH HOMOLOGOUS RECOMBINATION ASSOCIATED PROTEINS 有权
标题翻译：用于遗传重组相关蛋白质的遗传操作性和相关细菌的方法和组合物
公开(公告)号：US20130203170A1
公开(公告)日：2013-08-08
申请号：US13826953
申请日：2013-03-14
申请人： Bryan Tracy , Eleftherios Papoutsakis
发明人： Bryan Tracy , Eleftherios Papoutsakis
IPC分类号： C12N15/74
CPC分类号： C12N15/74 , C07K14/33 , C12N15/1082
摘要： Methods for enhancing single cross-over homologous recombination in gram positive bacteria are presented. These methods provide enhanced capability to genetically modify gram positive bacteria.
摘要翻译：提出了在革兰氏阳性细菌中增强单一交叉同源重组的方法。这些方法提供了增强革兰氏阳性菌遗传修饰的能力。

10. 发明授权

US5646448A Copper pellet for reducing electromigration effects associated with a conductive via in a semiconductor device 失效
标题翻译：用于减少与半导体器件中的导电通孔相关的电迁移效应的铜芯片
公开(公告)号：US5646448A
公开(公告)日：1997-07-08
申请号：US699821
申请日：1996-08-19
申请人： Richard K. Klein , Darrell Erb , Steven Avanzino , Robin Cheung , Scott Luning , Bryan Tracy , Subhash Gupta , Ming-Ren Lin
发明人： Richard K. Klein , Darrell Erb , Steven Avanzino , Robin Cheung , Scott Luning , Bryan Tracy , Subhash Gupta , Ming-Ren Lin
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L21/76805 , H01L21/76877 , Y10S257/915 , Y10S438/927
摘要： A multilayer semiconductor structure includes a conductive via. The conductive via includes a pellet of metal having a high resistance to electromigration. The pellet is made from a conformal layer of copper or gold deposited over the via to form a copper or gold reservoir or contact located in the via. A barrier layer is provided between the reservoir and an insulating layer to prevent the pellet from diffusing into the insulating layer. The pellet can be formed by selective deposition or by etching a conformal layer. The conformal layer can be deposited by sputtering, collimated sputtering, chemical vapor deposition (CVD), dipping, evaporating, or by other means. The barrier layer and pellet may be etched by anisotropic dry etching, plasma-assisted etching, or other layer removal techniques.
摘要翻译：多层半导体结构包括导电通孔。导电通孔包括具有高抗电迁移性的金属颗粒。沉淀物由沉积在通孔上的铜或金的保形层制成，以形成位于通孔中的铜或金储存器或触点。在储存器和绝缘层之间设置阻挡层以防止颗粒扩散到绝缘层中。颗粒可以通过选择性沉积或通过蚀刻保形层形成。可以通过溅射，准直溅射，化学气相沉积（CVD），浸渍，蒸发或其它方式沉积共形层。可以通过各向异性干蚀刻，等离子体辅助蚀刻或其它层去除技术来蚀刻阻挡层和颗粒。

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