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1. 发明授权

US5107489A Switch and its protocol for making dynamic connections 失效
标题翻译：切换及其制定动态连接协议
公开(公告)号：US5107489A
公开(公告)日：1992-04-21
申请号：US429267
申请日：1989-10-30
申请人： Paul J. Brown , Joseph C. Elliott , Peter A. Franaszek , Karl H. Hoppe , Kenneth R. Lynch , Martin W. Sachs , Leon Skarshinski
发明人： Paul J. Brown , Joseph C. Elliott , Peter A. Franaszek , Karl H. Hoppe , Kenneth R. Lynch , Martin W. Sachs , Leon Skarshinski
IPC分类号： H04L12/56
CPC分类号： H04L49/253 , H04L49/101 , H04L49/254
摘要： A dynamic switch and its protocol for establishing dynamic connections in a link by the use of frames, each frame having an identification of the source of the frame, an identification of the destination of the frame for the requested connection, and link controls to maintain, initiate or terminate a connection between the source and the destination. The frames are bounded by a start of frame delimiter and an end of frame delimiter which may also act as a connect link control and a disconnect link control, respectively, and the connections are made through the dynamic switch having dynamic-switch ports. The state of a dynamic-switch port is changed dependent on its present state, the dynamic connection requested, and the direction and type of frames passing through the dynamic-switch port.

2. 发明授权

US5412653A Dynamic switch cascading system 失效
标题翻译：动态开关级联系统
公开(公告)号：US5412653A
公开(公告)日：1995-05-02
申请号：US138288
申请日：1993-10-15
申请人： Karl H. Hoppe , Laura H. McGoogan , Leon Skarshinski , Michael E. Underkoffler
发明人： Karl H. Hoppe , Laura H. McGoogan , Leon Skarshinski , Michael E. Underkoffler
IPC分类号： G06F13/00 , G06F15/173 , H04L12/56 , H04J3/14
CPC分类号： H04L49/15 , G06F15/17375 , H04L49/25
摘要： A computer interconnection system provides dynamic switch cascading with a plurality of circuit switches having circuit switch ports coupled by a dynamic connection to provide a dynamically cascadable switching network having a plurality of nodes, including end point and switch nodes. Two individual circuit switches of the network are interconnected by a cross-link group of one or more links. The system transmits frame information including a source endpoint address and a destination endpoint address, each of which can be associated with an endpoint port or a cross-link group, and forms a connection between an endpoint port or a cross-link group to make a connection between a circuit switch port corresponding to a source endpoint address and a circuit switch port corresponding to the destination endpoint. The dynamic circuit switch connections, as applicable to dynamic switch cascade operation, is compatible with the ESCON I/O Interface Architecture or to a fabric node supporting the Class 1 service defined by the Fibre Channel ANSI Standard.
摘要翻译：计算机互连系统提供与具有通过动态连接耦合的电路交换端口的多个电路交换机的动态开关级联，以提供具有包括端点和交换节点在内的多个节点的动态级联交换网络。网络的两个单独的电路交换机通过一个或多个链路的交叉链路组来互连。系统发送包括源端点地址和目的地端点地址的帧信息，每个端点地址可以与端点端口或交叉链路组相关联，并且形成端点端口或交叉链路组之间的连接，对应于源端点地址的电路交换机端口与对应于目的端点的电路交换机端口之间的连接。动态电路交换机连接，适用于动态切换级联操作，与ESCON I / O接口架构兼容，或支持由光纤通道ANSI标准定义的1类服务的结构节点。

3. 发明授权

US5272729A Clock signal latency elimination network 失效
标题翻译：时钟信号延迟消除网络
公开(公告)号：US5272729A
公开(公告)日：1993-12-21
申请号：US763510
申请日：1991-09-20
申请人： Roland Bechade , Frank D. Ferraiolo , Bruce Kaufmann , Ilya I. Novof , Steven F. Oakland , Kenneth Shaw , Leon Skarshinski
发明人： Roland Bechade , Frank D. Ferraiolo , Bruce Kaufmann , Ilya I. Novof , Steven F. Oakland , Kenneth Shaw , Leon Skarshinski
IPC分类号： G06F1/10 , G11C11/407 , H03K5/00 , H03K5/135 , H03K5/15 , H04J3/06 , H04L7/033 , H04L7/00 , H04L25/36 , H04L25/40
CPC分类号： H03K5/1504 , G06F1/10
摘要： A process independent digital clock signal timing network is described for generating a chip clock substantially in phase with and offset by one cycle from an input clock signal. The timing network determines the delay experienced by a clock signal passing through a predetermined internal clock circuit on the chip and pregates the internal clock circuit by an amount equivalent to the determined delay such that the chip clock signal output from the internal clock circuitry lags the external clock signal input to the semiconductor chip by one cycle. Various timing network embodiments are described and claimed.
摘要翻译：描述了一种独立于过程的数字时钟信号定时网络，用于产生与输入时钟信号基本同相并偏移一个周期的芯片时钟。定时网络确定通过芯片上的预定内部时钟电路的时钟信号经历的延迟，并且将内部时钟电路预先相当于所确定的延迟量，使得从内部时钟电路输出的芯片时钟信号滞后于外部时钟信号输入到半导体芯片一个周期。描述和要求保护各种定时网络实施例。

4. 发明授权

US5048062A Transmitting commands over a serial link 失效
标题翻译：通过串行链路发送命令
公开(公告)号：US5048062A
公开(公告)日：1991-09-10
申请号：US429268
申请日：1989-10-30
申请人： Thomas A. Gregg , Leon Skarshinski
发明人： Thomas A. Gregg , Leon Skarshinski
IPC分类号： H04L7/00 , H04L7/08 , H04L25/49 , H04L29/08
CPC分类号： H04L25/4908 , H04L7/0083
摘要： An apparatus and method for transmitting commands over a serial link having a switch intermediate a channel and a control unit wherein continuous sequences of idle characters (K.28.5) are sent over the link for maintaining character synchronization. Commands and response information is sent between ports of the switch and the channel and/or the control unit by modifying every other idle character to a modified idle character to which a command or response function has been assigned. In the modification, a selected number of the bits of the idle character are held invariant, and only those bits are varied which form data characters according to the rules of the 8B/10B encoding method. Code points for a total of 124 modified idle characters are disclosed to which a separate command or response may be assigned.

5. 发明授权

US4866609A Byte count handling in serial channel extender with buffering for data pre-fetch 失效
标题翻译：串行通道扩展器中的字节计数处理，具有用于数据预取的缓冲
公开(公告)号：US4866609A
公开(公告)日：1989-09-12
申请号：US248273
申请日：1988-09-21
申请人： Salvatore A. Calta , Thomas A. Gregg , Leon Skarshinski , Richard Strangwayes
发明人： Salvatore A. Calta , Thomas A. Gregg , Leon Skarshinski , Richard Strangwayes
IPC分类号： G06F13/12
CPC分类号： G06F13/122
摘要： A channel subsystem with a conventional serial extender link that causes communications between a channel and a control unit to be delayed by the additional time to transmit a message in one direction and to transmit an acknowledgement in the other direction. The channel subsystem also has a buffer and associated components (called a channel outboard box) that are used for prefetching data from processor memory or from a peripheral device without waiting for the acknowledgment routines that are commonly used on both an interlocked data transfer and a non-interlocked transfer (called data streaming). A system of counters and other components and associated operations maintain the correct byte count that would otherwise be maintained in a system without the prefetch buffer and with only a short serial link. A system of count and status frames provides for sending byte count and other status information between the channel and the outboard box.
摘要翻译：具有常规串行扩展器链路的信道子系统，其使得信道和控制单元之间的通信被延迟额外的时间以在一个方向上发送消息并且在另一个方向上发送确认。信道子系统还具有用于从处理器存储器或外围设备预取数据的缓冲器和相关组件（称为通道外侧盒），而不等待在互锁的数据传输和非互连数据传输上通常使用的确认例程 - 称为数据流传输。计数器和其他组件和相关操作的系统保持正确的字节计数，否则将在没有预取缓冲区的系统中维护，并且仅具有短的串行链路。计数和状态帧的系统提供在通道和外侧盒之间发送字节计数和其他状态信息。

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