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1. 发明授权

US4866609A Byte count handling in serial channel extender with buffering for data pre-fetch 失效
标题翻译：串行通道扩展器中的字节计数处理，具有用于数据预取的缓冲
公开(公告)号：US4866609A
公开(公告)日：1989-09-12
申请号：US248273
申请日：1988-09-21
申请人： Salvatore A. Calta , Thomas A. Gregg , Leon Skarshinski , Richard Strangwayes
发明人： Salvatore A. Calta , Thomas A. Gregg , Leon Skarshinski , Richard Strangwayes
IPC分类号： G06F13/12
CPC分类号： G06F13/122
摘要： A channel subsystem with a conventional serial extender link that causes communications between a channel and a control unit to be delayed by the additional time to transmit a message in one direction and to transmit an acknowledgement in the other direction. The channel subsystem also has a buffer and associated components (called a channel outboard box) that are used for prefetching data from processor memory or from a peripheral device without waiting for the acknowledgment routines that are commonly used on both an interlocked data transfer and a non-interlocked transfer (called data streaming). A system of counters and other components and associated operations maintain the correct byte count that would otherwise be maintained in a system without the prefetch buffer and with only a short serial link. A system of count and status frames provides for sending byte count and other status information between the channel and the outboard box.
摘要翻译：具有常规串行扩展器链路的信道子系统，其使得信道和控制单元之间的通信被延迟额外的时间以在一个方向上发送消息并且在另一个方向上发送确认。信道子系统还具有用于从处理器存储器或外围设备预取数据的缓冲器和相关组件（称为通道外侧盒），而不等待在互锁的数据传输和非互连数据传输上通常使用的确认例程 - 称为数据流传输。计数器和其他组件和相关操作的系统保持正确的字节计数，否则将在没有预取缓冲区的系统中维护，并且仅具有短的串行链路。计数和状态帧的系统提供在通道和外侧盒之间发送字节计数和其他状态信息。

2. 发明授权

US5634007A Independent computer storage addressing in input/output transfers 失效
标题翻译：输入/输出传输中独立的计算机存储寻址
公开(公告)号：US5634007A
公开(公告)日：1997-05-27
申请号：US398053
申请日：1995-03-02
申请人： Salvatore A. Calta , Robert B. Cook , Fernando A. Luiz , Gregory M. Nordstrom , Martin W. Sachs , Caryl A. Thorn
发明人： Salvatore A. Calta , Robert B. Cook , Fernando A. Luiz , Gregory M. Nordstrom , Martin W. Sachs , Caryl A. Thorn
IPC分类号： G06F13/28 , G06F12/06
CPC分类号： G06F13/28
摘要： A method and apparatus for performing direct memory address (DMA) operations between a requestor and responder device by prestoring, for each device, a logical token and offset value which is recognizable by the device as an indicia to identify one or more local memory addresses within the device, and initiating a DMA operation within the requestor device by the requestor device transferring the token and offset value to the responder device, the responder device identifying a responder device local memory address by translation of the token and offset value, and the responder device accessing the identified responder local memory address for data transfer, associated with the token and offset, and the requestor device identifying a requestor device local memory address for completing the data transfer.
摘要翻译：一种用于通过为每个设备预先存储逻辑令牌和设备可识别的偏移值作为标记来识别一个或多个本地存储器地址内的一个或多个本地存储器地址的方式和装置，用于在请求者和响应器设备之间执行直接存储器地址（DMA）操作所述设备，以及由所述请求者设备在所述请求者设备中向所述应答器设备发送所述令牌和偏移值的DMA操作，所述响应者设备通过所述令牌和偏移值的转换来识别响应者设备本地存储器地址，以及所述应答器设备访问识别的响应者本地存储器地址用于与令牌和偏移相关联的数据传输，以及请求者设备标识用于完成数据传输的请求者设备本地存储器地址。

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