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1. 发明授权

US4567464A Fixed rate constrained channel code generating and recovery method and means having spectral nulls for pilot signal insertion 失效
标题翻译：固定速率限制信道码生成和恢复方法以及具有用于导频信号插入的频谱零点的装置
公开(公告)号：US4567464A
公开(公告)日：1986-01-28
申请号：US461842
申请日：1983-01-28
申请人： Paul H. Siegel , Stephen J. Todd
发明人： Paul H. Siegel , Stephen J. Todd
IPC分类号： H03M7/14 , G11B20/10 , G11B20/14 , H04L25/49 , G11B5/09
CPC分类号： G11B20/1426
摘要： The generation of NRZ representations of RLL encoded datastreams utilizes a length oriented arithmetically recursive RLL encoder whose finite state encoding transition space has assigned RLL symbols to state transitions. By constraining the paths, and hence restricting the set of allowable RLL symbol streams, then selectable notch frequencies in the spectra of the NRZ representation can be secured. Recovery of data is obtained by the logical dual of this process. Also, a NRZ bit stream representation exhibits a frequency spectrum notched at f/kn Hertz if k NRZ source codestreams are k-way interleaved.
摘要翻译： RLL编码数据流的NRZ表示的生成利用长度定向的算术递归RLL编码器，其有限状态编码转换空间已经将RLL符号分配给状态转换。通过限制路径并因此限制可允许的RLL符号流的集合，则可以确保NRZ表示的频谱中的可选择的陷波频率。通过该过程的逻辑双重获得数据的恢复。此外，如果k个NRZ源码流是k路交织的，则NRZ比特流表示呈现在f / kn赫兹切割的频谱。

2. 发明授权

US07284186B2 Parity check outer code and runlength constrained outer code usable with parity bits 有权
标题翻译：奇偶校验外码和运行长度约束外码可用奇偶校验位
公开(公告)号：US07284186B2
公开(公告)日：2007-10-16
申请号：US10862847
申请日：2004-06-07
申请人： Paul H. Siegel , Mats Öberg
发明人： Paul H. Siegel , Mats Öberg
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： H04L1/005 , G11B20/10009 , G11B20/1426 , H03M13/091 , H03M13/11 , H03M13/27 , H03M13/29 , H03M13/2957 , H03M13/6343 , H04L1/0041 , H04L1/0065 , H04L1/0066 , H04L1/0068 , H04L1/0071 , H04L25/497
摘要： A method uses an outer code that is a concatenation of code words generated by a parity check encoder. The outer code word is permuted by an interleaver. The high rate coding provides good performance with a simple structure. A parity check bit is generated for each data word of received systematic dates. Code words are formed by adding a generated parity bit to each data word. Groups of code words are permuted to form encoded input for transmission in a communication channel. The invention further includes encoding to maintain a runlength-limiting (RLL) constraint at the channel input. Interleaved runlength encoded system data is used to generate error code bits. Insertion of error code bits in the system data at the channel input is controlled. This guarantees that the channel input stream comprised of the runlength-limited system data and inserted error code bits meets the runlength constraints.
摘要翻译：一种方法使用外部代码，该外部代码是由奇偶校验编码器生成的码字的级联。外码字由交织器置换。高速率编码通过简单的结构提供了良好的性能。为接收到的系统日期的每个数据字生成奇偶校验位。通过将生成的奇偶校验位加到每个数据字上来形成代码字。代码字组被置换以形成用于在通信信道中传输的编码输入。本发明还包括编码以在频道输入端保持游程限制（RLL）约束。交错运行长度编码系统数据用于产生错误码位。在通道输入的系统数据中插入错误码位被控制。这保证由游程限制系统数据和插入的错误码位组成的信道输入流满足游程长度约束。

3. 发明授权

US5280489A Time-varying Viterbi detector for control of error event length 失效
标题翻译：用于控制误差事件长度的时变维特比检测器
公开(公告)号：US5280489A
公开(公告)日：1994-01-18
申请号：US869570
申请日：1992-04-15
申请人： Lyle J. Fredrickson , Razmik Karabed , James W. Rae , Paul H. Siegel , Hemant K. Thapar , Roger W. Wood
发明人： Lyle J. Fredrickson , Razmik Karabed , James W. Rae , Paul H. Siegel , Hemant K. Thapar , Roger W. Wood
IPC分类号： H03M13/31 , G06F11/20 , H03M13/12
CPC分类号： H03M13/31
摘要： A method and apparatus for detecting spectral null sequences of a spectrally-constrained code on a noisy communications channel. From a Viterbi detector with a trellis structure comprising a plurality of states and edges, predetermined ones of the states and edges in the trellis structure are deleted at preselected times modulo N, such as times .phi. modulo N and/or at intermediate times m modulo N, where m=.phi., thereby to create a time-varying trellis structure for limiting the maximum length of dominant error events. The deleted edges are generally those edges which would have entered or emanated from the deleted states if they were not deleted. The trellis structure may be a so-called systolic structure, in which case the spectral null sequences are preferably DC-free or Nyquist free.
摘要翻译：一种用于检测噪声通信信道上的频谱约束码的频谱零序列的方法和装置。从具有包括多个状态和边缘的网格结构的维特比检测器，网格结构中的预定的状态和边缘被预选为时间N，例如时间（phi）模N和/或中间时间m 模N，其中m =（phi），从而产生用于限制主要误差事件的最大长度的时变网格结构。删除的边通常是那些从删除状态输入或发出的边缘，如果它们没有被删除。网格结构可以是所谓的收缩结构，在这种情况下，光谱无效序列优选不含DC或奈奎斯特。

4. 发明授权

US4870414A Even mark modulation coding method 失效
标题翻译：偶标记调制编码方法
公开(公告)号：US4870414A
公开(公告)日：1989-09-26
申请号：US169918
申请日：1988-03-18
申请人： Razmik Karabed , Paul H. Siegel
发明人： Razmik Karabed , Paul H. Siegel
IPC分类号： H04L25/08 , G11B20/10 , H03M5/14 , H03M13/23 , H04L25/49 , H04L25/497
CPC分类号： G11B20/10009 , H03M5/145 , H04L25/4908 , H04L25/497
摘要： A method termed Even Mark Modulation (EMM) is disclosed for coding input strings for input-restricted (1+D) or (1+D).sup.2 partial response channels that require at least one pair of consecutive signals of one state in order to record or transmit data to a receiving device. EMM provides improved coding gains and is especially suitable for optical recording.An input string is encoded into a binary code string in which all one-state signals (e.g., "1's") are in the form of runs of at least one contiguous pair; however, signals of an opposite state (e.g., "0's") may be of any length or duration. The EMM signals are detected with a maximum likelihood detector using an algorithm based on a three-state trellis structure for (1+D) channels and a five-state trellis structure for (1+D).sup.2 channels adapted to the particular partial response channel. In a preferred embodiment, the coding rate is 2/3 and the coding gain is at least 3 dB unnormalized and at least 2.2 dB when normalized. A finite-state encoder and sliding block decoder are disclosed, together with logic equations for encoder and decoder circuits.

5. 发明授权

US06795947B1 Parity check outer code and runlength constrained outer code usable with parity bits 有权
公开(公告)号：US06795947B1
公开(公告)日：2004-09-21
申请号：US09577552
申请日：2000-05-24
申请人： Paul H. Siegel , Mats Öberg
发明人： Paul H. Siegel , Mats Öberg
IPC分类号： G06F1100
CPC分类号： H04L1/005 , G11B20/10009 , G11B20/1426 , H03M13/091 , H03M13/11 , H03M13/27 , H03M13/29 , H03M13/2957 , H03M13/6343 , H04L1/0041 , H04L1/0065 , H04L1/0066 , H04L1/0068 , H04L1/0071 , H04L25/497
摘要： A method uses an outer code that is a concatenation of code words generated by a parity check encoder. The outer code word is permuted by an interleaver. The high rate coding provides good performance with a simple structure. An odd parity check bit is generated for each data word of received systematic dates. Code words are formed by adding a generated parity bit to each data word. Groups of code words are permuted to form encoded input for transmission in a communication channel. The invention further includes encoding to maintain a runlength-limiting (RLL) constraint at the channel input. Interleaved runlength encoded system data is used to generate error code bits. Insertion of error code bits in the system data at the channel input is controlled. This guarantees that the channel input stream comprised of the runlength-limited system data and inserted error code bits meets the runlength constraints.

6. 发明授权

US5430744A Method and means for detecting partial response waveforms using a modified dynamic programming heuristic 失效
标题翻译：使用修改的动态规划启发式检测部分响应波形的方法和装置
公开(公告)号：US5430744A
公开(公告)日：1995-07-04
申请号：US129904
申请日：1993-09-30
申请人： Gerhard P. Fettweis , Razmik Karabed , Paul H. Siegel , Hemant K. Thapar
发明人： Gerhard P. Fettweis , Razmik Karabed , Paul H. Siegel , Hemant K. Thapar
IPC分类号： G06F11/10 , G11B20/18 , H03M13/23 , H03M13/41 , H04L25/08 , H03M13/00 , H04L25/34 , H04L25/49
CPC分类号： H03M13/6343 , H03M13/3961 , H03M13/41 , H03M13/4107 , H03M13/6502
摘要： A Viterbi decoder having a recursive processor modified to process each node in a trellis of a partial response coded signal to shift the branch metric additions over the node to effectuate compare, select, add operation order on the predecessor survivor metrics terminating in that node, to compare the metrics of the predecessor sequences terminating in the node, to select a survivor sequence, and to add the shifted branch metrics to the metric of the selected survivor sequence.
摘要翻译：一种具有递归处理器的维特比解码器，其被修改为处理部分响应编码信号的网格中的每个节点，以便通过该节点移动分支度量添加，以对在该节点终止的前导幸存者度量进行比较，选择，添加操作顺序，比较终止在节点中的前导序列的度量，以选择幸存者序列，并将移位的分支度量添加到所选存活序列的度量。

7. 发明授权

US5135029A Fuel hose breakaway unit 失效
标题翻译：燃油软管破碎机组
公开(公告)号：US5135029A
公开(公告)日：1992-08-04
申请号：US553227
申请日：1990-07-12
申请人： Paul B. Anderson , Donald L. Leininger , Paul H. Siegel , Lawerence L. Blasch , David R. Pendleton
发明人： Paul B. Anderson , Donald L. Leininger , Paul H. Siegel , Lawerence L. Blasch , David R. Pendleton
IPC分类号： F16L35/00 , F16L55/10
CPC分类号： F16L55/1015 , B67D7/3218 , F16L35/00 , Y10T137/87957
摘要： A breakaway unit which is adapted to be mounted in series flow relation with a fuel nozzle. The breakaway unit comprises a flex section which assures an axial transmission of forces to a valve section which is separated when a vehicle drives away from a dispensing unit with the nozzle lodged in its fuel tank. The valve section comprises inlet and outlet couplers and means for releasable locking the couplers in an assembled relation. These means comprise fingers which are flexed outwardly when a separating force exceeds a predetermined value. Garter springs embrace the fingers to accurately control at which the couplers will separate. The fingers engage angularly spaced lugs which permit the fingers to be telescoped therebetween and then rotated to a locking position to facilitate reassembly of the couplers with a minimum of effort. Alternate embodiments of the invention disclose other forms of spring means for accurately controlling the force at which the couplers will separate. Also disclosed are alternate constructions which minimize the effort required for reassembly.
摘要翻译：分离单元，其适于与燃料喷嘴串联流动关系。分离单元包括弯曲部分，其确保轴向轴向传递到阀部分的部分，当车辆驱动离开分配单元时，分离单元具有浸入其燃料箱中的喷嘴。阀部分包括入口和出口联接器以及用于以组装的关系可释放地锁定联接器的装置。这些装置包括当分离力超过预定值时向外弯曲的指状物。夹持弹簧包含手指以准确地控制耦合器将分离的位置。指状物接合角度间隔的凸耳，其允许手指在其间被套叠，然后旋转到锁定位置，以便以最小的努力重新组装耦合器。本发明的替代实施例公开了用于精确地控制耦合器将分离的力的其他形式的弹簧装置。还公开了使重新组装所需的努力最小化的替代结构。

8. 发明授权

US5510912A Method and apparatus for modulation of multi-dimensional data in holographic storage 失效
标题翻译：用于调制全息存储中的多维数据的方法和装置
公开(公告)号：US5510912A
公开(公告)日：1996-04-23
申请号：US104267
申请日：1993-08-09
申请人： Miguel M. Blaum , Paul H. Siegel , Glenn T. Sincerbox , Alexander Vardy
发明人： Miguel M. Blaum , Paul H. Siegel , Glenn T. Sincerbox , Alexander Vardy
IPC分类号： G06E1/04 , G11B7/0065 , G11C13/04 , G02B5/32
CPC分类号： H03M13/2906 , G06E1/045 , G11B7/0065 , G11C13/042 , H03M13/136 , H03M13/31
摘要： A modulator apparatus for modulating arrays of input data V.sub.in to be stored in a holographic recording medium is disclosed wherein the final output data array V.sub.out has frequent transitions from light to dark and from dark to light in either dimension across the data page and has the total amount of illuminated regions throughout the entire data page held constant. These two constraints are achieved by a first set of control arrays obtained from two fixed sets of m.times.n binary arrays {A.sub.0, A.sub.1, . . . , A.sub.n } and {B.sub.0, B.sub.1, . . . , B.sub.m } which in turn are obtained from fixed sets of binary control vectors {a.sub.0, a.sub.0, a.sub.1, . . . , a.sub.n }, {b.sub.0, b.sub.1, . . . , b.sub.m }, respectively. The control vectors a.sub.0, a.sub.1, . . . , a.sub.n any n+1 fixed elements of the inverse mapping, .phi. .sup.1 (C.sub.1), of the (t-2) error-correcting code C.sub.1 of length m. The control vectors b.sub.0, b.sub.1, . . . , b.sub.m are any m+1 fixed elements of the inverse mapping, .phi. .sup.1 (C.sub.2), of the (t-s) error-correcting code C.sub.2 of length n. The first constraint is achieved by V'.sub.in =V.sub.in .sym.(A.sym.B). In order to balance the modulated array, a second set of control arrays {W.sub.0, W.sub.1, W.sub.2, . . . , W.sub.1, W.sub.2, . . . , W.sub.mn-1 } is obtained from the set of control vectors {W.sub.0, W.sub.1, W.sub.2, . . . , W.sub.mn-1 }. The second constraint is achieved by complementing the bits of the input binary array V'.sub.in in a horizontal readout order terminating after the first i bits. The final modulated output array V.sub.out =V'.sub.in .sym.W simultaneously satisfies both constraints.
摘要翻译：公开了一种用于调制要存储在全息记录介质中的输入数据Vin阵列的调制器装置，其中最终输出数据阵列Vout在数据页面上的任一维度中都具有从亮到暗和从暗到浅的频繁转变，整个数据页面的照明区域数量保持不变。这两个约束通过从两个固定的mxn二进制数组{A0，A1，...获得）获得的第一组控制数组来实现。。。，An}和{B0，B1，... 。。，Bm}，其又从固定的二进制控制向量{+ E，rar / a / 0，+ E，rar / a / 0，+ E，rar / a / 1。。。，+ E，rar / a / n}，{+ E，rar / b / 0，+ E，rar / b / 1。。。，+ E，rar / b / m}。控制向量+ E，rar / a / 0，+ E，rar / a / 1，。。，+ E，rar / a / n长度m的（t-2）纠错码C1的逆映射的任意n + 1个固定元素，phi 1（C1）。控制向量b0，b1，... 。。 bm是长度为n的（t-s）纠错码C2的逆向映射的任何m + 1个固定元素，即phi 1（C2）。第一个约束是由V'in = Vin（+）（A（+）B）来实现的。为了平衡调制阵列，第二组控制阵列{W0，W1，W2，... 。。，W1，W2，...。。。，从而从控制矢量{+ E，rar / W / 0，+ E，rar / W / 1，+ E，rar / W / 2的集合获得Wmn-1}。。。，+ E，rar / W / mn-1}。第二个约束是通过在第一个i位之后终止的水平读出顺序互补输入二进制数组V'in的位来实现的。最终调制输出阵列Vout = V'in（+）W同时满足两个约束条件。

9. 发明授权

US5450443A Method and apparatus for constructing asymptotically optimal second order DC-free channel codes 失效
标题翻译：用于构建渐近最优的二阶无DC信道码的方法和装置
公开(公告)号：US5450443A
公开(公告)日：1995-09-12
申请号：US116147
申请日：1993-09-01
申请人： Paul H. Siegel , Alexander Vardy
发明人： Paul H. Siegel , Alexander Vardy
IPC分类号： H03M5/14 , H04L25/48 , H04L25/49 , H04L25/34
CPC分类号： H04L25/4912 , H03M5/145
摘要： An encoding apparatus for constructing an asymptotically optimal coding scheme for second order DC-constrained channels is disclosed. A first encoding function block breaks an input data stream into equal sized vectors of length m bits. A sign designation bit is then attached to each vector to make vectors of length m+1 bits. r redundancy bits are added to each vector, to produce balanced vectors of length m+1+r bits. A first moment is calculated for each vector. A determination is made whether the addition of this vector's first moment value to an accumulated running sum of all the vectors' first moments effectively drives the running sum in the direction of zero. If is does then that vector's first moment is added to the accumulated running sum of first moments and the vector is added to the output array. If not, then the value of that vector's first moment is inverted before being added to the accumulated running sum, and the individual bits of this vector get inverted, and the sign designation bit of that vector gets toggled so as to indicate upon decoding that the bits of this vector have been involved. This encoding process is repeated until all the first moments of all the individual vectors of the balanced array have been calculated and a total accumulated running sum of all the first moments has been determined. A last balanced vector is produced, whose first moment value is added to the value of the total accumulation running first moment sum to drive the final first moment sum to zero. The output array of such vectors is then second-order DC-free, and the above described encoder is asymptotically optimal for second order DC-constrained channels.
摘要翻译：公开了一种用于构造用于二阶DC约束信道的渐近最佳编码方案的编码装置。第一编码功能块将输入数据流分解成长度为m比特的相等大小的向量。然后，将符号指定位附加到每个向量以使长度为m + 1位的向量。 r个冗余比特被添加到每个向量，以产生长度为m + 1 + r比特的平衡向量。计算每个向量的第一时刻。确定是否将该向量的第一个力矩值加到所有向量的第一个力矩的累积运行总和中有效地驱动零向上的运行和。如果是，那么该向量的第一时刻被加到第一时刻的累加运行和，并将向量加到输出数组中。否则，该向量的第一时刻的值在加到累加运行和之前被反转，并且该向量的各个比特被反转，并且该向量的符号指定位被切换，以便在解码时指示已经涉及到这个向量的位。重复该编码处理，直到已经计算了平衡阵列的所有各个向量的所有第一时刻，并且已经确定了所有第一时刻的总累计运行总和。产生最后一个平衡向量，其第一个力矩值加到累积运行的第一时刻总和的值，以将最终的第一个力矩和驱动为零。这样的向量的输出阵列然后是二阶无DC的，并且上述编码器对于二阶DC约束信道是渐近最优的。

10. 发明授权

US5095484A Phase invariant rate 8/10 matched spectral null code for PRML 失效
标题翻译： PRML的相位不变率8/10匹配光谱空码
公开(公告)号：US5095484A
公开(公告)日：1992-03-10
申请号：US747401
申请日：1991-08-19
申请人： Razmik Karabed , Paul H. Siegel
发明人： Razmik Karabed , Paul H. Siegel
IPC分类号： G11B20/10 , G11B20/14 , H03M13/31 , H04L25/49
CPC分类号： G11B20/10055 , G11B20/10009 , G11B20/1426 , H03M13/31 , H04L25/4908 , G11B2020/1438
摘要： A method for coding a binary data string for a partial-response channel having a transfer function with a spectral null at zero frequency to provide a coding rate 8/10 and an output which is invariant to 180-degree phase shifts in the channel output signal. A finite-state machine is created having two pairs of states and a plurality of codewords each corresponding to a respective binary data byte. The binary data string is encoded by said machine into a string of binary codewords having a power spectrum value of zero for a frequency of zero. In response to each successive data byte in the binary data string, there is generated one of two complementary codewords from the one of that pair of the states designated by said machine as corresponding to the data byte for the then current state of the machine. The sequence of said one complementary codewords is so decoded as to provide the same data output for said codeword sequence and its complement, irrespective of which of said complementary codewords was generated. The next state of said machine is preselected according to the value of the data byte and current state, and the next state for one element of a pair is the complement of the next state for the other element of the same pair.
摘要翻译：一种用于对具有零频率的频谱零点的传递函数的部分响应信道的二进制数据串进行编码的方法，以提供编码率8/10和对信道输出信号中的180度相移不变的输出。创建具有两对状态和多个码字的有限状态机，每个码字对应于相应的二进制数据字节。二进制数据串由所述机器编码成频率为零的功率谱值为零的二进制码字串。响应于二进制数据串中的每个连续的数据字节，从所述机器指定的一对状态中的一个中产生两个互补码字中的一个对应于机器的当前状态的数据字节。所述一个互补码字的序列被解码为为所述码字序列及其补码提供相同的数据输出，而与所生成的所述互补码字中的哪一个无关。根据数据字节和当前状态的值预先选择所述机器的下一状态，并且一对的一个元件的下一状态是相同对的另一元件的下一状态的补码。

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