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1. 发明授权

US5448565A Multiport LAN bridge 失效
标题翻译：多端口LAN桥
公开(公告)号：US5448565A
公开(公告)日：1995-09-05
申请号：US975236
申请日：1992-11-12
申请人： Paul Chang , Joseph W. Coates , Edward H. C. Ku , Simin H. Sanaye
发明人： Paul Chang , Joseph W. Coates , Edward H. C. Ku , Simin H. Sanaye
IPC分类号： H04L12/46
CPC分类号： H04L12/46
摘要： A multiport bridge includes a plurality of Bridge Port Frame Handler (BPFH) units coupled through a Source Routing bus and a Transparent Bridge Bus to a microcontroller, a Packet Memory and a Transparent Bridge Control Management System (TBCMS). Each Bridge Port Frame Handler unit receives Frames from its attached LAN, forwards selected portions of Source Routing Frames to other Bridge Port Frame Handler Units for further processing. Likewise, selected portions of Transparent Bridge Frames are forwarded to the TBCMS whereat routing information and signature information is extracted and returned to the forwarding BPFH unit for further processing.
摘要翻译：多端口桥接器包括通过源路由总线和透明桥接总线耦合到微控制器，分组存储器和透明网桥控制管理系统（TBCMS）的多个桥接端口帧处理器（BPFH）单元。每个桥接端口帧处理器单元从其连接的LAN接收帧，将源路由帧的选定部分转发到其他网桥端口帧处理单元进行进一步处理。同样地，将透明网桥帧的选定部分转发到TBCMS，在该TBCMS中提取路由信息和签名信息，并返回到转发BPFH单元进行进一步处理。

2. 发明授权

US11070471B1 Switch fabric for networked virtual machines 有权
公开(公告)号：US11070471B1
公开(公告)日：2021-07-20
申请号：US16048815
申请日：2018-07-30
申请人： Paul Chang
发明人： Paul Chang
IPC分类号： H04L12/741 , H04L12/721 , H04L12/46 , H04L12/931 , H04L12/947
摘要： A switch fabric has a plurality of leaf switches, each leaf switch having a local tenant identifier (LTID) table, a local forwarding information base (LFIB) table, and a forwarding engine coupled to the LTID table and LFIB table. Each leaf switch has downlink ports operative on VLAN packets such as those generated by Container/Virtual machines (CVM), each leaf switch also having a reconfigurable uplink port for transmission and reception of VxLAN packets formed from VLAN packets which have a destination address which is not local to a particular leaf switch. The uplink ports are coupled to the leaf ports of one or more spine switches, each spine switch having a Global Forward Information Base (GFIB) table slice coupled to a VxLAN forwarder which receives VxLAN packets, de-encapsulates them and uses the GFIB table slice to form new VxLAN packets transmitted to a different leaf port.

3. 发明授权

US08845247B2 Thermal compensation system for a milling machine 有权
标题翻译：铣床热补偿系统
公开(公告)号：US08845247B2
公开(公告)日：2014-09-30
申请号：US13170793
申请日：2011-06-28
申请人： Ching-Wei Wu , Ying-Shing Shiao , Chia-Hui Tang , Yu-Che Wang , Paul Chang
发明人： Ching-Wei Wu , Ying-Shing Shiao , Chia-Hui Tang , Yu-Che Wang , Paul Chang
IPC分类号： B23Q15/18
CPC分类号： B23Q15/18 , G05B2219/45145 , G05B2219/49207 , G05B2219/49219 , Y10T409/300896 , Y10T409/306832 , Y10T409/307224 , Y10T409/309744
摘要： A milling machine has a base, a work platform mounted movably on the base, and a ruler mounted on the work platform. The work platform is movable relative to a base axis. The thermal compensation system includes a sensor and a control unit. The sensor is configured to be mounted on the base for sensing a position of each of the work platform and the ruler relative to the base axis. The control unit is coupled to the sensor, and determines a work platform displacement and a ruler displacement according to the positions sensed by the sensor. The control unit further calculates a compensation value based on the work platform displacement and the ruler displacement. The control unit is configured to correct the position of the work platform relative to the base axis according to the compensation value.
摘要翻译：铣床具有基座，可移动地安装在基座上的工作平台和安装在工作平台上的标尺。工作平台相对于基础轴线是可移动的。热补偿系统包括传感器和控制单元。传感器被配置为安装在基座上，用于感测工作平台和标尺中的每一个相对于基轴的位置。控制单元耦合到传感器，并根据传感器感测到的位置确定工作平台位移和尺子位移。控制单元进一步基于工作平台位移和标尺位移来计算补偿值。控制单元被配置为根据补偿值来校正工作平台相对于基准轴的位置。

4. 发明授权

US08703576B2 Gap-fill keyhole repair using printable dielectric material 失效
公开(公告)号：US08703576B2
公开(公告)日：2014-04-22
申请号：US13232293
申请日：2011-09-14
申请人： Paul Chang , Josephine B. Chang , Michael A. Guillorn , Jeffrey W. Sleight
发明人： Paul Chang , Josephine B. Chang , Michael A. Guillorn , Jeffrey W. Sleight
IPC分类号： H01L21/76
CPC分类号： H01L29/51 , H01L21/311 , H01L21/76825 , H01L21/76837 , H01L29/66545
摘要： Disposable gate structures are formed on a semiconductor substrate. A planarization dielectric layer is deposited over the disposable gate structures and planarized to provide a top surface that is coplanar with top surface of the disposable gate structures. The planarization dielectric layer at this point includes gap-fill keyholes between narrowly spaced disposable gate structures. A printable dielectric layer is deposited over the planarization dielectric layer to fill the gap-fill keyholes. Areas of the printable dielectric layer over the gap-fill keyholes are illuminated with radiation that cross-links cross-linkable bonds in the material of the printable dielectric layer. Non-crosslinked portions of the printable dielectric layer are subsequently removed selective to crosslinked portions of the printable dielectric layer, which fills at least the upper portion of each gate-fill keyhole. The disposable gate structures are removed to form gate cavities. The gate cavities are filled with a gate dielectric and a gate electrode.

5. 发明授权

US08626480B2 Compact model for device/circuit/chip leakage current (IDDQ) calculation including process induced uplift factors 失效
标题翻译：紧凑型器件/电路/芯片泄漏电流（IDDQ）计算，包括工艺引起的隆起因素
公开(公告)号：US08626480B2
公开(公告)日：2014-01-07
申请号：US12574440
申请日：2009-10-06
申请人： Paul Chang , Jie Deng , Terrence B. Hook , Sim Y. Loo , Anda C. Mocuta , Jae-Eun Park , Kern Rim , Xiaojun Yu
发明人： Paul Chang , Jie Deng , Terrence B. Hook , Sim Y. Loo , Anda C. Mocuta , Jae-Eun Park , Kern Rim , Xiaojun Yu
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G01R31/2848 , G01R31/3008 , G06F17/5009 , G06F17/5022 , G06F17/5036
摘要： A system, method and computer program product for implementing a quiescent current leakage specific model into semiconductor device design and circuit design flows. The leakage model covers all device geometries with wide temperature and voltage ranges and, without the need for stacking factor calculations nor spread sheet based IDDQ calculations. The leakage model for IDDQ calculation incorporates further parasitic and proximity effects. The leakage model implements leakage calculations at different levels of testing, e.g., from a single device to a full chip design, and are integrated within one single model. The leakage model implements leakage calculations at different levels of testing with the leverage of a single switch setting. The implementation is via a hardware definition language code or object oriented code that can be compiled and operated using a netlist of interest, e.g., for conducting a performance analysis.
摘要翻译：一种用于将静态电流泄漏特定模型实现为半导体器件设计和电路设计流程的系统，方法和计算机程序产品。泄漏模型涵盖宽温度和电压范围的所有器件几何，并且不需要堆叠因子计算，也不需要基于平板的IDDQ计算。 IDDQ计算的泄漏模型包含进一步的寄生和邻近效应。泄漏模型在不同的测试水平下实施泄漏计算，例如从单个设备到全芯片设计，并且集成在一个单一的模型中。泄漏模型通过单个开关设置的杠杆来实现不同测试级别的泄漏计算。该实现是通过硬件定义语言代码或面向对象的代码，其可以使用感兴趣的网表来编译和操作，例如用于进行性能分析。

6. 发明授权

US08456226B2 Method and system for a process sensor to compensate SoC parameters in the presence of IC process manufacturing variations 失效
标题翻译：用于在存在IC工艺制造变化的情况下补偿SoC参数的过程传感器的方法和系统
公开(公告)号：US08456226B2
公开(公告)日：2013-06-04
申请号：US13545580
申请日：2012-07-10
申请人： Stephen Chi-Wang Au , Arya Behzad , Paul Chang
发明人： Stephen Chi-Wang Au , Arya Behzad , Paul Chang
IPC分类号： G05F3/02
CPC分类号： H03F3/45475 , H03F2203/45048
摘要： Certain aspects of a method and system for a process sensor to compensate SoC parameters in the presence of IC process manufacturing variations are disclosed. Aspects of one method may include determining an amount of process variation associated with at least one transistor within a single integrated circuit. The determined amount of process variation may be compensated by utilizing a process dependent current, a bandgap current, and a current associated with a present temperature of the transistor. The process dependent current, the bandgap current and the current associated with the present temperature of the transistor may be combined to generate an output current. A voltage generated across a variable resistor may be determined based on the generated output current.
摘要翻译：公开了用于在存在IC工艺制造变化的情况下补偿SoC参数的工艺传感器的方法和系统的某些方面。一种方法的方面可以包括确定与单个集成电路内的至少一个晶体管相关联的工艺变化量。可以通过利用与工艺相关的电流，带隙电流和与晶体管的当前温度相关联的电流来补偿确定的工艺变化量。过程相关电流，带隙电流和与晶体管的当前温度相关联的电流可以被组合以产生输出电流。可以基于产生的输出电流来确定可变电阻器两端产生的电压。

7. 发明申请

US20130062709A1 Gap-Fill Keyhole Repair Using Printable Dielectric Material 失效
标题翻译：使用可印刷介质材料进行缺陷孔眼修复
公开(公告)号：US20130062709A1
公开(公告)日：2013-03-14
申请号：US13232293
申请日：2011-09-14
申请人： Paul Chang , Josephine B. Chang , Michael A. Guillorn , Jeffrey W. Sleight
发明人： Paul Chang , Josephine B. Chang , Michael A. Guillorn , Jeffrey W. Sleight
IPC分类号： H01L29/51 , H01L21/28
CPC分类号： H01L29/51 , H01L21/311 , H01L21/76825 , H01L21/76837 , H01L29/66545
摘要： Disposable gate structures are formed on a semiconductor substrate. A planarization dielectric layer is deposited over the disposable gate structures and planarized to provide a top surface that is coplanar with top surface of the disposable gate structures. The planarization dielectric layer at this point includes gap-fill keyholes between narrowly spaced disposable gate structures. A printable dielectric layer is deposited over the planarization dielectric layer to fill the gap-fill keyholes. Areas of the printable dielectric layer over the gap-fill keyholes are illuminated with radiation that cross-links cross-linkable bonds in the material of the printable dielectric layer. Non-crosslinked portions of the printable dielectric layer are subsequently removed selective to crosslinked portions of the printable dielectric layer, which fills at least the upper portion of each gate-fill keyhole. The disposable gate structures are removed to form gate cavities. The gate cavities are filled with a gate dielectric and a gate electrode.
摘要翻译：在半导体衬底上形成一次性栅极结构。平坦化电介质层沉积在一次性栅极结构上并且被平坦化以提供与一次性栅极结构的顶表面共面的顶表面。此时的平坦化电介质层包括狭缝间隔一次性栅极结构之间的间隙填充键孔。在平坦化介电层上沉积可印刷介电层以填充间隙填充键孔。在间隙填充键孔上的可印刷电介质层的区域被可印刷介电层的材料中交叉连接的辐射辐射照射。可打印介电层的非交联部分随后被选择性地移除到可印刷介电层的交联部分，该可印刷电介质层至少填充每个栅极填充孔眼的上部。去除一次性门结构以形成门腔。栅极腔填充有栅极电介质和栅电极。

8. 发明申请

US20120292598A1 EPITAXIAL SOURCE/DRAIN CONTACTS SELF-ALIGNED TO GATES FOR DEPOSITED FET CHANNELS 有权
标题翻译：外延源/漏极触点自定义到沉积FET通道的栅极
公开(公告)号：US20120292598A1
公开(公告)日：2012-11-22
申请号：US13565342
申请日：2012-08-02
申请人： Josephine B. Chang , Paul Chang , Vijay Narayanan , Jeffrey W. Sleight
发明人： Josephine B. Chang , Paul Chang , Vijay Narayanan , Jeffrey W. Sleight
IPC分类号： H01L29/775
CPC分类号： H01L51/0545 , B82Y10/00 , H01L27/283 , H01L51/0012 , H01L51/0048 , H01L51/0525
摘要： A method of forming a self-aligned device is provided and includes depositing carbon nanotubes (CNTs) onto a crystalline dielectric substrate, isolating a portion of the crystalline dielectric substrate encompassing a location of the CNTs, forming gate dielectric and gate electrode gate stacks on the CNTs while maintaining a structural integrity thereof and forming epitaxial source and drain regions in contact with portions of the CNTs on the crystalline dielectric substrate that are exposed from the gate dielectric and gate electrode gate stacks.
摘要翻译：提供了一种形成自对准器件的方法，包括将碳纳米管（CNT）沉积到晶体介质衬底上，隔离包含CNT位置的晶体介质衬底的一部分，在栅极电介质层和栅电极栅叠层 CNT同时保持其结构完整性，并且形成外延源极和漏极区域，其与从栅极介电层和栅电极栅极叠层暴露的晶体介质衬底上的CNT的部分接触。

9. 发明申请

US20120274397A1 METHOD AND SYSTEM FOR A PROCESS SENSOR TO COMPENSATE SOC PARAMETERS IN THE PRESENCE OF IC PROCESS MANUFACTURING VARIATIONS 失效
标题翻译：用于在IC工艺制造变化中存在SOC过程传感器补偿SOC参数的方法和系统
公开(公告)号：US20120274397A1
公开(公告)日：2012-11-01
申请号：US13545580
申请日：2012-07-10
申请人： Stephen Chi-Wang Au , Arya Behzad , Paul Chang
发明人： Stephen Chi-Wang Au , Arya Behzad , Paul Chang
IPC分类号： G05F3/02
CPC分类号： H03F3/45475 , H03F2203/45048
摘要： Certain aspects of a method and system for a process sensor to compensate SoC parameters in the presence of IC process manufacturing variations are disclosed. Aspects of one method may include determining an amount of process variation associated with at least one transistor within a single integrated circuit. The determined amount of process variation may be compensated by utilizing a process dependent current, a bandgap current, and a current associated with a present temperature of the transistor. The process dependent current, the bandgap current and the current associated with the present temperature of the transistor may be combined to generate an output current. A voltage generated across a variable resistor may be determined based on the generated output current.
摘要翻译：公开了用于在存在IC工艺制造变化的情况下补偿SoC参数的工艺传感器的方法和系统的某些方面。一种方法的方面可以包括确定与单个集成电路内的至少一个晶体管相关联的工艺变化量。可以通过利用与工艺相关的电流，带隙电流和与晶体管的当前温度相关联的电流来补偿确定的工艺变化量。过程相关电流，带隙电流和与晶体管的当前温度相关联的电流可以被组合以产生输出电流。可以基于产生的输出电流来确定可变电阻器两端产生的电压。

10. 发明授权

US08239790B2 Methods and system for analysis and management of parametric yield 有权
标题翻译：参数收益分析与管理方法与系统
公开(公告)号：US08239790B2
公开(公告)日：2012-08-07
申请号：US13216362
申请日：2011-08-24
申请人： James A. Culp , Paul Chang , Dureseti Chidambarrao , Praveen Elakkumanan , Jason Hibbeler , Anda C. Mocuta
发明人： James A. Culp , Paul Chang , Dureseti Chidambarrao , Praveen Elakkumanan , Jason Hibbeler , Anda C. Mocuta
IPC分类号： G06F17/50
CPC分类号： G01R31/26 , G06F17/5045
摘要： Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.
摘要翻译：对晶体管的导通电流和截止电流对晶体管的物理设计选择的参数性能的影响。设计参数的影响被纳入测量平均电流和平均截止电流的预测偏差的参数以及测量导通电流和截止电流分布的偏差预测增加的参数。可以在单元级别，块级或芯片级别进行统计，以在设计阶段优化芯片设计，或者在制造期间或在观察到抑制参数产量之后预测参数产量的变化。此外，可以逐区域地预测参数产量和电流水平，并与观察到的热发射进行比较，以确定芯片中的任何异常区域，以便在芯片设计中的任何错误中进行检测和校正。

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