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1. 发明授权

US06687853B1 Checkpointing for recovery of channels in a data processing system 有权
标题翻译：检查点以恢复数据处理系统中的通道
公开(公告)号：US06687853B1
公开(公告)日：2004-02-03
申请号：US09583670
申请日：2000-05-31
申请人： Patricia G. Driever , John R. Flanagan , Paul S. Frazer , Catherine C. Huang , Bernhard Laubli , Louis W. Ricci
发明人： Patricia G. Driever , John R. Flanagan , Paul S. Frazer , Catherine C. Huang , Bernhard Laubli , Louis W. Ricci
IPC分类号： G06F1100
CPC分类号： G06F11/1443
摘要： A method, program product and apparatus for checkpointing for recovery of channels in a data processing system using a protocol which allows for multiplexing operations at the frame level and streaming of commands and data. For unsuccessful retries, the correct primary CCW address is reported back to software indicating the extent to which the channel completed modifying and accessing S/390 storage.
摘要翻译：一种使用允许在帧级复用操作和命令和数据流的协议的数据处理系统中的信道恢复检查点的方法，程序产品和装置。对于不成功的重试，将正确的主CCW地址报告回软件，指示通道完成修改和访问S / 390存储的程度。

2. 发明申请

US20120089861A1 INTER-PROCESSOR FAILURE DETECTION AND RECOVERY 有权
标题翻译：处理器故障检测和恢复
公开(公告)号：US20120089861A1
公开(公告)日：2012-04-12
申请号：US12902501
申请日：2010-10-12
申请人： Charles S. Cardinell , Roger G. Hathorn , Bernhard Laubli , Timothy J. Van Patten
发明人： Charles S. Cardinell , Roger G. Hathorn , Bernhard Laubli , Timothy J. Van Patten
IPC分类号： G06F11/07 , G06F11/00
CPC分类号： G06F11/0757 , G06F11/0724
摘要： An approach to detecting processor failure in a multi-processor environment is disclosed. The approach may include having each CPU in the system responsible for monitoring another CPU in the system. A CPUn reads a timestampn+1 created by CPUn+1 which CPUn is monitoring from a shared memory location. The CPUn reads its own timestampn and compares the two timestamps to calculate a delta value. If the delta value is above a threshold, the CPUn determines that CPUn+1 has failed and initiates error handling for the CPUs in the system. One CPU may be designated a master CPU, and be responsible for beginning the error handling process. In such embodiments, the CPUn may initiate error handling by notifying the master CPU that CPUn+1 has failed. If CPUn+1 is the master CPU, the CPUn may take additional steps to initiate error handling, and may broadcast a non-critical interrupt to all CPUs, triggering error handling.
摘要翻译：公开了一种在多处理器环境中检测处理器故障的方法。该方法可以包括使系统中的每个CPU负责监视系统中的另一个CPU。 CPUn读取CPUn + 1创建的时间戳+1，CPUn正在从共享内存位置进行监控。 CPUn读取自己的时间戳，并比较两个时间戳来计算增量值。如果增量值高于阈值，CPUn确定CPUn + 1失败，并启动系统中CPU的错误处理。一个CPU可能被指定为主CPU，并负责开始错误处理过程。在这种实施例中，CPUn可以通过通知主CPU CPUn + 1失败来启动错误处理。如果CPUn + 1是主CPU，CPUn可能会采取额外的步骤来启动错误处理，并可能会向所有CPU广播非关键中断，从而触发错误处理。

3. 发明授权

US08089889B2 Adapter port configuration 失效
标题翻译：适配器端口配置
公开(公告)号：US08089889B2
公开(公告)日：2012-01-03
申请号：US10992539
申请日：2004-11-18
申请人： Mark Steven Bayus , Roger Gregory Hathorn , Bernhard Laubli
发明人： Mark Steven Bayus , Roger Gregory Hathorn , Bernhard Laubli
IPC分类号： G01R31/08
CPC分类号： H04L41/082
摘要： An apparatus for configuring a port in a multi-port communication adapter includes a quiesce module quiescing communications at one or more first I/O ports of a multi-port communication adapter while allowing communications at one or more second I/O ports of the multi-port communication adapter. A path module removes one or more logical paths between the one or more first I/O ports and one or more remote adapters in anticipation of taking the one or more first I/O ports offline. The offline module takes offline the one or more first I/O ports. The update module updates a port resource of the one or more first I/O ports while allowing a concurrent communication on the one or more second I/O ports of the multi-port communication adapter.
摘要翻译：用于在多端口通信适配器中配置端口的装置包括静止模块，静态地在多端口通信适配器的一个或多个第一I / O端口处进行通信，同时允许在多端口通信适配器的一个或多个第二I / O端口 - 端口通信适配器。路径模块在预期将一个或多个第一I / O端口离线的情况下，移除一个或多个第一I / O端口与一个或多个远程适配器之间的一个或多个逻辑路径。离线模块使一个或多个第一个I / O端口脱机。更新模块更新一个或多个第一I / O端口的端口资源，同时允许多端口通信适配器的一个或多个第二I / O端口上的并发通信。

4. 发明授权

US5210828A Multiprocessing system with interprocessor communications facility 失效
标题翻译：具有处理器间通信设施的多处理系统
公开(公告)号：US5210828A
公开(公告)日：1993-05-11
申请号：US504764
申请日：1990-04-04
申请人： Timothy V. Bolan , Josephine A. Boston , George A. Fax , Donald J. Hanrahan , Bernhard Laubli , David A. Ring , Alfred T. Rundle , David J. Shippy
发明人： Timothy V. Bolan , Josephine A. Boston , George A. Fax , Donald J. Hanrahan , Bernhard Laubli , David A. Ring , Alfred T. Rundle , David J. Shippy
IPC分类号： G06F15/167
CPC分类号： G06F15/167
摘要： A plurality of processors are connected to the interprocessor communications facility in the multiprocessing system of the invention. The interprocessor communications facility has arbitration circuitry, mailbox circuitry, and processor interrupt circuitry. The interprocessor communications facility of the invention is centralized and does not require the use of main storage. This enables processors to communicate with each other in a fast and efficient manner. The arbitration circuitry prevents simultaneous access of the interprocessor communications facility by more than one processor, and decodes the commands sent from the processors and routes them to the processor interrupt circuitry or to the mailbox circuitry, depending on the command. The mailbox circuitry of the invention receives messages from sending processors and provides them to the intended receiving processors in a safe and secure manner. The processor interrupt circuitry facilitates the interprocessor communications process by handling interprocessor interrupts.
摘要翻译：多个处理器连接到本发明的多处理系统中的处理器间通信设施。处理器间通信设施具有仲裁电路，邮箱电路和处理器中断电路。本发明的处理器间通信设施是集中式的，不需要使用主存储器。这使得处理器能够以快速和有效的方式相互通信。仲裁电路防止多个处理器同时访问处理器间通信设施，并根据命令解码从处理器发送的命令并将它们路由到处理器中断电路或邮箱电路。本发明的邮箱电路从发送处理器接收消息，并以安全和可靠的方式将它们提供给预期的接收处理器。处理器中断电路通过处理处理器间中断来促进处理器之间的通信过程。

5. 发明授权

US09075720B2 Locking a cache line for write operations on a bus 有权
标题翻译：在总线上锁定缓存行以进行写操作
公开(公告)号：US09075720B2
公开(公告)日：2015-07-07
申请号：US12897555
申请日：2010-10-04
申请人： Stephen L. Blinick , Charles S. Cardinell , Roger G. Hathorn , Bernhard Laubli , Miguel A. Montoya , Timothy J. Van Patten
发明人： Stephen L. Blinick , Charles S. Cardinell , Roger G. Hathorn , Bernhard Laubli , Miguel A. Montoya , Timothy J. Van Patten
IPC分类号： G06F12/00 , G06F12/08 , G06F12/12
CPC分类号： G06F12/0879 , G06F12/0802 , G06F12/0804 , G06F12/0833 , G06F12/0891 , G06F12/1009 , G06F12/127 , G06F12/1475 , G06F2212/1052 , G06F2212/303 , G06F2212/604 , G06F2212/62 , G06F2212/657
摘要： Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cache line from being cast out. Data is written to the cache line. All the data in the cache line is flushed to the target address over a bus in response to completing writing to the cache line.
摘要翻译：提供了一种用于在总线上锁定用于突发写入操作的高速缓存行的计算机程序产品，系统和方法。在目标地址的缓存中分配高速缓存行。为缓存行设置锁定，其中设置锁定防止高速缓存行中的数据被抛出。数据被写入缓存行。响应于完成对高速缓存线的写入，高速缓存行中的所有数据都通过总线刷新到目标地址。

6. 发明申请

US20120084514A1 LOCKING A CACHE LINE FOR WRITE OPERATIONS ON A BUS 有权
标题翻译：锁定用于在总线上进行写操作的高速缓存线
公开(公告)号：US20120084514A1
公开(公告)日：2012-04-05
申请号：US12897555
申请日：2010-10-04
申请人： Stephen L. Blinick , Charles S. Cardinell , Roger G. Hathorn , Bernhard Laubli , Miguel A. Montoya , Timothy J. Van Patten
发明人： Stephen L. Blinick , Charles S. Cardinell , Roger G. Hathorn , Bernhard Laubli , Miguel A. Montoya , Timothy J. Van Patten
IPC分类号： G06F12/08 , G06F13/24 , G06F12/00
CPC分类号： G06F12/0879 , G06F12/0802 , G06F12/0804 , G06F12/0833 , G06F12/0891 , G06F12/1009 , G06F12/127 , G06F12/1475 , G06F2212/1052 , G06F2212/303 , G06F2212/604 , G06F2212/62 , G06F2212/657
摘要： Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cache line from being cast out. Data is written to the cache line. All the data in the cache line is flushed to the target address over a bus in response to completing writing to the cache line.
摘要翻译：提供了一种用于在总线上锁定用于突发写入操作的高速缓存行的计算机程序产品，系统和方法。在目标地址的缓存中分配高速缓存行。为缓存行设置锁定，其中设置锁定防止高速缓存行中的数据被抛出。数据被写入缓存行。响应于完成对高速缓存线的写入，高速缓存行中的所有数据都通过总线刷新到目标地址。

7. 发明申请

US20060165116A1 Apparatus, system, and method for adapter port configuration 失效
标题翻译：适配器端口配置的设备，系统和方法
公开(公告)号：US20060165116A1
公开(公告)日：2006-07-27
申请号：US10992539
申请日：2004-11-18
申请人： Mark Bayus , Roger Hathorn , Bernhard Laubli
发明人： Mark Bayus , Roger Hathorn , Bernhard Laubli
IPC分类号： H04J1/16 , H04L12/66
CPC分类号： H04L41/082
摘要： An apparatus, system, and method are disclosed for configuring a port in a multi-port communication adapter. The apparatus includes an offline module and an update module. The offline module takes offline a first port of a multi-port communication adapter. The update module updates a port resource of the first port while allowing a concurrent communication on a second port of the multi-port communication adapter. The port resource may include a port topology and/or a port protocol. Furthermore, the apparatus may include an online module to put the first port online in response to the port resource update. Advantageously, the apparatus updates the port resource and configures the selected port according to the port resource attributes without interrupting concurrent communications, if any, on the other ports of the adapter.
摘要翻译：公开了一种用于配置多端口通信适配器中的端口的装置，系统和方法。该装置包括离线模块和更新模块。离线模块脱机多端口通信适配器的第一个端口。更新模块更新第一端口的端口资源，同时允许多端口通信适配器的第二端口上的并发通信。端口资源可以包括端口拓扑和/或端口协议。此外，该装置可以包括在线模块以响应于端口资源更新来将第一端口联机。有利地，设备更新端口资源并根据端口资源属性配置所选择的端口，而不中断适配器的其他端口上的并发通信（如果有的话）。

8. 发明授权

US5450073A Controlling power sequencing of a control unit in an input/output system 失效
标题翻译：控制输入/输出系统中控制单元的电源排序
公开(公告)号：US5450073A
公开(公告)日：1995-09-12
申请号：US178489
申请日：1994-01-06
申请人： Paul J. Brown , Joseph C. Elliott , Bernhard Laubli , Kenneth R. Lynch , William F. Micka
发明人： Paul J. Brown , Joseph C. Elliott , Bernhard Laubli , Kenneth R. Lynch , William F. Micka
IPC分类号： G06F1/26 , H04Q1/00
CPC分类号： G06F1/26 , Y10T307/477 , Y10T307/753
摘要： A mechanism for controlling the powering-on and powering-off of control units in a data processing system having a plurality of channels, a plurality of control units, and a communications network of links for linking the channels to the control units. Each control unit includes a power-control table for recording power-control allegiance of the control unit to the channels. Where a control unit receives a power-on command from a channel, it records the identity of the channel in its power-control table. When a channel orders a control unit to power-off, the control unit checks to see if it owes power-control allegiance to the ordering channel. If it does, the control unit deletes the identity from its power-control table. The control unit will not power-off unless its power-control table is empty, indicating that it does not owe allegiance to any other channel.
摘要翻译：一种用于控制具有多个通道的数据处理系统中的控制单元的通电和断电的机构，多个控制单元和用于将通道链接到控制单元的通信通信网络。每个控制单元包括用于将控制单元的功率控制效用记录到通道的功率控制表。在控制单元从信道接收上电命令的情况下，在其功率控制表中记录通道的标识。当一个通道命令一个控制单元断电时，控制单元检查它是否对功率控制效忠于订购通道。如果是，则控制单元从其功率控制表中删除身份。除非控制单元的电源控制表为空，否则控制单元将不会断电，表示不对其他通道造成效忠。

9. 发明授权

US08935511B2 Determining processor offsets to synchronize processor time values 有权
标题翻译：确定处理器偏移量以同步处理器时间值
公开(公告)号：US08935511B2
公开(公告)日：2015-01-13
申请号：US12902047
申请日：2010-10-11
申请人： Charles S. Cardinell , Bernhard Laubli , Timothy J. Van Patten
发明人： Charles S. Cardinell , Bernhard Laubli , Timothy J. Van Patten
IPC分类号： G06F1/14 , G06F11/16
CPC分类号： G06F9/30087 , G06F1/12 , G06F1/14 , G06F11/1675
摘要： Provided are a computer program product, system, and method for determining processor offsets to synchronize processor time values. A determination is made of a master processor offset from one of a plurality of time values of the master processor and a time value of one of the slave processors. A determination is made of slave processor offsets, wherein each slave processor offset is determined from the master processor offset, one of the time values of the master processor, and a time value of the slave processor. A current time value of the master processor is adjusted by the master processor offset. A current time value of each of the slave processors is adjusted by the slave processor offset for the slave processor whose time value is being adjusted.
摘要翻译：提供了一种用于确定处理器偏移以同步处理器时间值的计算机程序产品，系统和方法。确定主处理器偏离主处理器的多个时间值之一和从属处理器之一的时间值的偏移。确定从处理器偏移，其中从主处理器偏移确定每个从处理器偏移，主处理器的时间值之一和从属处理器的时间值之一。主处理器的当前时间值由主处理器偏移量调整。每个从属处理器的当前时间值由对其时间值正在调整的从属处理器的从属处理器偏移进行调整。

10. 发明授权

US08850262B2 Inter-processor failure detection and recovery 有权
标题翻译：处理器间故障检测和恢复
公开(公告)号：US08850262B2
公开(公告)日：2014-09-30
申请号：US12902501
申请日：2010-10-12
申请人： Charles S. Cardinell , Roger G. Hathorn , Bernhard Laubli , Timothy J. Van Patten
发明人： Charles S. Cardinell , Roger G. Hathorn , Bernhard Laubli , Timothy J. Van Patten
IPC分类号： G06F11/00 , G06F11/07
CPC分类号： G06F11/0757 , G06F11/0724
摘要： An approach to detecting processor failure in a multi-processor environment is disclosed. The approach may include having each CPU in the system responsible for monitoring another CPU in the system. A CPUn reads a timestampn+1 created by CPUn+1 which CPUn is monitoring from a shared memory location. The CPUn reads its own timestampn and compares the two timestamps to calculate a delta value. If the delta value is above a threshold, the CPUn determines that CPUn+1 has failed and initiates error handling for the CPUs in the system. One CPU may be designated a master CPU, and be responsible for beginning the error handling process. In such embodiments, the CPUn may initiate error handling by notifying the master CPU that CPUn+1 has failed. If CPUn+1 is the master CPU, the CPUn may take additional steps to initiate error handling, and may broadcast a non-critical interrupt to all CPUs, triggering error handling.
摘要翻译：公开了一种在多处理器环境中检测处理器故障的方法。该方法可以包括使系统中的每个CPU负责监视系统中的另一个CPU。 CPUn读取CPUn + 1创建的时间戳+1，CPUn正在从共享内存位置进行监控。 CPUn读取自己的时间戳，并比较两个时间戳来计算增量值。如果增量值高于阈值，CPUn确定CPUn + 1失败，并启动系统中CPU的错误处理。一个CPU可能被指定为主CPU，并负责开始错误处理过程。在这种实施例中，CPUn可以通过通知主CPU CPUn + 1失败来启动错误处理。如果CPUn + 1是主CPU，CPUn可能会采取额外的步骤来启动错误处理，并可能会向所有CPU广播非关键中断，从而触发错误处理。

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